IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`SPTS TECHNOLOGIES LTD.
`Petitioner
`
`v.
`
`PLASMA-THERM LLC
`Patent Owner
`
`Inter Partes Review No.: IPR2017-01314
`U.S. Patent No. 8,980,764
`
`PATENT OWNER’S PRELIMINARY RESPONSE TO PETITION FOR
`INTER PARTES REVIEW OF U.S. PATENT NO. 8,980,764 UNDER 37
`C.F.R. § 42.107
`
`

`

`TABLE OF CONTENTS
`
`TABLE OF CONTENTS .............................................................................................i
`TABLE OF AUTHORITIES..................................................................................... iii
`LIST OF EXHIBITS ...................................................................................................v
`I.
`INTRODUCTION........................................................................................1
`II.
`TECHNOLOGY OVERVIEW .................................................................3
`A.
`Dicing Overview .............................................................................4
`B.
`Plasma Dicing ..................................................................................6
`III. THE ‘764 PATENT AND PROSECUTION HISTORY ..................9
`A.
`Overview of the ‘764 Patent..................................................................9
`B.
`Relevant Prosecution History..............................................................13
`PERSON OF ORDINARY SKILL IN THE ART..........................................14
`IV.
`CLAIM CONSTRUCTION ..........................................................................14
`V.
`VI. OVERVIEW OF ASSERTED REFERENCES..............................................18
`A.
`Sekiya ‘901 (U.S. Pub. No. 2004/0115901)....................................18
`B.
`Todorow (U.S. Pub. No. 2006/0000805).........................................21
`C.
`Nisany (U.S. Pub. No. 2009/0183583) ............................................24
`D.
`Ogasawara (U.S. Patent No. 7,411,384)..........................................26
`VII. PETITIONER HAS FAILED TO ESTABLISH A REASONABLE
`LIKELIHOOD THAT THE CHALLENGED CLAIMS ARE
`UNPATENTABLE .........................................................................................29
`A.
`The Cited References Relate To Completely Different Aspects Of The
`Fabrication Process Than The Challenged Claims .............................29
`1.
`Sekiya ‘901................................................................................30
`2.
`Todorow ....................................................................................31
`3.
`Nisany And Ogasawara.............................................................33
`Person Of Skill In The Art Would Not Combine The Cited References
`As Proposed By Petitioner ..................................................................34
`1.
`A POSITA Would Not Have Combined The Stabilizer Of
`Todorow With Sekiya ‘901.......................................................35
`i
`
`B.
`
`

`

`b.
`
`There Is No Need For The Stabilizer Of Todorow In
`Sekiya ‘901 .....................................................................36
`Petitioner’s Proposed Combination Would Render The
`Prior Art Unsatisfactory For Its Intended Purpose.........37
`Petitioner Relies On Impermissible Hindsight...............39
`c.
`A POSITA Would Not Have Combined The Lift Mechanism Of
`Todorow With Sekiya ‘901.......................................................41
`A POSITA Would Not Have Combined The Lift Mechanisms
`Of Nisany Or Ogasawara With Sekiya ‘901 and Todorow ......44
`Petitioner’s Other Rationales For Combining The Cited
`References Are Insufficient ......................................................47
`VIII. THE DECLARATION OF DR. JOHN E. SPENCER SHOULD BE GIVEN
`LITTLE OR NO WEIGHT.............................................................................50
`IX. CONCLUSION..............................................................................................51
`
`2.
`
`3.
`
`4.
`
`IPR2017-01314
`U.S. Patent No. 8,980,764
`
`a.
`
`ii
`
`

`

`TABLE OF AUTHORITIES
`
`Cases
`
`ACTV, Inc. v. Walt Disney Co.,
`346 F.3d 1082 (Fed. Cir. 2003) .........................................................................16
`
`DePuy Spine, Inc. v. Medtronic Sofamor Danek, Inc.,
`567 F.3d 1314 (Fed. Cir. 2009) ............................................................................43
`
`Epos Techs. Ltd. v. Pegasus Techs. Ltd.,
`766 F.3d 1338 (Fed. Cir. 2014) .........................................................................18
`
`Ericsson, Inc. v. D-Link Sys., Inc.,
`773 F.3d 1201 (Fed. Cir. 2014) .........................................................................14
`
`Gen. Elec. Co. v. Tas Energy, Inc.,
`IPR2014-00163, Paper 11 (PTAB May 13, 2014) ...............................................50
`
`GPNE Corp. v. Apple Inc.,
`830 F.3d 1365 (Fed. Cir. 2016) .........................................................................15
`
`In re ICON Health & Fitness, Inc.,
`496 F.3d 1374 (Fed. Cir. 2007) ............................................................................44
`
`In re Kahn,
`441 F.3d 977 (Fed. Cir. 2006) ..............................................................................29
`
`In re Translogic Tech., Inc.,
`504 F.3d 1249 (Fed. Cir. 2007) .........................................................................14
`
`InTouch Techs., Inc. v. VGO Commc'ns, Inc.,
`751 F.3d 1327 (Fed. Cir. 2014) ......................................................................40, 47
`
`KSR Int'l Co. v. Teleflex Inc.,
`550 U.S. 398 (2007)..............................................................................................29
`
`iii
`
`

`

`IPR2017-01314
`U.S. Patent No. 8,980,764
`
`Nichia Corp. v. Everlight Americas, Inc.,
`855 F.3d 1328 (Fed. Cir. 2017) ..........................................................41, 46, 47, 48
`
`Phillips v. AWH Corp.,
`415 F.3d 1303 (Fed. Cir. 2005) ...................................................................16, 18
`
`Securus Techs., Inc. v. Global Tel*link Corp.,
`2017 WL 2992516 (Fed. Cir. July 14, 2017)........................................................41
`
`Trivascular, Inc. v. Samuels,
`812 F.3d 1056 (Fed. Cir. 2016) ............................................................................49
`
`Vitronics Corp. v. Conceptronic, Inc.,
`90 F.3d 1576 (Fed. Cir. 1996)............................................................................17
`
`Vivid Techs., Inc. v. Am. Sci. & Eng’g, Inc.,
`200 F.3d 795 (Fed. Cir. 1999)............................................................................15
`
`Wowza Media Sys., LLC v. Adobe Sys., Inc.,
`IPR2013-00054, Paper 16 (PTAB July 13, 2013) ................................................50
`
`Rules
`
`37 C.F.R. § 42.100(b) ............................................................................................14
`
`Fed. R. Evid. 702......................................................................................................51
`
`iv
`
`

`

`IPR2017-01314
`U.S. Patent No. 8,980,764
`
`LIST OF EXHIBITS
`
`Exhibit No.
`2001
`2002
`2003
`
`2004
`2005
`
`2006
`
`Description
`Declaration of Stanley Shanfield, Ph.D.
`Curriculum Vitae of Stanley Shanfield, Ph.D
`Lei, et al., “Die singulation technologies for advanced packaging:
`A critical review”
`U.S. Patent No. 8,206,829 to Sun et al.
`Excerpts of Liebermann, et al., “Principles of Plasma Discharges
`and Materials Processing”
`Chapman, et al., “Optimized Electromagnetic Coil Theory”
`
`v
`
`

`

`I.
`
`INTRODUCTION
`Petitioner’s lone asserted ground of invalidity is a classic example of
`
`hindsight reconstruction that the Board and the Federal Circuit have long rejected.
`
`Petitioner cherry picks the recited claim elements from four unrelated references
`
`with no regard for how or why a person of skill in the art (POSITA) would or could
`
`combine them. Tellingly, the reference relied on by Petitioner for disclosing the
`
`majority of the recited claim elements, was already considered by the Examiner
`
`during prosecution. Petitioner’s haphazard attempt to pick and choose elements
`
`from four different references fails to establish that one or more of the challenged
`
`claims are more likely than not invalid.
`
`First, none of the four references is directed to solving the same problem as
`
`the challenged claims of U.S. Patent No. 8,980,764 (“the ‘764 patent”). The ‘764
`
`patent
`
`is directed to a method of conducting plasma dicing and handling a
`
`semiconductor wafer that is on tape on a frame during plasma dicing. By contrast,
`
`the cited references relate to a variety of other semiconductor processing steps, and
`
`do not attempt to solve the same problem as the ‘764 patent. Moreover, the four
`
`references address four separate fabrication issues that are unrelated to each other.
`
`A POSITA would have no reason to consult any of the cited references in
`
`developing a plasma dicing system, nor would a POSITA consult any of the four
`
`cited references to modify any of the other cited references.
`
`1
`
`

`

`IPR2017-01314
`U.S. Patent No. 8,980,764
`
`Second, Petitioner glosses over critical technical details which, as a POSITA
`
`would understand, demonstrate that
`
`there would be no need to combine the
`
`elements in the way Petitioner proposes.
`
`In fact, Petitioner’s proposed
`
`combinations would render the primary reference unsuitable for its intended
`
`purpose.
`
`In particular, contrary to Petitioner’s argument, a POSITA would have
`
`no reason to combine the plasma stabilizer of Todorow with the plasma system of
`
`Sekiya ‘901 because the plasma generated in Sekiya ‘901 is already stable, unlike
`
`the plasma generated in Todorow. Moreover, the plasma stabilizer of Todorow
`
`would not function to reduce the amount of heat generated by the plasma, which
`
`would damage the wafer and/or the tape holding the wafer in Sekiya ‘901, and
`
`render Sekiya ‘901 unsuitable for its intended purpose. In addition, the lift pins of
`
`Todorow would also damage the thinned wafer of Sekiya ‘901 by directly
`
`contacting the backside of the wafer.
`
`Third, Petitioner improperly relies on the Nisany and Ogasawara references,
`
`which relate to unrelated testing and inspection steps. A POSITA would not be
`
`aware of the specific handling techniques used in testing and inspection.
`
`In
`
`addition, the lifting mechanisms used in Nisany and Ogasawara would not function
`
`in the plasma vacuum chamber used in plasma dicing.
`
`Fourth, Petitioner relies on vague, boilerplate rationales for combining the
`
`four references, without regard for how or why a POSITA would make such a
`
`2
`
`

`

`IPR2017-01314
`U.S. Patent No. 8,980,764
`
`combination. Contrary to Petitioner’s arguments, the individual components would
`
`not function as expected when used in a plasma chamber, nor would using the
`
`claimed lift mechanism be one of a finite amount of predictable solutions.
`
`Petitioner’s vague arguments are insufficient to establish a motivation to combine
`
`the references.
`
`II.
`
`TECHNOLOGY OVERVIEW
`
`Integrated circuits and other semiconductor devices are found in a wide array
`
`of devices that people use every day from computers to refrigerators. The
`
`manufacturing of semiconductor devices is a very complex process that includes
`
`dozens, if not hundreds, of processing steps. Semiconductor devices are fabricated
`
`on substrates that are in form of thin wafers. Silicon is commonly used as the
`
`substrate material, but other materials may also be used. The bare wafer repeatedly
`
`undergoes a series of processing steps including applying a photoresist layer,
`
`photolithography, depositing thin films, etching,
`
`removing the photoresist,
`
`diffusion and implantation, and chemo-mechanical polishing.
`
`(See Ex. 2001 at
`
`¶ 23). Inspection and electrical measurement steps are interspersed throughout this
`
`process. (See id.). By repeating these processes many times, layers or devices and
`
`circuits are formed on the wafer. (See id. at Fig. 1, ¶ 23).
`
`The etching step in the fabrication process is typically plasma etching, in
`
`which the wafer is placed in a vacuum chamber and exposed to a highly reactive
`
`3
`
`

`

`IPR2017-01314
`U.S. Patent No. 8,980,764
`
`plasma that removes thin films (i.e., having a thickness of less than 1 micron) of
`
`materials such as poly-silicon, silicon nitride, silicon dioxide, various metals, or
`
`thin layers of photoresist.
`
`(See id. at ¶ 24). Conventional plasma etching
`
`equipment used in the fabrication process is specifically designed for handling
`
`wafers without mounting hardware or mounting tape.
`
`(See id.). The processing
`
`chamber and plasma source are also configured to optimize the wafer temperature,
`
`reaction chemistry, and reaction rate needed to remove very thin layers. (See id.).
`
`The inspection and testing steps conducted during fabrication are done under
`
`normal atmospheric conditions (as opposed to the vacuum conditions of the etching
`
`step), and use specific automated handling systems. (See id. at ¶ 25). For example,
`
`inspection systems use transport systems that precisely position the wafer for
`
`inspection by optical microscopes. (See id.). Likewise, wafer chucks designed for
`
`use at atmospheric conditions are used to support the wafer during testing. Once
`
`the fabrication process is complete, the wafer is ready for dicing, packaging, and
`
`final testing. (See id. at ¶¶ 26-27).
`
`A.
`
`Dicing Overview
`
`When the wafer has completed front-side processing, the top surface of the
`
`wafer is typically covered with a repeated pattern of integrated circuits. After
`
`front-side electrical testing, the wafer begins a series of back-side processing steps
`
`that ultimately separate, or “dice” the wafer into individual integrated circuit chips.
`
`4
`
`

`

`IPR2017-01314
`U.S. Patent No. 8,980,764
`
`(See id. at ¶ 27). First, an adhesive is applied to the backside surface of the wafer,
`
`and the wafer and adhesive are laminated onto a flexible polymer tape, or
`
`alternatively the polymer tape already has adhesive on it. (See id.). The outer edge
`
`of the polymer tape is then mounted to a metal tape frame to allow for easier
`
`handling. (See id.). A mechanical saw, or alternatively a laser, is typically used to
`
`cut the wafer along the “streets” between the individual chips or “die.” (See id. at
`
`¶ 28). Prior to sawing the wafer, or cutting the wafer with a laser, a removable
`
`protective film is often applied to the front side of the wafer to prevent sawing
`
`debris and fluid used for cooling the saw from damaging the front-side circuits.
`
`(See id.). Alternatively, a fluid may be used when sawing to wash away debris and
`
`provide cooling. (See id.). After the wafer is diced, the separated die are removed
`
`from the tape for packaging. (See id.).
`
`Mechanical sawing, however, suffers from a number of drawbacks. For
`
`example, the process can be relatively slow because the saw must cut each street
`
`one by one until the entire wafer was diced. (See id. at ¶ 29). In addition, damage
`
`to the die frequently occurs as a result of the mechanical cutting. Therefore, a new
`
`dicing process was developed in which plasma was used to chemically etch the
`
`wafer along the streets between the die. (See id.). Plasma dicing provides several
`
`advantages over mechanical dicing, such as etching all streets simultaneously,
`
`5
`
`

`

`IPR2017-01314
`U.S. Patent No. 8,980,764
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`increasing the number of die per wafer by etching narrower streets, and reducing
`
`damage to the chips. (See id. at ¶ 30).
`
`To facilitate migration of manufacturers from a traditional mechanical
`
`cutting method for die separation to plasma dicing, the plasma dicing process of the
`
`‘764 patent uses the same preparation of the wafer as mechanical cutting for back
`
`end processing, i.e., a full thickness wafer is mounted on backside grinding tape,
`
`and uniformly ground to a reduced thickness.
`
`(See id. at ¶ 32).
`
`In one
`
`embodiment, the front side of the thinned wafer is then patterned with a masking
`
`layer, such as a photoresist, in order to define the streets between the individual
`
`die, and the wafer is mounted on flexible polymer tape.
`
`(See id. at ¶ 30). The
`
`periphery of the tape is then mounted to a metal frame.
`
`(See id.). After being
`
`thinned and mounted on the tape within the frame, the mounted wafer within a
`
`frame is placed in a vacuum chamber and is subjected to a substantially anisotropic
`
`high rate silicon plasma etch, which etches away, or removes, the exposed portions
`
`of the wafer between the individual chips.
`
`(See id.).
`
`If the streets were defined
`
`with a photoresist, the photoresist may be removed, and the individual chips are
`
`removed from the tape for packaging.
`
`B.
`
`Plasma Dicing
`
`Plasma used in semiconductor processing is typically generated by applying
`
`a radio-frequency (RF) or microwave electromagnetic field to a mixture of gases
`
`6
`
`

`

`IPR2017-01314
`U.S. Patent No. 8,980,764
`
`under vacuum. (See id. at ¶ 31). The plasma contains some fraction of electrically
`
`charged ionized molecular species, or “ions.” (See id.). The ions are reactive and
`
`energetic plasma components, and generate significant heat when they chemically
`
`react with the material to be etched.
`
`(See id.). Plasma also includes radical
`
`molecular species (“radicals”), which are electrically neutral but chemically
`
`unstable fragments of stable molecules. (See id.). Radicals are highly reactive, but
`
`are typically less energetic than ions, and can provide specific or selective chemical
`
`reactions with material to be etched or removed.
`
`(See id.). Because they are
`
`electrically neutral, radicals are not directly influenced by electrical potentials.
`
`(See id.).
`
`In order to be economically feasible, the silicon etch rate of a plasma dicing
`
`system must be high enough to produce diced chips at output rates similar to non-
`
`plasma systems. (See id. at ¶ 33). However, in achieving a high silicon etch rate,
`
`excessive heating must be avoided so that the wafer, the masking material forming
`
`the pattern of dicing cuts, and the supporting tape do not reach damaging
`
`temperature levels.
`
`(See id. at ¶ 34). For example, the ‘764 patent explains that
`
`above 100° C, the tape may deteriorate. (Ex. 1001 at col. 1:23-26).
`
`A wafer mounted on a tape frame and immersed in a reactive plasma will be
`
`heated by both ion bombardment and by absorption of light from the plasma. (Ex.
`
`2001 at ¶ 36). In particular, a high density plasma with a large number of reactants
`
`7
`
`

`

`IPR2017-01314
`U.S. Patent No. 8,980,764
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`has a small population of ionized, high energy molecules.
`
`(See id.). The wafer
`
`surface will absorb the energy carried in these species. (See id.). The plasma also
`
`emits light at various wavelengths that also contribute to the heat load of the wafer.
`
`(See id.). As the plasma density (i.e., density of ions and radicals) increases, the
`
`heat load applied to the wafer also increases. (See id.).
`
`In conventional plasma etching systems, it is well known that increasing the
`
`plasma density in the vicinity of the wafer increases the etch rate, but will also
`
`increase the temperature of the wafer. (See id. at ¶ 39). For applications requiring
`
`the removal of significant amounts of material, a process engineer skilled in plasma
`
`etching typically selects the plasma density to balance an adequate etch rate and
`
`acceptable wafer temperature.
`
`(See id.). When etching very thin layers of
`
`materials such as polysilicon, silicon oxide, etc. that are typically less than one
`
`micron thick, a high etch rate is not required. (See id.). But when dicing the wafer
`
`itself, which had a typical thickness of 675-775 microns at the time of invention of
`
`the ‘764 patent, a much higher etch rate is required so that the dicing time is not
`
`prohibitively slow.
`
`(See id. at ¶ 40). The ‘764 patent provides a plasma dicing
`
`solution that seeks to balance the competing objectives of achieving a sufficiently
`
`high etch rate, while maintaining a temperature that will not damage the wafer or
`
`tape.
`
`8
`
`

`

`IPR2017-01314
`U.S. Patent No. 8,980,764
`
`III.
`
`THE ‘764 PATENT AND PROSECUTION HISTORY
`
`A.
`
`Overview of the ‘764 Patent
`
`The ‘764 patent describes a method for plasma dicing a substrate mounted
`
`on tape on a frame where the substrate can have a semiconducting layer and/or a
`
`protective layer such as a photoresist layer that is patterned to define the individual
`
`chips on the substrate.
`
`(See e.g., Ex. 1001 at col. 5:3-8). A process chamber is
`
`provided, where the process chamber includes a wall with a plasma source that
`
`generates a plasma in the process chamber, the plasma source being adjacent to the
`
`wall of the process chamber. (See e.g., id. at col. 5:8-10, 9:63-64, Fig. 6). A work
`
`piece is formed by adhering the substrate to a support film and then mounting the
`
`substrate with the support film to a frame, as shown below.
`
`(See e.g., id. at col.
`
`9:33-35, Fig. 3 (shown below)).
`
`9
`
`

`

`IPR2017-01314
`U.S. Patent No. 8,980,764
`
`The work piece 1A is then placed onto a work piece support 13 for plasma
`
`processing. An RF power source 14 can be coupled to the work piece support 13
`
`to accelerate ions out of the generated plasma to facilitate dicing. A lifting
`
`mechanism 17 is provided where the lifting mechanism is incorporated into the
`
`work piece support 13 and the work piece is placed onto the work piece support 13
`
`using the lifting mechanism 17. The lifting mechanism 17 engages the frame 6 of
`
`the work piece, i.e., touches the portion of the work piece overlapped by the frame
`
`and provides no point contact to the substrate. (See e.g., id. at col. 5:21-24, 9:61-
`
`10:4, Figs. 4, 6).
`
`10
`
`

`

`IPR2017-01314
`U.S. Patent No. 8,980,764
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`The ‘764 patent also discloses a mechanical partition 25, or conductive
`
`screen, which can be provided below the plasma source 12 and above the work
`
`piece 1A, and can also be mounted to the wall of the process chamber. (See e.g.,
`
`id. at col. 12:29-40, Fig. 6 (shown below), Fig. 14).
`
`The mechanical partition can be made of conductive material such as
`
`aluminum, may be coated with a plasma resistant coating, and may include a
`
`plurality of holes which allows neutral species from the plasma to reach the
`
`substrate such that the etch rate is only slightly reduced and to further allow for
`
`mounting of the mechanical partition to the processing chamber.
`11
`
`(See e.g., id. at
`
`

`

`IPR2017-01314
`U.S. Patent No. 8,980,764
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`col. 12:34-38, Figs. 6, 14). Etching is then performed on the work piece through
`
`the generated plasma from the plasma source with the mechanical partition in place
`
`between the plasma source and the work piece. (See e.g., id. at col. 5:52-54, 12:34-
`
`38, Figs. 6, 14). Figure 14 is reproduced below:
`
`The ‘764 patent specification explains that
`
`the partition reduces ion
`
`bombardment on the work piece, but allows neutral radicals to pass through. (Id. at
`
`col. 12:29-37). In addition, the light generated by the plasma that would otherwise
`
`heat the work piece is either reflected or absorbed by the partition, which reduces
`
`the heating of the work piece. (Ex. 2001 at ¶ 48).
`
`12
`
`

`

`IPR2017-01314
`U.S. Patent No. 8,980,764
`
`B.
`
`Relevant Prosecution History
`
`The application that ultimately issued as the ‘764 patent was filed on
`
`February 11, 2013. A preliminary amendment, filed with the application, canceled
`
`claims 1-32 and added new claims 33-42, which included subject matter fully
`
`supported by the specification.
`
`In response to a Non-Final Office Action dated July 18, 2013, Applicant
`
`filed a Response on October 18, 2013, amending the claims, adding new claims,
`
`and submitting replacement drawings to address informal drawing objections.
`
`In response to a Final Office Action dated January 29, 2014, Applicant filed
`
`a Response further amending the claims. The claim amendments included the
`
`etching of the work piece through the high density plasma is done with the
`
`mechanical partition being positioned below the plasma source and above the work
`
`piece.
`
`Following an Advisory Action, Applicant filed a Request for Continued
`
`Examination on April 28, 2014,
`
`resubmitting the previously filed claim
`
`amendments.
`
`In response to a Non-Final Rejection on June 6, 2014, Applicant
`
`filed a subsequent Response on August 27, 2014. The Response included claim
`
`amendments directed towards “providing a lifting mechanism within the work
`
`piece support” where the work piece is placed on the work piece support “using the
`
`lifting mechanism, the lifting mechanism only touching a portion of the work piece
`
`13
`
`

`

`IPR2017-01314
`U.S. Patent No. 8,980,764
`
`overlapped by the frame.” A Notice of Allowance was issued on December 24,
`
`2014, which included an Examiner’s Amendment by which the term “only” was
`
`removed from claim 1.
`
`IV.
`
`PERSON OF ORDINARY SKILL IN THE ART
`
`Patent Owner submits that a person of ordinary skill in the art relevant to the
`
`‘764 patent would have at
`
`least a Master’s degree in electrical engineering,
`
`chemical engineering, materials science, physics or chemistry, or a similar field,
`
`and at least four years of experience in process development or process engineering
`
`related to plasma etching. Alternatively, this person would have a Ph.D. in physics,
`
`chemistry, electrical engineering, materials science or a similar field, along with
`
`two years of experience with process development or process engineering related
`
`to plasma etching. (See Ex. 2001 at ¶ 21).
`
`V. CLAIM CONSTRUCTION
`
`For purposes of inter partes review, “[a] claim in an unexpired patent
`
`shall be given its broadest reasonable construction in light of the specification
`
`of the patent in which it appears.”
`
`37 C.F.R. § 42.100(b). Claim terms
`
`generally are given their ordinary and customary meaning, as would be
`
`understood by one of ordinary skill in the art in the context of the entire
`
`disclosure. Ericsson, Inc. v. D-Link Sys., Inc., 773 F.3d 1201, 1218 (Fed. Cir.
`
`2014); In re Translogic Tech., Inc., 504 F.3d 1249, 1257 (Fed. Cir. 2007).
`
`14
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`

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`IPR2017-01314
`U.S. Patent No. 8,980,764
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`However, not all claim terms must be construed. Rather, claim terms only
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`need to be construed to the extent necessary to resolve the controversy. See
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`GPNE Corp. v. Apple Inc., 830 F.3d 1365, 1372 (Fed. Cir. 2016); Vivid
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`Techs., Inc. v. Am. Sci. & Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir. 1999).
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`Petitioner proposes constructions for five claim terms: (1) “plasma
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`source;” (2) “adjacent
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`to the wall of
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`the process chamber;” (3) “lift
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`mechanism;” (4) “touching a portion of the work piece overlapped by the
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`frame;” and (5) “mechanical partition.” Patent Owner does not believe that
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`any terms of
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`the challenged claims require construction to resolve the
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`obviousness question. Nevertheless, Patent Owner disagrees with Petitioner’s
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`proposed construction of “mechanical partition.”1
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`Petitioner’s proposal that “mechanical partition” should be interpreted
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`to mean “a physical structure located between and defining different interior
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`regions of the chamber” is overly narrow and improperly attempts to import
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`limitations from the specification into the claim. For example, the claim
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`language itself does not in any way suggest that the claimed partition must
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`“defin[e] different interior regions of the chamber.”
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`See Phillips v. AWH
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`1 Patent Owner expresses no opinion at this time regarding Petitioner’s proposed
`constructions of the remaining four claim terms, and reserves the right to propose
`alternative claim constructions should any such constructions become necessary to
`resolve the parties’ dispute.
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`Corp., 415 F.3d 1303, 1314 (Fed. Cir. 2005) (“the claims themselves provide
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`substantial guidance as to the meaning of particular claim terms”).
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`For
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`example, claim 1 of the ‘764 patent merely recites “providing a mechanical
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`partition positioned below the plasma source, said mechanical partition
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`positioned above the work piece,” and “said mechanical partition being
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`positioned below the plasma source and said mechanical partition be
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`positioned above the work piece.”
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`(Ex. 1001 at col. 16:8-15). The plain
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`language of the claim merely states that the mechanical partition is positioned
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`between the plasma source and the work piece, and does not require or even
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`suggest defining different regions of the chamber. See ACTV, Inc. v. Walt
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`Disney Co., 346 F.3d 1082, 1088 (Fed. Cir. 2003) (“the context of the
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`surrounding words of the claim also must be considered in determining the
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`ordinary and customary meaning of those terms”).
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`The ‘764 patent specification is consistent with the recitation of the
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`mechanical partition in the claims. Specifically, the specification explains
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`that the “conductive screen (25) . . . can be placed between the substrate (1)
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`and the plasma (7).” (Ex. 1001 at col. 12:29-32). Contrary to Petitioner’s
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`proposed construction, the specification contains no indication, implicitly or
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`explicitly, that the mechanical partition (i.e., “conductive screen”) must define
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`different regions of the chamber.
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`See Phillips, 415 F.3d at 1315 (“the
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`U.S. Patent No. 8,980,764
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`specification ‘is always highly relevant to the claim construction analysis.
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`Usually, it is dispositive; it is the single best guide to the meaning of a
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`disputed term.’”) (quoting Vitronics Corp. v. Conceptronic, Inc., 90 F.3d
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`1576, 1582 (Fed. Cir. 1996)).
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`Petitioner is apparently attempting to improperly import the exemplary
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`embodiment shown in Fig. 6 of the ‘764 patent into the claimed “mechanical
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`partition.” As shown below in Fig. 6 of the ‘764 patent, the conductive screen
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`25, or “mechanical partition,” could arguably define two regions of the
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`vacuum processing chamber 10.
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`However, the conductive screen 25 in Fig. 6 is merely an exemplary
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`embodiment of the claimed partition, the particular configuration of which
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`should not be read into the claims. See Phillips, 415 F.3d at 1323 (noting
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`importance “to avoid the danger of reading limitations from the specification
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`into the claim.”); see also Epos Techs. Ltd. v. Pegasus Techs. Ltd., 766 F.3d
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`1338, 1341 (Fed. Cir. 2014) (“it
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`is improper to read limitations from a
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`preferred embodiment described in the specification—even if it is the only
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`embodiment—into the claims absent a clear indication in the intrinsic record
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`that the patentee intended the claims to be so limited”). Because there is
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`nothing in the intrinsic record indicating that the claims should be limited to
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`the specific embodiment
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`in Fig. 6,
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`the “mechanical partition” should be
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`construed as a “physical structure positioned between the plasma source and
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`the work piece.”
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`VI. OVERVIEW OF ASSERTED REFERENCES
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`Petitioner asserts four references across one Ground: Sekiya, Todorow,
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`Nisany and Ogasawara. These references are summarized below.
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`A.
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`Sekiya ‘901 (U.S. Pub. No. 2004/0115901)
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`Sekiya ‘901 is a U.S. printed publication entitled “Method for
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`Dividing Semiconductor Wafer.” Sekiya ‘901 attempts to solve the problem
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`of the cracking or stressing of semiconductor chips due to the dicing of the
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`chips by rotary blades without extra cost. (See e.g., Ex. 1005 at ¶ 3).
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`Generally, Sekiya ‘901 discloses a method for dicing a semiconductor
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`wafer, the semiconductor wafer having circuits sectioned by crosswise streets
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`diced. The wafer is put on an adhesive tape, which traverses the opening of a
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`frame. The wafer is stuck to the adhesive tape with its circuit face (i.e., its
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`front surface) up, forming a whole unit. The wafer is diced into individual
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`semiconductor chips each having a circuit. (See e.g., Ex. 1005 at Abstract).
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`The method disclosed in Sekiya ‘901 includes a masking step which
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`involves covering the semiconductor wafer
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`(W), which is mounted on
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`adhesive tape (T) within a frame (F), with a tape member (10) to cover the
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`circuit face of the semiconductor wafer on which the circuit patterns are
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`formed. The masking step is illustrated in FIG. 1 of Sekiya ‘901, shown
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`below:
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`U.S. Patent No. 8,980,764
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`Sekiya ‘901 – Fig. 1
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`Sekiya ‘901 further teaches a selective tape-removing step where the
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`crosswise portions of the tape member that are exactly aligned with the
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`underlying crosswise streets of the wafer are mechanically cut and removed.
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`Subsequently, an etching and dividing step is performed, which includes
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`chemically etching the semiconductor wafer having the crosswise streets
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`uncovered, where the crosswise streets are permitted to erode so that the wafer
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`is divided into individual semiconductor chips. (See e.g., id. at ¶ 11).
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`The method taught by Sekiya '901 does not require photomasks or
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`exposure equipment, which Sekiya '901 suggests lowers costs associated with
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`plasma dicing.
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`(See e.g., id. at ¶ 56). Further, Sekiya ‘901 teaches using a
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`low-density plasma (as opposed to the high density plasma of t