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UNITED STATES PATENT AND TRADEMARK OFFICE
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`Page 1
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`SAMSUNG ELECTRONICS COMPANY, LTD., )
`)
` Petitioner, )
`)
`vs. ) No. IPR2017-00036
`)
`PROMOS TECHNOLOGIES, INC., )
`)
` Patent Owner. )
`__ )
`
`DEPOSITION OF BILL GERVASI
`Redwood Shores, CA
`Tuesday, September 12, 2017
`
`REPORTED BY:
`SUSAN F. MAGEE, RPR, CCRR, CLR, CSR No. 11661
`Job No. 129048
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`SAMSUNG EXHIBIT 1013
`Samsung Electronics Co., Ltd. v. ProMOS Technologies, Inc.
`IPR2017-01414
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`Page 1 of 127
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`September 12, 2017
`9:13 a.m.
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`Deposition of BILL GERVASI, held at the offices
`of TECHKNOWLEDGE LAW GROUP LLP, 100 Marine Parkway,
`Suite 200, Redwood Shores, CA 94065, pursuant to Notice
`before SUSAN F. MAGEE, RPR, CCRR, CLR, CSR No. 11661.
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`APPEARANCES:
` PAUL HASTINGS
` Attorneys for Petitioner
` 875 15th Street, N.W.
` Washington, DC 20005
` BY: CHETAN BANSAL, ESQ.
` PAUL ANDERSON, ESQ.
`
` TECHKNOWLEDGE LAW GROUP
` Attorney for Patent Owner
` 100 Marine Parkway
` Redwood Shores, CA 94065
` BY: KEVIN JONES, ESQ.
`
` --o0o--
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`

` BILL GERVASI,
`called as a witness, having been duly sworn by a
`Certified Shorthand Reporter, was examined and testified
`as follows:
`
`Page 4
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` EXAMINATION BY MR. BANSAL
`
` Q. Good morning, Mr. Gervasi.
` Could you please state your name and spell it
`for the record.
` A. My name is Bill Gervasi, G-e-r-v-a-s-i.
` Q. You understand you're under oath today; right,
`Mr. Gervasi?
` A. Yes, I do.
` Q. Have you been deposed before, Mr. Gervasi?
` A. Yes, I have.
` Q. How many times?
` A. I'm not even sure. Seven or eight maybe.
` Q. Do you know the subject matter of the cases of
`those depositions?
` A. I can probably look at my notes and find what
`they all were.
` Q. Do you recall sitting here today?
` A. I recall some of them. I've been -- I mean,
`are you asking about specific cases or are you talking
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`about the material covered? I mean, I'm not exactly
`sure what your question is.
` Q. Yeah. I think you can start with the cases and
`then what the subject matter of each of those cases was.
` A. Let's see. Most recently -- I'm sorry. I'd
`have to look at my notes, but I worked on various cases
`such as ITC case with Nanya and Tessera in defense of
`the plaintiffs.
` Let's see. There was Samsung -- there was a
`couple of cases with Round Rock. There was Round Rock
`and SanDisk. There was Round Rock and somebody else.
`The names don't come to me. I'm sorry. I can't be more
`explicit, but I can look them up if you would hand me my
`résumé there. I think I have them listed.
` MR. BANSAL: I want to hand the witness what
`has been previously been marked as Exhibit 2002.
` BY MR. BANSAL:
` Q. Mr. Gervasi, what is this?
` A. This is my CV.
` Q. Is this accurate as of today?
` A. Yeah. I think it looks accurate, up-to-date.
` Q. Does your CV refresh your memory regarding the
`cases you worked on and what the subject matter was of
`those cases?
` A. Sure does. Exactly what I needed.
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` Q. So maybe let's start with the Tessera case at
`the very bottom.
` A. Mm-hmm.
` Q. Were you -- who were you representing? The
`plaintiff or the defendant in that case?
` A. I was representing Tessera in that case.
` Q. Were you deposed in that case?
` A. Yes.
` Q. Did you testify at trial in that case?
` A. I testified in Washington, D.C. for that.
` Q. And what was the subject matter of that suit?
` A. The window ball grid array package patent.
` Q. That was on DRAM?
` A. Yeah. It was for DRAM. The the window-BGA is
`the primary packaging type used by all DRAMs even today.
` Q. Then I see that you were also an expert witness
`for HP v. Technology Properties case.
` Who did you represent in that case?
` A. I don't remember.
` Q. Do you recall what the subject matter of that
`case was?
` A. Not of that one. No, I don't recall the
`details of that particular case.
` Q. How about the HiTi Digital v. Technology
`Properties case?
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` A. That one, I believe, was regarding disclosure.
`Disclosure of intellectual property during the standards
`process.
` Q. So in any of the cases that you were involved
`in as an expert witness, did you testify regarding DRAM
`technology other than packaging?
` A. Yes. For example, the -- let's see. In
`ZiiLABS -- in the ZiiLABS case, for example, earlier
`this year, it was regarding circuitry for the internals
`of a DRAM and the data capture mechanisms.
` Q. In any of the expert work that you have done,
`have you provided an opinion that the patent claim's
`invalid?
` A. I've done prior art searching for -- I don't
`remember which case that was. I believe the prior art
`search was the SK Hynix v. Intellectual Ventures. There
`was also Entorian work where I did prior art search and
`invalidation by prior art. Lenovo and Round Rock was
`patent validity. Yeah, so a few of the cases.
` Q. In the Lenovo v. Round Rock case, did you
`provide testimony in court that a patent claim was
`invalid?
` A. It didn't go to court. It settled prior to
`going to court.
` Q. Did you submit an expert report in that case?
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` A. I submitted an expert report and was deposed.
` Q. The expert report opined that one or more
`patent claims were invalid?
` A. I don't recall the specific details on that.
` Q. So would it be accurate for me to say that you
`have not opined -- actually, strike that.
` So would it be accurate for me to say that
`sitting here today, you do not recall a case in which
`you have submitted an expert reported or testified to a
`patent claim being invalid?
` A. In multiple cases I have opined that a patent
`was valid. Invalidity -- invalidity on prior art I have
`opined on, but specifically the invalidity of a patent I
`don't recall a specific case.
` Q. What's -- is there a difference between
`invalidity on prior art and invalidity of a patent?
` A. Pardon me?
` Q. You said you have opined on invalidity on prior
`art, but --
` A. Oh. Based on prior art saying that such a
`concept had, you know -- had -- was derivative or
`potentially didn't side towards something like that;
`right?
` Q. So I don't know if I understood your answer,
`but I'll just repeat my question.
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` Would it be accurate for me to say that sitting
`here today, you do not recall a case in which you have
`submitted an expert report or testified that a patent
`claim is invalid?
` A. I don't recall a case like that. Infringement
`analysis is not the same thing as invalidity analysis,
`and so a lot of my work has primarily been in
`infringement analysis.
` Q. So before we begin, I just want to go over some
`basic ground rules because you've been deposed before,
`so you probably know this. I'll be asking you questions
`during this deposition. Your counsel Kevin here may
`object, but you must answer unless your counsel
`instructs you not to answer a question.
` Is that understood?
` A. Correct.
` Q. Our conversation here will be transcribed by
`the court reporter, and therefore, it's important that
`you speak your answers for obvious reasons. The court
`reporter cannot take down gestures. Again, for the
`benefit of the court reporter, let's make sure do not
`speak over each other. I'm probably more guilty of that
`than you will be, so I'll try my best.
` Breaks: We'll be taking breaks during this
`deposition, but if you need one, just let me know.
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` A. Great.
` Q. If a question is pending, I'll request that you
`answer the question before requesting a break.
` Any questions before we begin?
` A. Ready to go.
` Q. Is there any reason that would prevent you from
`testifying truthfully and accurately today?
` A. No.
` Q. Did you prepare for this deposition,
`Mr. Gervasi?
` A. Of course.
` Q. How many hours did you spend?
` A. For -- specifically for the prep for the
`deposition? Maybe ten.
` Q. What did you do in preparation for this
`deposition?
` A. Reviewed the patent, reviewed the other patents
`that had been cited by Samsung, reviewed my report.
`That was it. Basic -- had discussions with counsel
`about the patent materials and the concepts being
`expressed.
` Q. When you say you had discussions with counsel,
`who was counsel?
` A. Mr. Jones.
` Q. Anyone else?
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` A. No.
` Q. I was going to hand you your declaration, which
`was marked as Exhibit 2001 in this proceeding, but I
`understand you already have a copy of that.
` A. Okay.
` Q. So, Mr. Gervasi, I'm going to refer to your
`Exhibit 2001 as your declaration; is that okay?
` A. Okay.
` Q. Could you go to the last page of that
`declaration.
` A. Yes, sir.
` Q. Is that your signature?
` A. That is my signature.
` Q. Did you write this declaration yourself?
` A. Yeah.
` Q. You understand that this declaration was
`provided with ProMOS's patent owner's response in this
`proceeding?
` A. With ProMOS's what?
` Q. Patent owner response in this proceeding?
` A. Yeah.
` Q. Did you in any way help prepare the patent
`owner's response?
` MR. JONES: Objection to form.
` THE WITNESS: I don't know what document that
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`is exactly.
` BY MR. BANSAL:
` Q. If you don't mind, can you turn to -- I had a
`few quick questions on your CV.
` A. Okay.
` Q. So from 1989 through 1995, you were at Intel
`Corporation; correct?
` A. Correct.
` Q. Did any of your work at Intel Corporation
`involve DRAM?
` A. Yes. Significant amount.
` Q. Between 1989 and 1995?
` A. Yeah.
` Q. Did Intel get out of DRAM before then?
` A. Yes. Intel was not manufacturing DRAMs at that
`time, but manufacturing microprocessors interfacing to
`DRAMs.
` Q. Could you turn to paragraph 9 of your
`declaration.
` A. To paragraph 9 on page 4?
` Q. Yeah.
` A. Yes.
` Q. Do you see the sentence, the last one, "for
`nonvolatile memory, including DRAM."
` Is DRAM is a nonvolatile memory device?
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` A. DRAM is volatile.
` Q. So there did you mean DRAM to be included in
`nonvolatile memory devices or you were just saying that
`it's nonvolatile and DRAM?
` A. That's a bit of a typo. That -- yeah. That's
`a -- fundamentally a typo. I'm sorry. That should have
`read "flash."
` Q. So I just wanted to get a basic understanding
`of DRAM technology in the 1992 time frame or around
`that. So between 1990 and 1993. So all my questions
`today, whenever you answer that question, assume you are
`in that time frame.
` So give me your opinion based on one of
`ordinary skill in the art would have known in the 1990
`through 1992 time frame.
` A. Okay.
` Q. Okay. Because I may not specify that time
`frame, but you should assume that.
` Are you familiar with DRAMs as they existed in
`the time frame?
` A. My first task with Intel in 1976 was working on
`first-generation DRAMs, one kilobit DRAMs, and so yes,
`I've been familiar with DRAM operations since the 1970s.
`So in 1990 to 1992, if I recall, that would have been
`the -- that would have probably even been a little
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`Page 14
`before EDO memory, but it was kind of in that fast-paced
`world at that time if I recall.
` Q. So you are familiar with the DRAM in the 1990
`to 1992 time frame?
` A. Yes. I designed memory controllers in that
`general time frame. The 1980s.
` Q. Were DRAMs synchronous or asynchronous at that
`time?
` A. They were asynchronous at that time.
` Q. Do you know, what were the typical DRAM sizes
`in that time frame?
` A. Primarily we were around the -- let's see. 16
`mega- -- no. 16 kilobit. In the early '80s we were up
`at around 64 kilobit. I'm thinking 64 kilobit. 256
`kilobit would have been the mainstream memories around
`that time frame.
` Q. In the 1989 to 1992 time frame?
` A. Yeah. Something like that.
` Q. I'm going to pass you what has been previously
`marked as Exhibit 2001.
` What is it?
` A. This is the '270 patent. "Sense Amplifier with
`Local Write Drivers."
` MR. JONES: I just want make a clarification.
`I think you meant Exhibit 1001. It doesn't matter much,
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`but just so the record is clear.
` MR. BANSAL: Yes, Kevin. You are correct. I
`have passed to the witness what has been previously
`marked as Exhibit 1001.
` BY MR. BANSAL:
` Q. Could you please turn to column 2, line 14?
` A. I'm there.
` Q. Do you see the mention of a large memory, 16
`megabit DRAM?
` A. Yes.
` Q. It says also there are thousands of columns and
`thousands of rows?
` A. Correct.
` Q. Was a 16 megabit DRAM a typical DRAM size in
`the '89-1992 time frame?
` A. 1992? No. I don't think so.
` Q. Was 4 megabit DRAM a typical DRAM size in that
`time frame?
` MR. JONES: Objection to form.
` THE WITNESS: Maybe. I think in that time
`frame it might have been pretty boutique if it existed
`at all.
` BY MR. BANSAL:
` Q. So if you have a 256 kilobit memory, what is a
`256 kilobit referring to?
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` A. 256 kilobits is referring to the number of
`capacitive memory cells available from the outside that
`are stored inside the device.
` Q. What does one memory cell include in a DRAM?
` A. A memory cell includes primarily a capacitor.
`That capacitor stores a charge for some period of time.
`The volatile nature of a DRAM is that you have to
`refresh it periodically as you're probably aware, and --
`but it's just a capacitor that holds the charge.
` Q. Does each capacitor have an associated
`transistor that allows the capacitor to be accessed?
` A. There are multiple architectures, but that's
`the primary DRAM design characteristic is there is a
`transistor that allows the contents of that cell to be
`read and written.
` Q. So 256 kilobit DRAM chip typically would
`include at least 256 times 10 to the 3 access
`transistors?
` A. It would be 2- -- roughly 256,000 capacitors,
`256,000 transistors plus, you know, there would be
`spares and redundant rows and so forth, so there are
`actually more than that, but that's the general rule of
`thumb is that at least what's addressable from outside
`the chip are 256,000 of them.
` Q. But how many columns would be in a 256 kilobit
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`DRAM?
` MR. JONES: Objection to form.
` THE WITNESS: I would have to look at a data
`sheet to remember what the row and column organization
`was for those devices.
` BY MR. BANSAL:
` Q. Would it be less than 1,000?
` MR. JONES: Objection to form.
` THE WITNESS: Don't remember. Been too long
`since I worked on those devices.
` BY MR. BANSAL:
` Q. Could you turn to paragraph 27 of your
`declaration?
` A. So what am I turning to?
` Q. Paragraph 27.
` A. Paragraph 27. Okay.
` Q. The first sentence says, "In large memories
`having thousands of columns and rows, a chip may have
`thousands of sense amplifiers."
` Do you see that?
` A. Right.
` Q. Were large memories having thousands of columns
`and rows typical in the 1992 time frame?
` MR. JONES: Objection to form.
` THE WITNESS: I do not recall what the number
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`of rows are as I previously stated. I mean, number of
`columns in a device in that time frame. I'd be happy to
`open up a data sheet and point it to you, but I don't
`know it off the top of my head. 1024 is common in more
`recent generations of memory.
` BY MR. BANSAL:
` Q. What was more common at that time?
` A. I don't remember.
` MR. JONES: Objection to form.
` BY MR. BANSAL:
` Q. Is it 1,024 per bank?
` A. That is dependent on the DRAM design. Some
`DRAM designs share sense amps between banks.
` Q. So this sentence that you have in paragraph 27
`of enlarged memories having thousands of columns and
`rows, is that your opinion that that large memories had
`thousands of columns and rows or are you simply citing
`to what's in the '270 patent?
` A. It's DRAM design. DRAM design. I mean, you
`know, if you have ten row bits, you're going to have two
`to the tenth sense amps minimum for that device, and
`depending on the DRAM design you may have more. You may
`have multiples of that.
` Q. What I don't understand was, did large memories
`in the 1992 time frame have thousands of columns and
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`rows?
` A. I believe I've answered that.
` MR. JONES: Objection to form.
` BY MR. BANSAL:
` Q. Because you state that in paragraph 27, the
`first sentence, Enlarged memories having thousands of
`columns and rows.
` What I'm trying to understand, did large
`memories at the time of the invention of the '270 patent
`have thousands of columns and rows?
` MR. JONES: Objection to the form.
` THE WITNESS: Without seeing a data sheet of a
`DRAM from that time frame, I can't answer that specific
`question.
` BY MR. BANSAL:
` Q. Could you please look at column 2, line 14
`through 15 of the '270 patent?
` A. Column 2, line 14? Yes.
` Q. It says, In any large memory, such a 16 megabit
`DRAM, there will be thousands of columns and thousands
`of rows.
` Do you agree or disagree with that statement?
` A. I believe that that could be accurate, yes.
` Q. But you're not sure it's -- whether it's
`accurate or not?
`
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` A. I would have to see a data sheet to answer that
`question to -- if you look at a DRAM data sheet, one of
`the first things you see is the row/column organization,
`and that even changes based on the number of I/Os on the
`chip that you may have a by-4 device that has, for
`example, 15 rows and 10 columns for -- in terms of the
`number of bits. The by-8 may or may not have that same
`organization. The by-16 may or may not have that same
`organization. It's the first thing that you see in a
`DRAM data sheet basically is the row and column
`organization, but it tends to be in the newer
`generations on that order. Like 16 columns and 10 row
`bits.
` In 1992, I just don't recall what the exact
`organization was.
` Q. How were the memory cells arranged in the DRAM
`typically in the 1992 time frame?
` MR. JONES: Objection to form.
` THE WITNESS: Rows and columns.
` BY MR. BANSAL:
` Q. So the intersection of the row and column is
`where a single memory cell will be located?
` A. Somewhere generally local to that intersection
`of the row and column lines.
` Q. Can you please turn to page 9 of your
`
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`declaration, paragraph 24.
` A. I'm there.
` Q. Do you see the section that starts with, "Each
`memory cell is formed of a capacitor holding a state."
` Do you see that sentence?
` A. Yeah.
` Q. Can you read that and let me know if you
`believe it's accurate?
` A. "Each memory cell is formed of a capacitor
`holding a state (either a '1' or a '0') and resides at
`the intersection of a bit line pair (typically arranged
`in rows) and a word line (typically arranged in
`columns)."
` "Rows" and "columns" may be a little backwards
`depending on what you -- how would one interpret that
`grammar. But yeah, it's essentially the intersection of
`rows and columns by which the capacitor would be
`located.
` Q. Could you please turn to column 1, line 31 of
`the '270 patent.
` A. Line 31. Starting with, "Often, a memory array
`is divided into subarrays"?
` Q. Yeah. Can you please just read those two
`sentences to yourself.
` A. Okay.
`
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` Q. What is meant by subarrays in the context of
`DRAM in the 1992 time frame?
` MR. JONES: Objection to form.
` THE WITNESS: There are a number of ways in
`which the memory array can be split up. Some DRAM
`designers, for example, if they have a by-4 it I/O
`interface at the periphery of the chip may find it
`advantageous to put each of those four bits into
`separate blocks. Other designers find it advantageous
`to have all four bits in each of these subarrays. And
`so when you're dividing up the memory into these
`subarrays, essentially what you're trying to do is
`optimize the length of the metal lines interconnecting
`the rows and columns, so that optimization leads you in
`that direction of breaking up the array if you can to
`minimize the bit line lengths.
` BY MR. BANSAL:
` Q. So 256 kilobit DRAM memory array would be
`broken up into, say, four subarrays of 64 kilobits?
` A. That would be up to the designer as to how the
`division would be done. There are some in more modern
`memories where there are specifically four or eight
`addressable banks. It is explicit how some of that
`breakup is done. In DRAM design, it's sometimes up to
`the DRAM designer exactly how to make that division, and
`
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`Page 23
`it's not visible explicitly to the memory controller.
` Q. In your opinion, how were subarrays split up in
`the 1992 time frame typically?
` MR. JONES: Objection to form.
` BY MR. BANSAL:
` Q. Or was each subarray the same size --
` MR. JONES: Objection.
` BY MR. BANSAL:
` Q. -- typically in the 1992 time frame?
` A. The subarrays would be identical within a given
`chip, but between manufacturers or designers, no, there
`were no common standards.
` Q. Yeah. I was just asking same chip.
` A. In the same chip, yes, each block would be the
`same size.
` Q. And you would also agree with me that the
`subarray often had its own decoder.
` So four subarrays may individually each have
`their own decoder?
` MR. JONES: Objection to form.
` THE WITNESS: Not necessarily.
` BY MR. BANSAL:
` Q. But that was one way that was known at the time
`of the '270 patent; right?
` MR. JONES: Objection to form.
`
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` THE WITNESS: Don't know.
` BY MR. BANSAL:
` Q. So do you disagree with column 1, line 32
`through 34 of the '270 patent?
` A. No, I don't disagree with it. I just can't
`assert that that's the only way that you can design in
`that time frame.
` Q. Well, what I was asking you based on your
`knowledge of the DRAM industry for so many years,
`especially your knowledge during the 1990 through 1992
`time frame, was it known for each subarray to have its
`own decoder?
` A. I cannot state definitively what 1992 time
`frame, how that arrangement would have been done. No, I
`don't know.
` Q. If a subarray had its own decoder, would the
`subarray be independently addressable?
` A. The term "decoder" in this context, are you
`referring to the row and column decoders? Are you
`referring to bank decoders? There are many decoders in
`a chip. What specifically are you asking about?
` Q. Were there multiple banks in 1992 on a DRAM
`chip?
` MR. JONES: Objection to form.
` THE WITNESS: I don't know.
`
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` BY MR. BANSAL:
` Q. So let's assume that I'm talking about multiple
`column decoders or column decoders in general.
` Was it known in the 1992 time frame for each
`subarray to have its own row and its own column decoder?
` MR. JONES: Objection to form.
` THE WITNESS: I do not know.
` BY MR. BANSAL:
` Q. Can you think of any advantage that you would
`obtain by having an independent row and independent
`column decoder for each subarray?
` A. Yes.
` Q. What would it be?
` A. As I previously mentioned, controlling the
`length of the metal lines in the array is a key to
`maintaining DRAM performance. And so subdividing into
`subarrays, the primary goal is that minimization of the
`metal lengths. So duplicating decoders would be a
`technique for minimizing the length of the wires.
` Q. Any other advantages that you can think of that
`would arise from having multiple subarrays, each of the
`subarrays having its own row and column decoder?
` A. There can be timing advantages. You can
`exploit having parallelism to overlap certain
`operations, you know. When we get into talking about
`
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`Page 26
`some of the cited art like Ogawa, you can see that there
`were -- there were timing things that you can do to
`increase the efficiency. And aside from that, I mean,
`the primary goal, again, is to access time and
`controlling access time.
` Q. When you say "efficiency" and "parallelism,"
`are you referring to throughput?
` A. No. Throughput is strictly kilobits per
`second, megabits per second, gigabits per second.
` Efficiency is how busy you can keep the I/Os,
`and there's always some measure of inefficiency,
`especially in a memory that has a bidirectional
`interface. You have turnaround time from read to write,
`for example, that inserts bubbles, delays. And
`minimizing those delays and extracting as close to 100
`percent efficiency is different than frequency, for
`example.
` Q. If the I/Os are busier, don't you have more
`throughput in terms of data transfer?
` A. Let's take a classic example. If you are
`running today's memories are running, for example, at
`peak of around 3.2 gigabits per second, per I/O pin. So
`that's your bandwidth. That's your frequency of
`operation. Your bandwidth is that specific number. Can
`you achieve 100 percent throughput? Well, you can while
`
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`Page 27
`you're bursting data out of the memory. In theory, you
`can achieve a throughput of 3.2 gigabits per second. In
`practice, you have an efficiency problem that, because
`of commands, because of turnaround bubbles and so forth,
`most computer systems actually only operate at around,
`say, 60 percent. Or let's pick an easier number. If
`that efficiency of operation is only 50 percent, then
`your throughput is half. It's 1600 instead -- 1.6
`instead of 3.2 gigabits per second of effective
`throughput.
` So the question is -- is a little bit non
`sequitur in the sense that it's just the distinction
`between frequency and actual effective work that I'm
`drawing the line between.
` Q. What would be the benefit of keeping the I/Os
`busier by having multiple column and row decoders?
` A. Well, you're asking two questions there. The
`first half of your question if I may rephrase it is
`what's the advantage of keeping your I/Os busier, and
`the answer to that is, that's what customers are paying
`for. When you're on your phone and you want to view a
`picture, the faster the memory is running, the faster
`your picture is going to come up and the better
`perceived consumer effects.
` Now you're asking the second question, and if I
`
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`Page 28
`may paraphrase that, you said, what is the advantage of
`having multiple row and column decoders in terms of
`keeping the I/Os busier. And so that's the efficiency
`question. If you can overlap certain operations, if you
`can Ping-Pong between them, if you can do various
`manipulations with these data sources, then you can keep
`the I/Os busier.
` For example, a DRAM has a row-to-row timing,
`minimum timing that you can -- you cannot exceed. You
`have to basically delay and give the chance for the next
`row to be activated, for the precharge operation.
`Whatever is going on inside the chip, you have to wait
`for that.
` So if you're waiting, that represents a delay
`on your outputs, and the user experience goes down.
`However, if you have two banks, if you can Ping-Pong
`between them, then you can take that row-to-row column,
`that row-to-row delay and split it up with other work to
`be done.
` So just in general having more resources inside
`of a device gives you more opportunities to try to keep
`the I/O busier and give the better user experience.
` Q. Would better user experience include faster
`access time?
` A. This is typically not -- and it depends on your
`
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`definition of "access time." And unfortunately I --
`being a nerd, I tend to jump right into access time
`meaning like from the first row activation. But, for
`example, that row-to-row timing, yeah, that is -- that's
`also an access time delay. And yes, you can mitigate
`some of them by doing parallel operations.
` Q. Let me just understand what you're saying.
` You're saying that one of the benefits of
`having multiple row and column decoders would have been
`that you can provide a better user experience?
` MR. JONES: Objection to form.
` THE WITNESS: The answer to that would be yes.
` BY MR. BANSAL:
` Q. By better user experience, you mean that, for
`example, the data that the user is asking for could be
`retrieved at a faster pace?
` A. That would be an advantage of having a faster
`memory or a more efficient memory.
` Q. What would having a disadvantage of having
`multiple row and multiple column decoders?
` A. Primary

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