Trials@uspto.gov
`571.272.7822
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`
`
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`Paper No. 6
`Filed: November 17, 2017
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`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`SAMSUNG ELECTRONICS CO., LTD.,
`Petitioner,
`
`v.
`
`PROMOS TECHNOLOGIES, INC.,
`Patent Owner.
`____________
`
`Case IPR2017-01415
`Patent 6,208,574
`____________
`
`Before JAMESON LEE, KEVIN F. TURNER, and
`MATTHEW J. McNEILL, Administrative Patent Judges.
`
`McNEILL, Administrative Patent Judge.
`
`
`
`
`DECISION
`Institution of Inter Partes Review
`37 C.F.R. § 42.108
`
`
`
`
`
`
`
`
`571.272.7822
`
`
`
`
`
`Paper No. 6
`Filed: November 17, 2017
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`SAMSUNG ELECTRONICS CO., LTD.,
`Petitioner,
`
`v.
`
`PROMOS TECHNOLOGIES, INC.,
`Patent Owner.
`____________
`
`Case IPR2017-01415
`Patent 6,208,574
`____________
`
`Before JAMESON LEE, KEVIN F. TURNER, and
`MATTHEW J. McNEILL, Administrative Patent Judges.
`
`McNEILL, Administrative Patent Judge.
`
`
`
`
`DECISION
`Institution of Inter Partes Review
`37 C.F.R. § 42.108
`
`
`
`
`
`
`
`
`
`IPR2017-01415
`Patent 6,208,574
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`I. INTRODUCTION
`
`A. Background
`
`On May 12, 2017, Petitioner, Samsung Electronics Co. Ltd., filed a
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`Petition (Paper 1, “Pet.”) to institute inter partes review of claims 4‒18 and
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`21‒27 of U.S. Patent No. 6,208,574 (Ex. 1001, “the ’574 patent”).
`
`Petitioner proffered a Declaration of R. Jacob Baker, Ph.D., P.E. (Ex. 1002)
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`with its Petition. Patent Owner, ProMOS Technologies, Inc., did not file a
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`Preliminary Response.
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`To institute an inter partes review, we must determine that the
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`information presented in the Petition shows “that there is a reasonable
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`likelihood that the petitioner would prevail with respect to at least 1 of the
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`claims challenged in the petition.” 35 U.S.C. § 314(a). For the reasons that
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`follow, Petitioner has demonstrated a reasonable likelihood that it would
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`prevail in establishing that each of claims 4‒18 and 21‒27 is unpatentable as
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`obvious over the cited prior art. Accordingly, we institute an inter partes
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`review as to claims 4‒18 and 21‒27 of the ’574 patent on the grounds of
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`unpatentability presented.
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`B.
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`Related Matters
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`Petitioner concurrently filed a Petition challenging claims 1‒3 and
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`30‒37 of the ’574 Patent in IPR 2017-001414. Petitioner identifies
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`U.S. Patent No. 6,088,270 (“the ’270 patent”) as related to the ’574 patent.
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`Pet. 2. Petitioner indicates that the ’270 patent is the subject of inter partes
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`review in IPR 2017-00036.
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`Petitioner indicates that Patent Owner asserted the ’574 patent against
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`Petitioner in ProMOS Technologies, Inc. v. Samsung Electronics Co., No.
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`1:16-cv-00335-SLR-SRF (D. Del.). Pet. 1. Petitioner indicates Patent
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`2
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`IPR2017-01415
`Patent 6,208,574
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`Owner has also asserted the following patents in that action: U.S. Patent
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`Nos. 6,069,507; 6,172,554; 6,562,714; 7,375,027; and 6,559,044. Id.
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`Petitioner concurrently filed IPR petitions challenging the other asserted
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`patents in the following inter partes review proceedings: IPR2017-01412,
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`IPR2017-01413, IPR2017-01416, IPR2017-01417, IPR2017-01418, and
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`IPR2017-01419. Id.
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`Petitioner also filed several IPR petitions involving patents asserted
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`by Patent Owner against Petitioner in ProMOS Technologies, Inc. v.
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`Samsung Electronics Co., No. 1:15-cv-00898-SLR-SRF (D. Del.). Pet. 1‒2.
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`Petitioner identifies the following inter partes review proceedings for the
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`patents involved in that suit: IPR2017-00032, IPR2017-00033, IPR2017-
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`00035, IPR2017-00036, IPR2017-00037, IPR2017-00038, IPR2017-00039,
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`and IPR2017-00040. Id.
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`C.
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`The ’574 Patent
`
`The ’574 patent relates to sense amplifiers in integrated circuit
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`memories. Ex. 1001, 1:9–11. Integrated circuit memories often include a
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`large number of memory cells set forth in a memory array. Id., 1:14‒15.
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`Memory arrays are often organized into rows and columns. Id., 1:35‒36.
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`Rows represent the memory cells located along a word line. Id., 1:36‒37.
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`Columns are organized perpendicularly to the rows and represent the
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`memory cells located along a bit line. Id., 1:37‒40. Generally, each column
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`is connected to a sense amplifier. Id., 1:40‒41. In a large memory cell with
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`thousands of columns and rows, the voltage that reaches sense amplifiers at
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`different ends of the array may be appreciably different as a result of
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`resistance along the lines, causing inefficient or slow operation. Id., 2:15‒
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`3
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`IPR2017-01415
`Patent 6,208,574
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`39. The ’574 patent relates to additional circuitry that may be connected to
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`the sense amplifiers to alleviate these issues. Id., 4:61‒5:39.
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`One embodiment of the ’574 patent is represented in Figure 5, which
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`is reproduced below.
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`
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`Figure 5 depicts sense amplifier 100 having a latch formed by
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`transistors 112, 114, 118, and 120. Id. at 6:6–9. Node 102 is coupled to the
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`gate electrodes of P-channel transistor 112 and N-channel transistor 118.
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`Node 102 is also coupled to the source-drain path of pass transistor 124. Id.
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`at 6:28‒31. Node 104 is coupled to the gate electrodes of P-channel
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`transistor 114 and N-channel transistor 120. Id. at 6:9–13. Node 104 is also
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`coupled to the source-drain path of pass transistor 122. Id. at 6:28‒31. Pass
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`transistors 122 and 124 are driven by column write select signal YW. Id. at
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`6:15–16.
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`Transistor 122 is also coupled to node 126 between the source
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`4
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`IPR2017-01415
`Patent 6,208,574
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`electrode of local data write driver transistor 128 and the drain of local data
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`write driver transistor 130. Id. at 6:32–35. Transistors 128 and 130 are
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`N-channel transistors having their source-drain paths coupled in series. Id.
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`at 6:35–36. The drain of transistor 128 is coupled to VCC and the source of
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`transistor 130 is coupled to ground. Id. at 6:36–38. Data write signal DW is
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`coupled to the gate electrode of transistor 128, and its complement DWB is
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`coupled to the gate electrode of transistor 130. Id. at 6:38–40. Transistors
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`132 and 134 on the opposite side of sense amplifier have a similar
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`arrangement, though DW and DWB are applied oppositely. Id. at 6:40–47.
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`Figure 5 also depicts local sense amplifier drive transistors 140 and
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`142. Id. at 7:16‒18. Transistor 140 is coupled to the source electrodes of
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`transistors 112 and 114. Id. at 6:53‒55. The source electrode of transistor
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`140 is coupled to VCC (or LATCHP). Id. at 6:55‒56. The gate of transistor
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`140 is coupled to LPB, which is the logical complement of LATCHP. Id. at
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`6:56‒57. Transistor 142 is similarly configured with N channel transistors
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`118 and 120, but the gate electrode of transistor 142 is coupled to signal
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`LNB, the logical complement of LATCHN. Id. at 6:59‒65.
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`The lower portion of Figure 5 also depicts a local column read
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`amplifier comprising N channel transistors 150, 152, 154, and 156. Id. at
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`6:66‒7:1. The source-drain paths of transistors 150 and 152 are coupled in
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`series, and the drain electrode of transistor 150 receives signal DRB, the
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`logical complement of a data read signal DR. Id. at 7:1‒4. The gate
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`electrode of transistor 150 is coupled to column read signal YR. Id. at 7:7‒8.
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`The source electrode of transistor 152 is coupled to ground. Id. at 7:4‒5.
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`The gate electrode of transistor 152 is coupled to node 104. Id. at 7:5‒7.
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`The source-drain paths of transistors 154 and 156 are similarly
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`5
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`IPR2017-01415
`Patent 6,208,574
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`configured, being coupled in series between data read signal DR and ground
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`on the right side of the figure. Id. at 7:8‒10. The gate electrode of transistor
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`156 is coupled to node 102. Id. at 7:11‒13.
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`Petitioner notes (see Pet. 4) that the ’574 patent claims priority to an
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`earlier application filed on November 12, 1992. Ex. 1001, at [62]. As
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`discussed below, Petitioner establishes that the asserted references qualify as
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`prior art assuming that November 12, 1992, is the priority date of the ’574
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`patent. See Pet. 4.
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`Claim 4 of the ’574 patent is independent and reproduced below:
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`A sense amplifier arrangement for an integrated circuit
`4.
`memory comprising, for each of a plurality of sense amplifiers:
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`a sense amplifier latch circuit having a pair of nodes to
`which respective bit lines may be coupled;
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`a local column read amplifier responsively coupled to the
`sense amplifier, and receiving at least one data read signal; and
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`a local data write driver circuit coupled to receive write
`data during a write operation at a gate electrode of a transistor in
`said data write driver circuit and to apply a signal based upon
`receiving said write data to one of said latch circuit nodes.
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`Ex. 1001, 13:46‒58.
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`D.
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`Evidence Relied Upon
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`Petitioner relies on the following prior art:
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`Japanese Patent Application Publication No. S58-128087,
`published July 30, 1983 (Ex. 1007, “Inoue”);1
`
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`1 Petitioner relies on a certified English translation of Inoue. Exhibit 1007
`includes an English language version of Inoue (pages 1‒6), the Japanese
`language version of Inoue (pages 7‒10), a declaration certifying the English
`translation (page 11), and a certified correction to the translation (page 12).
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`Patent 6,208,574
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`UK Patent Application Publication No. G.B. 2246005A,
`published January 15, 1992 (Ex. 1008, “Min”);
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`Hamade, U.S. Patent No. 5,323,349, filed August 28,
`1992, issued June 21, 1994 (Ex. 1009, “Hamade”); and
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`Ogawa, U.S. Patent No. 5,293,347, filed December 30,
`1991, issued March 8, 1994 (Ex. 1010, “Ogawa”).
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`E.
`
`The Asserted Grounds
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`Petitioner asserts the following grounds of unpatentability2:
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`References
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`Basis
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`Claims Challenged
`
`Inoue, Min, and Hamade
`
`§ 103(a)
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`4‒10, 14‒17, 21‒27
`
`Inoue, Min, Hamade, and
`Ogawa
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`§ 103(a)
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`11‒13, 18
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`II. ANALYSIS
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`A. Claim Construction
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`Petitioner represents that the ’574 patent will expire on March 27,
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`2018, during the pendency of this proceeding, if a trial is instituted. Pet. 9‒
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`10. Patent Owner does not state otherwise. Accordingly, we construe the
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`challenged claims according to rules applicable to expired patent claims.
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`We review expired patent claims according to the standard applied by
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`the district courts. See In re Rambus, 694 F.3d 42, 46 (Fed. Cir. 2012).
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`Specifically, we apply the principles set forth in Phillips v. AWH Corp.,
`
`
`Our citations refer to the certified English translation of Inoue (pages 1‒5 of
`Exhibit 1007).
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`2 Petitioner asserts separate grounds of patentability for claims 17 and 18,
`respectively, because the asserted grounds for these rely on different
`portions of the cited references than Grounds 1 and 2. See Pet. 4 (Grounds 3
`and 4). For simplicity, we have consolidated Ground 3 into Ground 1 and
`Ground 4 into Ground 2.
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`7
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`IPR2017-01415
`Patent 6,208,574
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`415 F.3d 1303, 1312 (Fed. Cir. 2005). “In determining the meaning of the
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`disputed claim limitation, we look principally to the intrinsic evidence of
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`record, examining the claim language itself, the written description, and the
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`prosecution history, if in evidence.” DePuy Spine, Inc. v. Medtronic
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`Sofamor Danek, Inc., 469 F.3d 1005, 1014 (Fed. Cir. 2006) (citing Phillips,
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`415 F.3d at 1312–17).
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`Only terms which are in controversy need to be construed, and only to
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`the extent necessary to resolve the controversy. See Wellman, Inc. v.
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`Eastman Chem. Co., 642 F.3d 1355, 1361 (Fed. Cir. 2011); Vivid Techs.,
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`Inc. v. Am. Sci. & Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir. 1999). Based on
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`the current record, we determine that only the two terms below require
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`explicit construction at this time.
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`1.
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`“local data write driver circuit”
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`Petitioner proposes that we construe the term “local data write driver
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`circuit” in independent claim 4 to mean “a data write driver circuit that is
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`associated with only one latch circuit.” Pet. 10. Petitioner notes that it
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`proposed the same construction in IPR2017-00036 concerning the related
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`’270 patent, and the Board adopted this proposed construction in the
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`Institution Decision in IPR2017-00036. Id. (citing Samsung Elecs. Co., Ltd.
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`v. ProMOS Techs., Inc., IPR2017-00036, Paper 6 at 8 (Apr. 6, 2017)).
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`In the IPR2017-00036 Institution Decision, the Board noted that the
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`term “local” as applied to this limitation had been construed in an ex parte
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`appeal of the application that matured into the ’270 patent. Id. In the
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`ex parte appeal, the Board construed the term “local” to mean having “a
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`definite spatial form or location.” Id. In the IPR2017-00036 Institution
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`Decision, the Board noted this construction is not inconsistent with
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`8
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`Petitioner’s proposed construction because the ex parte appeal applied the
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`broadest reasonable interpretation of the term and the term was construed in
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`the Institution Decision under the Phillips standard. Id.
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`Petitioner cites evidence from the Specification to support its
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`proposed construction. Pet. 10‒12 (citing Ex. 1001, 4:61‒63, 5:29‒36, 6:5‒
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`13, 7:15‒16, Fig. 5). Petitioner also contrasts the “local” nature of the data
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`write driver circuit with the term “global” in the Specification, which is
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`defined as “connected to several sense amps.” Pet. 12 (citing Ex. 1001,
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`11:25‒31).
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`Petitioner additionally cites to arguments the patent applicant made
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`during prosecution of applications leading to related patents with the same
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`Specification and similar claim limitations that are consistent with
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`Petitioner’s proposed construction. See id. at 13 (citing Ex. 1006, 274; Ex.
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`1005, 166–68). In particular, in the Reply Brief during the ex parte appeal
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`of the application that led to the related ’270 patent, the applicant stated that
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`“the pair of data write circuits in the present application is associated with
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`only one latch circuit and is clearly local to that one latch circuit,”
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`contrasting the prior art reference that disclosed write circuits connected to
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`multiple latch circuits. Ex. 1006, 274. In addition, during prosecution of
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`Application No. 07/976,312, of which the ’270 patent is a divisional
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`application, the applicant stated in the Remarks to an Amendment that the
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`transistors cited by the Examiner were “connected to several sense
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`amplifiers” and, therefore, “global – just the opposite of local drive
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`transistors.” Ex. 1005 at 168. Accordingly, during prosecution of the
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`related ’270 patent and its parent application, the applicant contrasted local
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`circuit elements that were connected to a single sense amplifier with global
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`Patent 6,208,574
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`circuit elements that were connected to multiple sense amplifiers.
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`Based on the presented evidence and the approach for claim
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`construction under Phillips, we construe “local data write driver circuit” for
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`purposes of this Decision to mean “a data write driver circuit that is
`
`associated with only one latch circuit.”
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`2.
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`“local column read amplifier”
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`Petitioner proposes that we construe the term “local column read
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`amplifier” in independent claims 1 and 30 to mean “a column read amplifier
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`that is associated with only one latch circuit.” Pet. 14.
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`Petitioner cites evidence from the Specification to support its
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`proposed construction. Pet. 14‒16 (citing Ex. 1001, 4:64‒65, 5:29‒36,
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`6:66‒7:1, 13:22‒24, 13:46‒58, 15:52‒16:1, Fig. 5). For example, Petitioner
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`contends that throughout the Specification, a “local column read amplifier is
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`described as being connected to, or associated with, a single latch circuit.”
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`Pet. 15 (citing Ex. 1001, Fig. 5, 4:64‒65, 5:29‒36). Petitioner also contrasts
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`the “local” nature of the column read amplifier with the term “global” in the
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`Specification, which is defined as “connected to several sense amps.” Pet.
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`16.
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`Based on the presented evidence and the approach for claim
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`construction under Phillips, we construe “local column read amplifier” to
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`mean “a column read amplifier that is associated with only one latch
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`circuit.”
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`B.
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`Level of Ordinary Skill in the Art
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`With regard to the level of ordinary skill in the art, Petitioner states:
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`“A person of ordinary skill in the art at the time of the alleged invention of
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`the ’574 patent (‘POSITA’) would have had at least a Bachelor’s degree in
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`10
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`Patent 6,208,574
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`electrical engineering or a similar field, and at least two to three years of
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`experience in design of semiconductor memory circuits.” Pet. 5. Petitioner
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`further states that “[m]ore education can supplement practical experience
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`and vice versa.” Id. at 5. Dr. Baker’s testimony supports Petitioner’s
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`position. Ex. 1002, ¶ 20. Patent Owner did not file a Preliminary Response
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`and, therefore, has not disputed Petitioner’s position. At this stage of the
`
`proceeding, we are satisfied that Petitioner’s proposed definition comports
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`with the qualifications a person would need to understand and implement the
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`teachings of the ’574 patent and the prior art of record. Accordingly, we
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`apply Petitioner’s definition of the level of ordinary skill in the art for
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`purposes of this Decision.
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`C. Ground 1: Alleged Obviousness of Claims 4‒10, 14‒16, and
`21‒27 over Inoue, Min, and Hamade
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`We have reviewed the Petition and determine that, on the present
`
`record, Petitioner has shown a reasonable likelihood that it would prevail in
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`establishing unpatentability of each of claims 4‒10, 14‒16, and 21‒27 as
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`obvious over Inoue, Min, and Hamade.
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`1.
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`Inoue
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`Inoue is a Japanese patent application publication directed to “a
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`semiconductor device that consumes only a small amount of transient power
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`when writing to a flip-flop.” Ex. 1007, 3. Figure 6 of Inoue is reproduced
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`below.
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`11
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`Figure 6 depicts a CMOS flip-flop circuit having supply terminals
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`VDD, nodes N1–N3, N-channel transistors QN1–QN10, P-channel transistors
`QP1–QP3, and clocks ϕ1–ϕ4. Id. at 3–4. D & D̅ are input terminals. Id. at 4.
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`The circuit in Figure 6 may be applied to a sense amplifier in a dynamic
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`memory, wherein nodes N1 and N2 correspond to bit lines, and transistors
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`QN6–QN9 correspond to the output stage for the data input buffer. Id.
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`We agree with Petitioner (Pet. 4) that Inoue qualifies as prior art under
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`at least 35 U.S.C. § 102(b)3 because Inoue’s publication date is July 30,
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`1983, which is more than one year before the earliest possible priority date
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`for the ’574 patent, November 12, 1992. See Ex. 1001, at [62]; Ex. 1007,
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`at [43].
`
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`3 The Leahy-Smith America Invents Act, Pub. L. No. 112-29, 125 Stat. 284
`(2011) (“AIA”), amended 35 U.S.C. §§ 102 and 103. Because the priority
`date of the ’270 patent is before the effective date of the applicable AIA
`amendments, the pre-AIA versions of 35 U.S.C. §§ 102 and 103 apply.
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`2. Min
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`Min is a United Kingdom patent application publication directed to a
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`sense amplifier driving circuit for controlling sense amplifiers of a high
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`density semiconductor memory device. Ex. 1008, Abstract. Figure 3B of
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`Min is reproduced below.
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`
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`Figure 3B depicts a memory device with a plurality of sense
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`amplifiers SA1‒SAN. Ex. 1008, 1:4‒8, Fig. 3B. Each sense amplifier is
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`coupled to a bit line pair (BLL and BLR). Ex. 1008, 2:5‒15, Fig. 3B. Each
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`sense amplifier is also coupled to a positive power supply (VCC) via driving
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`transistor Q10i and to ground (VSS) via driving transistor Q20i. Id. at 21:1‒
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`13, Fig. 3B. Min discloses a common driving signal from driving transistors
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`Q10i and Q20i. Ex. 1008, Fig. 3B.
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`We agree with Petitioner (Pet. 4) that Inoue qualifies as prior art under
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`at least 35 U.S.C. § 102(a) because Inoue’s publication date is January 15,
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`1992, which is before the earliest possible priority date for the ’574 patent,
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`November 12, 1992. See Ex. 1001, at [62]; Ex. 1008, at [43].
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`3.
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`Hamade
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`Hamade discloses a semiconductor memory device. Ex. 1009, 1:8‒9.
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`Figure 1 of Hamade is reproduced below.
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`
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`Figure 1 illustrates a “main part” of such a device and depicts a pair of
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`bit lines BL and /BL and their associated circuitry. Id. at 3:1‒5, 7:10‒13,
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`Fig. 1. Each bit line pair is associated with n-type sense amplifier 2 and p-
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`type sense amplifier 3. Id. at 1:47‒52, 7:4‒13 Fig. 1. Drive circuit 9,
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`comprised of transistors Q16‒Q19, is provided for each bit line pair. Id. at
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`7:14‒19, Fig. 1. Drive circuit 9 “amplifies the potentials of the associated
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`bit lines.” Id. Drive circuit 9 “operate[s] to amplify the potentials on bit
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`lines BL and /BL during a read operation, and allow[s] one of read only data
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`lines RI and /RI to be discharged to ground during a read operation.” Pet.
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`33.
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`We agree with Petitioner (Pet. 4) that Hamade qualifies as prior art
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`under at least 35 U.S.C. § 102(e) because Hamade’s filing date is
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`August 28, 1992, which is before the earliest possible priority date for the
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`’574 patent, November 12, 1992. See Ex. 1001, at [62]; Ex. 1008, at [22],
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`[45].
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`14
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`4.
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`Independent claim 4
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`Claim 4 recites “A sense amplifier arrangement for an integrated
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`circuit memory comprising.” Petitioner asserts that Inoue discloses this
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`feature. Pet. 17. In particular, Petitioner asserts “Inoue discloses ‘a
`
`semiconductor device’ comprising a sense amplifier with a flip-flop circuit.
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`The circuit in figure 6 of Inoue is for a sense amplifier in a dynamic
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`memory.” Id. (citations omitted). Petitioner further asserts an ordinarily
`
`skilled artisan “would have understood that ‘dynamic memory’ in Inoue
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`refers to a dynamic random access memory (DRAM), which is an integrated
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`circuit memory.” Dr. Baker’s testimony supports Petitioner’s assertions.
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`Ex. 1002, ¶ 68. Patent Owner did not file a Preliminary Response and,
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`therefore, has not disputed Petitioner’s position. We are sufficiently
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`persuaded that Inoue discloses “A sense amplifier arrangement for an
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`integrated circuit memory comprising.”
`
`Claim 4 further recites “for each of a plurality of sense amplifiers: a
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`sense amplifier latch circuit having a pair of nodes to which respective bit
`
`lines may be coupled.” Petitioner asserts that Inoue in combination with
`
`Min discloses this limitation. Pet. 17‒27.
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`Inoue discloses a “semiconductor device” in a “dynamic memory.”
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`Ex. 1007, 3‒4. Inoue discloses an embodiment, illustrated by Figure 6, with
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`multiple sense amplifiers, where each comprises a CMOS “F/F” or “latch”
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`that includes a pair of internal nodes “N1 and N2 correspond[ing] to bit
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`lines.” Ex. 1007, 4. However, Petitioner concedes that Inoue does not
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`expressly disclose a plurality of sense amplifiers or a plurality of bit line
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`pairs corresponding to such sense amplifiers. Pet. 20.
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`Min discloses a semiconductor memory device with a plurality of
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`sense amplifiers SA1‒SAN. Ex. 1008, 1:4‒8, Fig. 3B. Each sense amplifier
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`is coupled to a bit line pair (BLL and BLR). Ex. 1008, 2:5‒15, Fig. 3B. Each
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`sense amplifier is also coupled to a positive power supply (VCC) via driving
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`transistor Q10i and to ground (VSS) via driving transistor Q20i. Ex. 1008,
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`21:1‒13, Fig. 3B. Min discloses a common driving signal from driving
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`transistors Q10i and Q20i. Ex. 1008, Fig. 3B.
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`Petitioner asserts an ordinarily skilled artisan “would have been
`
`motivated to implement Inoue’s figure 6 circuit in a multi-column memory
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`system to create a dynamic memory having a plurality of bit line pairs with
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`each of bit line pairs coupled to a respective sense amplifier.” Pet. 21.
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`Specifically, Petitioner asserts an ordinarily skilled artisan would have been
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`motivated to implement Inoue’s circuitry of Figure 6 to implement a multi-
`
`column DRAM with multiple sense amplifiers as taught by Min because
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`practical DRAMs had multiple columns. Pet. 22. Petitioner further asserts
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`an ordinarily skilled artisan would have found it beneficial to use common
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`drive signals for the drive transistors as set forth in Min to reduce the
`
`amount of circuitry and, therefore, chip area, when compared to separate
`
`clock signals for each latch circuit. Pet. 24. Dr. Baker’s testimony supports
`
`these assertions. Ex. 1002, ¶¶ 34‒37, 73, 77.
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`Petitioner further asserts modifying Inoue’s apparatus to use a
`
`plurality of sense amplifiers and a plurality of bit line pairs as set forth in
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`Min would have been straightforward for an ordinarily skilled artisan
`
`because Inoue’s Figure 6 embodiment describes a single sense amplifier
`
`with a single bit line pair and Min discloses a plurality of sense amplifiers,
`
`each coupled to respective bit line pairs. Pet. 24‒25. According to
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`16
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`Petitioner, an ordinarily skilled artisan would have understood how to
`
`incorporate Inoue’s sense amplifier into Min’s multi-column memory. Id. at
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`25. Petitioner asserts such a combination would have been a predictable
`
`combination of known components according to known methods, and would
`
`have been consistent with working DRAM features. Id. at 25‒26. Dr.
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`Baker’s testimony supports these assertions. Ex. 1002, ¶¶ 74, 78.
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`In an obviousness analysis, there must be articulated reasoning with a
`
`rational underpinning to support a conclusion of obviousness. In re Kahn,
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`441 F.3d 977, 988 (Fed. Cir. 2006). Petitioner has articulated reasoning with
`
`a rational underpinning to support applying Inoue’s sense amplifier to a
`
`practical multi-column memory because working DRAMs use multi-column
`
`arrangements and Min’s common driving signals for multiple sense
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`amplifiers and their corresponding bit line pairs would help reduce the
`
`amount of circuitry in such a memory, thereby reducing the chip area. Dr.
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`Baker’s testimony amply supports this rationale. Ex. 1002, ¶¶ 72‒77.
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`Accordingly, we are sufficiently persuaded that the combination of Inoue
`
`and Min discloses “for each of a plurality of sense amplifiers: a sense
`
`amplifier latch circuit having a pair of nodes to which respective bit lines
`
`may be coupled” and that an ordinarily skilled artisan would have been
`
`motivated to combine the teachings of Inoue and Min.
`
`Claim 4 further recites “a local column read amplifier responsively
`
`coupled to the sense amplifier, and receiving at least one data read signal.”
`
`Petitioner concedes “[t]he combined Inoue-Min system does not expressly
`
`disclose this feature.” Pet. 27. However, Petitioner asserts that the Inoue-
`
`Min system in combination with Hamade discloses this limitation. Pet. 27‒
`
`35.
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`Hamade discloses a semiconductor memory device. Ex. 1009, 1:7‒9.
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`Figure 1 of Hamade, shown below, illustrates a “main part” of such a device
`
`and depicts a pair of bit lines BL and /BL and their associated circuitry. Id.,
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`3:1‒5, 7:4‒12, Fig. 1.
`
`Each bit line pair is associated with n-type sense amplifier 2 and p-
`
`type sense amplifier 3. Id., 1:47‒52, 7:4‒13, Fig. 1. Dr. Baker testifies that
`
`an ordinarily skilled artisan would understand that collectively these sense
`
`amplifiers form a latch similar to the latch in Inoue Figure 6. Ex. 1002,
`
`
`
`¶¶ 86.
`
`Hamade further discloses a drive circuit 9 comprised of transistors
`
`Q16‒Q19 is provided for each bit line pair. Ex. 1009, 7:14‒19, Fig. 1. Drive
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`circuit 9 “amplifies the potentials of the associated bit lines.” Ex. 1009, Id.
`
`Petitioner asserts an ordinarily skilled artisan would have understood drive
`
`circuit 9 to constitute a “column read amplifier” as claimed because drive
`
`circuit 9 “operate[s] to amplify the potentials on bit lines BL and /BL during
`
`a read operation, and allow[s] one of read only data lines RI and /RI to be
`
`discharged to ground during a read operation.” Pet. 29 (citing Ex. 1009,
`
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`3:61‒4:10, 8:8‒31, 8:52‒54). Petitioner asserts “drive circuit 9 is provided
`
`for each column because it is provided for each bit line pair (Ex. 1009,
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`7:22‒23), which is “related to memory cells in one column of the memory
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`cell array.’ (Id., 1:36‒39 (emphasis added), 7:4‒9; Ex. 1002, ¶ 87.).” Pet.
`
`29. Petitioner asserts the drive circuit 9 “would receive signals on read only
`
`data lines RI and /RI (‘receiving at least one data read signal’) in the
`
`combined system.” Id. at 32‒33 (citing Ex. 1009, 7:35‒39, Fig. 1). Dr.
`
`Baker’s testimony supports these assertions. Ex. 1002, ¶¶ 82‒95. We are
`
`sufficiently persuaded that the combination of Inoue, Min, and Hamade
`
`discloses “a local column read amplifier responsively coupled to the sense
`
`amplifier, and receiving at least one data read signal” as we have construed
`
`the term “local column read amplifier.”
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`Petitioner further asserts an ordinarily skilled artisan would have been
`
`motivated to combine the Inoue-Min system with Hamade’s drive circuit at
`
`each column because Hamade discloses that drive circuit 9 is provided for
`
`each bit line pair. Pet. 29. Petitioner asserts an ordinarily skilled artisan
`
`would have known how to assemble and implement all of the relevant
`
`circuitry into the combined system without undue experimentation. Id.
`
`Petitioner asserts an ordinarily skilled artisan would have looked to Hamade
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`to modify the Inoue-Min system because the combined Inoue-Min system
`
`does not disclose read circuitry that would typically be found in a practical
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`DRAM. Id. at 34. According to Petitioner, the combined Inoue-Min-
`
`Hamade system would allow “fast reading of the data carried by the bit
`
`lines.” Id. Petitioner asserts the combination would use known components
`
`according to known methods to yield predictable results. Id. at 34‒35.
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`Petitioner has articulated reasoning with a rational underpinning to
`
`support applying Hamade’s drive circuit 9 to the combined Inoue-Min
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`system because adding the drive circuit would allow fast reading of data
`
`carried on the bit lines. Dr. Baker’s testimony amply supports this rationale.
`
`Ex. 1002, ¶¶ 82‒95. Accordingly, we are sufficiently persuaded that an
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`ordinarily skilled artisan would have been motivated to combine the
`
`teachings of Inoue, Min, and Hamade.
`
`Claim 4 further recites “a local data write driver circuit coupled to
`
`receive write data during a write operation at a gate electrode of a transistor
`
`in said data write driver circuit and to apply a signal based upon receiving
`
`said write data to one of said latch circuit nodes.” Petitioner asserts that the
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`combined Inoue-Min-Hamade system discussed above discloses this
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`limitation. Pet. 35‒41. In particular, Petitioner asserts QN6 and QN8 form
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`one “local data write driver circuit” on the left side of Inoue’s Figure 6 and
`
`QN7 and QN9 form a second “local data write driver circuit” on the right side
`
`of the figure. Id. at 35‒36. Each of these data write driver circuits are only
`
`associated with the sense amplifier depicted in Figure 6. Dr. Baker’s
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`testimony supports Petitioner’s assertions. Ex. 1002, ¶ 100.
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`Petitioner further asserts each latch circuit is coupled to only one pair
`
`of data write driver circuits and, therefore, each data write driver circuit is a
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`“local data write driver circuit” as Petitioner proposes we construe the term.
`
`Pet. 37‒38. Dr. Baker’s testimony supports Petitioner’s assertion. Ex. 1002,
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`¶ 102.
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`Petitioner further asserts:
`
`Each of the local data write driver circuits at each column in the
`combined Inoue-Min-Hamade system would have been coupled
`
`
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`20
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`to (1) receive data at their gate terminals D and D̅ (“receive write
`data”) during a write operation at a gate electrode of a transistor
`QN6/QN8 or QN7/QN9 (“a transistor in said data write driver
`circuit”) in said data write driver circuit, and (2) apply a signal
`corresponding to a level ‘H’ or ‘L’ (“apply a signal”) based upon
`receiving data D or D̅ (“based upon receiving said write data”)
`to node N1 or N2 of the latch circuit (“one of said latch circuit
`nodes”) (red below). (Ex.1007, FIG. 6; Ex.1002, ¶103.)
`
`Pet. 38‒39. Patent Owner did not file a Preliminary Response and,
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`therefore, has not disputed Petitioner’s position. We are sufficiently
`
`persuaded that the combination of Inoue, Min, and Hamade discloses “a
`
`local data write driver circuit coupled to receive write data during a write
`
`operation at a gate electrode of a transistor in said data write driver circuit
`
`and to apply a signal based upon receiving said write data to one of said
`
`latch circuit nodes” as we have construed the term “loca
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