UNITED STATES PATENT AND TRADEMARK OFFICE
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`SAMSUNG ELECTRONICS CO. LTD.,
`Petitioner,
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`v.
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`PROMOS TECHNOLOGIES, INC.,
`Patent Owner.
`____________
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`Case IPR2017-01416
`Patent 6,172,554 B1
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`
`Record of Oral Hearing
`Held: August 16, 2018
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`Before JAMESON LEE, KEVIN F. TURNER, and JOHN A. HUDALLA,
`Administrative Patent Judges.
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
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`SAMSUNG ELECTRONICS CO. LTD.,
`Petitioner,
`
`v.
`
`PROMOS TECHNOLOGIES, INC.,
`Patent Owner.
`____________
`
`Case IPR2017-01416
`Patent 6,172,554 B1
`____________
`
`Record of Oral Hearing
`Held: August 16, 2018
`____________
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`Before JAMESON LEE, KEVIN F. TURNER, and JOHN A. HUDALLA,
`Administrative Patent Judges.
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`Case IPR2017-01416
`Patent 6,172,554 B1
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`APPEARANCES:
`
`ON BEHALF OF THE PETITIONER:
`PAUL M. ANDERSON, ESQUIRE
`NAVEEN MODI, ESQUIRE
`CHETAN BANSAL, ESQUIRE
`DANIEL ZEILBERGER, ESQUIRE
`Paul Hastings
`875 15th Street, N.W.
`Washington, D.C. 20005
`
`
`ON BEHALF OF PATENT OWNER:
`KEVIN JONES, ESQUIRE
`JERRY CHEN, ESQUIRE
`CRAIG R. KAUFMAN, ESQUIRE
`MICHAEL TING, ESQUIRE
`Tech Knowledge Law Group, LLP
`100 Marine Parkway
`Suite 200
`Redwood Shores, California 94065
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`
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`The above-entitled matter came on for hearing on Thursday, August
`16, 2018, commencing at 10:00 a.m., at the U.S. Patent and Trademark
`Office, 600 Dulany Street, Alexandria, Virginia.
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`P R O C E E D I N G S
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`JUDGE TURNER: Good morning. We are convened for oral
`argument for IPR2017-01416 which challenges U.S. patent 6,172,554. I am
`Judge Turner. And I'm here along with Judges Lee and Hudalla. I would
`like to start with appearances this morning. Can we begin with petitioner.
`Please approach the podium and let me know who is going to be arguing and
`who is represented for petitioner.
`MR. MODI: Good morning, Your Honors. Naveen Modi from
`Paul Hastings on behalf of petitioner, Samsung. With me I have my
`colleagues Dan Zeilberger, Paul Anderson and Chetan Bansal. And Mr.
`Zeilberger willing be presenting for Samsung today for the '554 patent.
`JUDGE TURNER: Thank you. And for patent owner?
`MR. KAUFMAN: Good morning, Your Honor. Craig Kaufman
`from Tech Knowledge Law Group for patent owner. With me today are my
`colleagues, Kevin Jones, Jerry Chen and Mike Ting. Mr. Jones will be
`presenting for the '554 patent this morning.
`JUDGE TURNER: Thank you and welcome to both sides. Each
`side, per the oral hearing order, will have 30 minutes to argue this morning.
`Petitioner has the ultimate burden of proving unpatentability and will argue
`first and may reserve rebuttal time. Patent owner will proceed thereafter to
`respond to petitioner's case and may respond on rebuttal if warranted. Are
`there any questions about the logistics of this morning from either side?
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`Any questions either side has? Seeing or hearing none, we would like to
`proceed. Petitioner.
`MR. ZEILBERGER: Thank you, Your Honor. If I may, may I
`approach the bench with physical copies of the demonstratives for the judges
`present?
`JUDGE LEE: Yes, please. Thank you.
`JUDGE TURNER: And would you like to reserve any rebuttal
`time this morning?
`MR. ZEILBERGER: Yes, Your Honor. I would like to reserve
`five minutes of rebuttal time.
`JUDGE TURNER: Okay. I will ask Judge Lee to set the clock.
`When he indicates that it's set up, you may begin.
`JUDGE LEE: Let me say, it's been a while since I operated this.
`Let me just set it in my mind and I'll look at the clock on the wall. I'll give
`you a two-minute warning when your 25 minutes are about to be due.
`MR. ZEILBERGER: Thank you, Your Honor.
`JUDGE TURNER: Thank you. You may proceed.
`MR. ZEILBERGER: Good morning and may it please the Board,
`please turn to slide 2. So slide 2 just has a reproduction of the instituted
`grounds. I'm sure Your Honors are well aware of what's at issue here. For
`purposes of today, I'm going to focus on the two grounds that have been at
`issue post institution in terms of arguments by the parties, the anticipation
`ground based on Ito and the obviousness ground based on Park.
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`Turning to slide 4, please, so slide 4 has claim 22 which is at issue
`in the anticipation ground based on Ito. As Your Honors see, it has
`essentially two core limitations, a voltage generator and a detector circuit.
`The voltage generator generates a bias voltage. The detector circuit detects
`the bias voltage and regulates the voltage generator to maintain the bias
`voltage at a substantially constant negative value. The detector circuit
`allows the bias voltage to get arbitrarily close to the ground voltage but not
`allowing the bias voltage to become positive.
`Slide 5, please. So just briefly going over Ito, on slide 5 we have
`Figure 9 which is the figure that we relied on in our petition. At the high
`level what's happening here is the voltage of VBB is being monitored. And
`essentially, if it goes too far below the threshold voltage of the PMOS
`transistor 5, then the pumping circuit will turn on and bring it back up. And
`if it goes too high -- if it goes too low, then the pumping circuit will be
`turned back off and then VBB will be allowed to rise again.
`If you go to slide 8, please, that's what you see on slide 8, which is
`Figure 2 of Ito. You can see VBB is rising when charge pumping is off.
`And then after VBB exceeds the threshold voltage of the transistor, charge
`pumping turns on, it goes back down and then the process repeats.
`Slide 9, please. So there's actually only one limitation that's in
`dispute between the parties, and that's what you see here highlighted in
`yellow, the detector circuit allowing the bias voltage V1 to get arbitrarily
`close to the ground voltage.
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`Slide 11, please. So on the bottom half of slide 11, you see what --
`this is essentially patent owner's argument, which is that this claim element
`requires a circuit that allows the designed target value of VBB to be close to
`zero volts, in any case closer to zero volts than one threshold below. And
`the word that I want to key in on there is the word "designed."
`If you turn to slide 13, I think it provides a clearer picture of what
`patent owner is essentially arguing in this case, which is that patent owner is
`saying that even though VBB and Ito, in fact, gets arbitrarily close to ground
`voltage, it's not designed to do so but instead is only happening because of
`circuit delay. But the claim doesn't say anything about the reason why the
`voltage is allowed to get arbitrarily close to ground voltage. And if you go
`back to slide 9, I think that is made clear if you read the claim language. All
`the claim requires is that the detector circuit allows the bias voltage to get
`arbitrarily close to ground voltage. It doesn't say anything about the
`reasoning behind whether the person designing the circuit had in mind
`circuit delay, whether the person designing the circuit had in mind
`something else. It simply has the result that the detector circuit allows what
`it says to happen to happen.
`So slide 14, I think, is an important one because patent owner has
`essentially argued that Ito is no different than the prior art that it highlighted
`in its patent and that it overcame during prosecution. And that's simply not
`true. If you look at Figure 3B, I think it provides a pretty accurate
`representation of how patent owner characterized the prior art that was
`considered by the examiner. What you see is that the VBB is limited to
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`going no higher than the threshold voltage of the transistor in the prior art.
`It's capped there. You don't see VBB going above the threshold voltage.
`In contrast to that, if we go back to slide 10, you can see in Ito
`that's not the case. VBB is allowed to go above the threshold voltage, and
`that is not like the prior art which we see in Figure 3B of the '554 patent.
`Go to slide 15, please. Turning to the Park/Baker obviousness
`combination, go to slide 16, please. So I would like to focus attention on
`claim 1 which I know is a long claim, but actually, there's really no dispute
`that Park discloses nearly every limitation in the claim. There's only two
`limitations that are in dispute between the parties, and that's what I would
`like to focus on today.
`If you go to slide 17, please, so on slide 17 we have Figures 5 and
`1 from Park which we rely on in our petition. On the left-hand side you see
`the circuitry that corresponds to what we mapped to the detector circuit
`where VBB is again being monitored. It generates what Park refers to as an
`OSCEN signal which is then, if you turn to Figure 1, fed into what we've
`mapped to the voltage generator, feeds into the VBB oscillator which
`generates an OSC signal which feeds into the VBB pump which is what
`corresponds to the voltage generator.
`Slide 20, please. So that takes us to the first limitation that's in
`dispute. It says that we have a circuit for providing a bias voltage which is
`substantially insensitive to variations of a power supply voltage. That's
`exactly what Park teaches. If we go back to slide 18, I think we can see
`why. So this is a zoomed-in version of the detector circuit. And the feature
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`here that I want to key in on is what Park refers to as voltage reference
`generators denominated number 60. It's in the top left of the figure.
`And what Park explains is that because of the existence of VREF
`generator, the current that's flowing into node 51 and out of node 51 isn't
`affected by VCC fluctuations. And it explains why as well. If you look at
`Park at column 4, line 66 to column 5, line 14, it essentially explains that
`current IP prime, which you see right in the middle of the figure, it's an
`equation that you can look at, but two of the terms that you see to generate
`that current value are ICC -- excuse me, VCC minus VREF. But then Park
`also explains that VREF itself is just a constant amount away from VCC. So
`you essentially have VCC minus parentheses VCC minus K. And then the
`VCC terms cancel out and VCC has no effect on the current.
`If we could turn to slide 21, please, so patent owner argues that
`there's no disclosure in either of the prior art references of a circuit that
`produces a bias voltage that's substantially insensitive to power supply
`voltage variations. That's simply not correct. For one, I think it's important
`to keep in mind that the claims don't recite complete insensitivity. They
`only recite substantial insensitivity.
`Having said that, if we go to the next slide, please, slide 22, we see
`in Figure 8 of Park three different lines charting VCC versus VBB. And A
`and B, you can see A, B and C for the three lines. A and B, Park explains,
`are prior art, what it considers prior art circuit designs. And line C is Park's
`inventive circuit design. And what you can see here -- and I think even
`before we get there, I think it's important to note the axes that you see here
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`because to be sure, all three of the lines have a downward slope, but if you
`look at the VCC line, it goes from 3 volts all the way to 6 volts. If you look
`at the VBB line, it's actually charted a little bit differently. It goes in tenth
`increments, from -1.4 volts to -1.8 volts. And while lines A and B have
`somewhat of a more dramatic downward trend, line C actually only goes
`from a slight bit above -1.5 volts to a slight bit below -1.5 volts. So we're
`probably talking about orders of hundredths of volts of downward trend for
`VBB even though VCC is going all the way from 3 volts to 6 volts.
`If you go to slide 23, please, and I think what's also equally
`important is that Park itself recognizes that it's insensitive to power supply
`voltage variations. You can see at column 1, lines 10 to 13, which is the top
`of slide 23, that Park recognizes that although the present invention is
`suitable for a wide scope of applications, it is particularly suitable for
`constantly maintaining a back bias voltage with respect to the variation of an
`external voltage. And then below that, column 6, lines 39 to 42, Park
`explains that even if the external voltage VCC is varied, the threshold
`voltage VT of the NMOS pull-down transistor N is constantly maintained
`because the back bias voltage VBB is stable.
`Please turn to slide 24. So that takes us to the other limitation
`that's in dispute with respect to the Park/Baker combination, and that's what
`you see highlighted on slide 24. It says that the inverter, which is referring
`to the inverter of the sensing circuit which is of the detector circuit,
`possesses a trip point which is substantially insensitive to power supply
`voltage variations.
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`Slide 25, please. So what you see highlighted on slide 25 is
`inverter IN1 from Park which is what we generally mapped to the inverter
`that's recited in the claim, barring the modification I'll talk to in a minute.
`But what I want to key in on here is what you see as the input of inverter 1
`which is node 51.
`If you turn to the next slide, slide 26, please, so slide 26 has the
`testimony from Dr. Baker, petitioner's expert, paragraphs 105 and 106. As
`Dr. Baker testified, with respect to the input to the inverter, as we just talked
`about with respect to the previous limitation, that input is substantially
`insensitive to power supply voltage variations because of Park's use of the
`voltage reference generator. Having said that, Park doesn't explicitly talk
`about making the trip point of the inverter also insensitive to power supply
`voltage variations, and that's where Baker comes in.
`Could you turn to slide 32, please. So slide 32 has additional
`testimony from Dr. Baker as well as an excerpt from the Baker textbook,
`specifically the equation outlining how to determine the voltage trip point of
`an inverter. And there's a few different terms there, and I think it's important
`to keep in mind what they are. On the left-hand side you see VSP. The
`Baker textbook refers to it as a voltage switching point, but there's no
`dispute between the parties that that is referring to the trip point. Then you
`also see a VDT term that's referring to the power supply voltage, also a
`VTHN and VTHP variables which are referring to the threshold voltages of
`the NMOS and PMOS transistors of the inverter as well as a beta N and beta
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`P variable, and those are referring to transconductance parameters of the
`NMOS and PMOS transistors.
`And as Dr. Baker testified, a person of ordinary skill in the art
`would see that having this variable in front of them, they could understand
`how to minimize the effect of VDD. And Dr. Baker also explained why that
`is, because essentially you have a numerator with two different terms being
`added, and if you make the first one really big, the second one which has the
`VDD term will be minimized. And Dr. Baker also testified how that would
`be done. It's pretty simple. You essentially just make beta N much bigger
`than beta P. Then the left-hand side of the numerator gets bigger and VDD
`goes away.
`Go to slide 34, please. What's critical here is that the Baker
`textbook also provides an example of exactly what I just described. It's
`homework problem 11.1 which is given to students to do. And the
`homework problem tells students design and simulate the DC characteristics
`of an inverter with VSP approximately equal to VTHN. And I say that's
`exactly what I described because if you make the beta N term much bigger
`than the beta P term, the equation reduces to VSP being approximately equal
`to VTHN.
`If we go to slide 36, please, so slide 36 includes an admission from
`patent owner's declarant. And it shows there's actually no dispute between
`the parties that an inverter sized in the way that petitioner has proposed
`would, in fact, have a trip point that is substantially insensitive to power
`supply voltage variations. We asked him, question: So what the '554 patent
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`is teaching is that if the switching point of an inverter is approximately equal
`to the threshold voltage of the NMOS transistor and the inverter, then the
`inverter is substantially insensitive to power supply voltage variations?
`And he answered: Just one second. Yeah, pretty much.
`That's exactly what we just saw in the homework problem of the
`Baker textbook and as we saw in the equation of the Baker textbook
`suggesting to people of ordinary skill in the art.
`JUDGE TURNER: Counsel, let me just, before you move on, let
`me ask a question. In terms of solving this problem in the Baker textbook, is
`the only way to reach the requirements of the problem to do what patent
`owner is specifying or are there other -- I mean, it's an equation. Are there
`other ways to set the variables such that you reach the requirements?
`MR. ZEILBERGER: So if we go back to --
`JUDGE TURNER: And I can repeat my question because maybe
`it wasn't clear.
`MR. ZEILBERGER: I think I understood it, Your Honor. If I
`didn't, please correct me. If you go back to slide 32 where we can see the
`equation, I think that might be helpful. So essentially what this equation is
`giving you is it characterizes the trip point of the inverter. So really you
`could plug any values you want into these variables and manipulate it so that
`you get a given trip point for an inverter.
`But what petitioner has proposed given Park's motivation, express
`motivation to minimize the effect of the back bias voltage in a circuit that's
`driving the back bias voltage and given Baker's additional suggestion with
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`the homework problem saying make it so that VSP equals VTHN, the way
`you would do that, and I believe it's the only way to do that is to make beta
`N much larger than beta P.
`JUDGE TURNER: Okay.
`MR. ZEILBERGER: I would also note that for purposes of the
`claim, the claim doesn't specify any particular way of manipulating this
`equation. Although, while the '554 patent doesn't, in fact, provide this
`equation, I would say it's governed by the same laws of physics that Baker
`describes in its textbook.
`If you go to slide 37, please, so one of the arguments that patent
`owner has made is that we shouldn't be allowed and the Board shouldn't be
`allowed to look to the homework problem in Baker that we saw a moment
`ago which specifically sets the switch point as the NMOS transistor
`threshold because according to patent owner we didn't rely on it in our
`petition. And that's simply incorrect.
`If you look at the bottom half of slide 37, it's an excerpt of our
`petition. It's describing the equation we just talked about. It cites to the
`Baker declaration paragraph 108 which is the paragraph we were just talking
`about. And in Dr. Baker's declaration, he testified that one of ordinary skill
`in the art looking at this equation and understanding the full context of it
`which also has the homework problem which is discussed in Dr. Baker's
`declaration, one of ordinary skill in the art would have arrived at the
`proposed modification.
`Please turn to slide 30.
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`JUDGE HUDALLA: But you don't specifically bring out that
`equation or that -- that homework problem in your petition?
`MR. ZEILBERGER: You won't find the homework problem
`explicitly in our petition. The homework problem is in the full context of
`understanding how one of ordinary skill in the art would understand the
`equation that's in Baker. And the equation certainly is discussed in our
`petition.
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`JUDGE HUDALLA: Does paragraph 108 actually refer to the
`homework problem?
`MR. ZEILBERGER: Yes, Your Honor. If we go back to slide --
`JUDGE TURNER: Thirty-four.
`MR. ZEILBERGER: It's in paragraph 108, Your Honor.
`JUDGE TURNER: At the bottom of your slide 34, it says -- it
`cites it there.
`MR. ZEILBERGER: That's right. That's right, Your Honor.
`JUDGE HUDALLA: Thank you.
`MR. ZEILBERGER: Please turn to slide 30. So patent owner has
`also argued that nothing in the Baker textbook tells a person of ordinary skill
`in the art to select the specific values necessary to provide the claim
`structure. As I just explained, that's incorrect. The equation certainly
`suggests setting the values in the way that petitioner has proposed and the
`homework problem explicitly suggests to do so.
`Please turn to slide 31. Patent owner has also argued that the
`claimed inverter design is a nonstandard design. I think that's misplaced for
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`two reasons. For one, it's somewhat irrelevant whether or not it's a standard
`or nonstandard design for an inverter. The question is whether Park and
`Baker would have suggested to a person of ordinary skill in the art to create
`such an inverter.
`But having said that, I think perhaps even equally relevant here is
`that it's inconsistent with what patent owner described in their own
`specification. If we turn to slide 41, these are two key passages in the '554
`patent that I think the Board needs to keep in mind when it analyzes this
`issue. In column 4, lines 7 to 10, it treats this limitation almost as an
`afterthought and says that in some embodiments simple circuit techniques
`such as proper ratioing of the sizes of the pull-up and pull-down transistors
`of inverter 12 can be used to eliminate the dependence of inverter 12 trip
`point on VCC.
`And then at column 1, lines 55 to 60, in fact, in describing the prior
`art, because this passage is talking about a prior art example that the '554
`patent is trying to improve upon, it actually appears to concede that this
`limitation was in the prior art. It says that this assumption, when it's talking
`about the prior art, assumes that inverter 12 in the prior art is designed so
`that its trip point is insensitive to VCC.
`So in this context we have Park that's explicitly telling people of
`skill to minimize the effect of voltage variations on VBB. We have Baker
`that arms the person of ordinary skill in the art with an equation telling you
`how to determine a tip point. We have the Baker textbook also providing a
`homework problem that provides an active example of what's described in
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`the claim. And given all that context and the '554 patent conceding that this
`involves simple circuit techniques, petitioner proposes that the Park/Baker
`combination would have rendered this limitation obvious.
`And if there are no further questions, I'll reserve the rest of my
`time for rebuttal.
`JUDGE TURNER: Thank you. I have it as nine minutes for
`rebuttal.
`MR. JONES: Good morning, Your Honors. If I may approach
`with hard copies of the demonstratives.
`JUDGE LEE: Thank you.
`MR. JONES: Good morning. I would like to address two of the
`three arguments that opposing counsel has discussed this morning. The first
`issue is whether Ito anticipates claim 22 focused on the arbitrarily close to
`ground voltage language. And the second issue is the inverter trip point
`issue which he addressed last.
`So first talking about claim 22, the language "arbitrarily close to
`ground voltage," I want to start back in the disclosure in the patent of exactly
`what the prior art was in the patent and what our invention is, because I
`think in this discussion of the claim, we are losing track of what the
`invention is and how it's better than the prior art.
`So on slide 2 we have an image here of Figure 3A which is the
`prior art disclosed in the patent itself. As you can see, the NMOS transistor
`M30 is grounded at its gate, and as a result, the maximum VBB that this
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`circuit allows is a threshold below zero. That's what Figure 3B shows in the
`hash the maximum value being -VTN.
`Now, the applicants say that's not good enough; we want VBB to
`be closer to zero. So on slide 3, in Figure 5A they replaced that ground
`terminal on transistor M30 with this circuit comprising M55 and M56. What
`that circuit does is it brings up the gate voltage on M30 to the threshold
`value. And as a result, as you can see in Figure 5B, the maximum VBB
`moves up by a threshold voltage, of course, because that was the gate
`voltage, and that brings VBB up to just below ground, which was the goal.
`Now, skipping ahead to slide 8, Ito is exactly the same as Figure
`3A that we just looked at on slide 2. On slide 8, Ito shows PMOS transistor
`5 which has a terminal connected to its gate, and as a result, the maximum
`value of VBB in Ito is a threshold below zero, just like Figure 3A. And Mr.
`Brahmbhatt even says that Ito suffers -- on slide 12 that Ito suffers the same
`problems as Figure 3A in the '554 patent.
`So from this point the disclosure in Figure 3A of the prior art
`operates identically to Ito. So whatever that term means, arbitrarily close to
`ground voltage, and I will address that going forward, whatever that means,
`it can't cover the prior art that we disclosed in the patent.
`So Samsung points to the timing diagram in Ito which is on slide 9.
`And they point to the fact that the VBB rises above VTHP and they say,
`therefore, that proves that Ito gets you closer to zero than the threshold
`below and therefore, that's arbitrarily close to ground voltage.
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`Now, this everyone agrees, both experts agree and Ito even says
`the rise of VBB above the threshold below zero, that rise is due to circuit
`delay. For example, the delay that it takes to get the voltage up higher to
`trigger the charge pump and charge pump startup time. Those problems
`exist in Figure 3A too. That's what Mr. Brahmbhatt says.
`Now, the fact that Figure 3B, and I'm going back to slide 2 again to
`look at the prior art in our patent. The fact that Figure 3B has a perfectly flat
`line at -VTN doesn't mean that in actual conditions the VBB value doesn't
`leak above that value. Our patent is focused on the idealized design value
`that the circuit allows, the maximum VBB target. And they use the word
`"target" throughout the patent.
`Ito was focused on in actual operation the circuit has some delay
`and it leaks above the target value and Ito is trying to improve that leakage
`and bring it closer to the target value. So they are focused on different
`things, but in actuality, they both suffer the same problem because both have
`the target value of the threshold below.
`JUDGE TURNER: Counsel, let me ask at this point, it seems like
`you are sort of taking a position that there's no way that claim 22 could read
`on the prior art, but isn't that just the sort of error that we are supposed to
`catch here in post-grant proceedings? I mean, I certainly can envision a
`scenario wherein the examiner allows the claim, it reads on patent owner's
`own disclosed prior art, and you are sort of saying, well, no, that's
`impossible. So help me figure that conundrum out.
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`MR. JONES: Sure. Well, I think the answer lies in the
`understanding of arbitrarily close to ground voltage. That phrase, while it
`hasn't been posed as a rigid claim construction dispute between the parties,
`our understanding and Mr. Brahmbhatt's understanding of that is that we are
`discarding minor circuit delays, temperature fluctuations that cause electron
`mobility differences, charge pump startup times, all the things Ito was
`concerned with, you are discarding that and you are focused in this phrase
`just on the circuit allows you to get closer to zero than a threshold below.
`JUDGE TURNER: Okay. And now that we've moved on to claim
`construction, this arbitrarily close, is there somewhere in the specification of
`the '554 that you can point me to that says here is what arbitrarily close
`means?
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`MR. JONES: If you'll allow me about ten seconds to find an
`answer to that, Your Honor.
`JUDGE TURNER: I'll allow you more than ten seconds. You can
`take up to a half hour if you want, but I would suggest that probably
`wouldn't be within patent owner's best interest.
`MR. JONES: Sure. I think the best place to look would be in
`column 3 at line 14, and it's describing the invention over the prior art. It's
`in the background here, and they are saying some generators include a
`circuit that allows VBB to get arbitrarily close to zero volts, and they say in
`some embodiments like this claimed embodiment, this is achieved by
`biassing the gate of transistor M30 to the threshold voltage VTN. So here
`they are associating that claim language, arbitrarily close, with the two
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`transistors in Figure 5A that I talked about in slide 3. They are saying those
`two transistors are what you get you closer to zero and then using the
`language "arbitrarily close to zero volts."
`JUDGE TURNER: Let's say we were, if I were shifting over to an
`infringement context, I mean, ballpark, which is arbitrarily close? A
`microvolt? A tenth of a volt? How close is close? I mean, you have a claim
`term here that says arbitrarily close to zero, and if I want to know if I
`infringed this claim, how do I know what arbitrarily close is? Obviously,
`zero is problematic, but what's arbitrarily close?
`MR. JONES: Certainly this is because this is zero volts. The
`example that the patent uses which is in column -- I believe it was in column
`2. The example the patent uses is -1 to zero volts. In column 2 at line 54 it
`says lower target values in the range of -1 to zero, for example, minus a half
`of a volt are highly desirable.
`Now, of course that depends on the operational voltage of the chip.
`And technology has improved and voltages have become lower. So I don't
`think the applicant intended to restrict the invention to just -1 to zero. But I
`think it is clear that you need a circuit different than the prior art. You need
`a circuit that brings up that gate voltage higher than ground, which Ito and
`Figure 3A did not do.
`JUDGE HUDALLA: Is it your contention that Ito doesn't -- when
`we look at this Figure 2 of Ito doesn't meet what you just quoted to us from
`column 2 of the patent?
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`MR. JONES: Yes. We believe this figure does not meet that
`language of the specification.
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