Paper 7
`Trials@uspto.gov
`571-272-7822 Entered: November 30, 2017
`
`
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`SAMSUNG ELECTRONICS CO., LTD.,
`Petitioner,
`
`v.
`
`PROMOS TECHNOLOGIES, INC.,
`Patent Owner.
`____________
`
`Case IPR2017-01416
`Patent 6,172,554 B1
`____________
`
`DECISION
`Institution of Inter Partes Review
`35 U.S.C. § 314(a) and 37 C.F.R. § 42.108
`
`
`
`
`
`
`
`
`
`Before JAMESON LEE, KEVIN F. TURNER, and
`JOHN A. HUDALLA, Administrative Patent Judges.
`
`TURNER, Administrative Patent Judge.
`
`
`
`
`
`Trials@uspto.gov
`571-272-7822 Entered: November 30, 2017
`
`
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`SAMSUNG ELECTRONICS CO., LTD.,
`Petitioner,
`
`v.
`
`PROMOS TECHNOLOGIES, INC.,
`Patent Owner.
`____________
`
`Case IPR2017-01416
`Patent 6,172,554 B1
`____________
`
`DECISION
`Institution of Inter Partes Review
`35 U.S.C. § 314(a) and 37 C.F.R. § 42.108
`
`
`
`
`
`
`
`
`
`Before JAMESON LEE, KEVIN F. TURNER, and
`JOHN A. HUDALLA, Administrative Patent Judges.
`
`TURNER, Administrative Patent Judge.
`
`
`
`
`
`
`IPR2017-01416
`Patent 6,172,554 B1
`
`I. INTRODUCTION
`Samsung Electronics Co., Ltd. (“Petitioner”) filed a Petition for inter
`partes review of claims 1–3, 14–16, 22, and 28–36 of U.S. Patent No.
`6,172,554 B1 (Ex. 1001, “the ’554 Patent”). Paper 1 (“Pet.”). ProMOS
`Technologies Inc. (“Patent Owner”) did not file a Preliminary Response.
`Institution of an inter partes review is authorized by statute when “the
`information presented in the petition . . . and any response . . . shows that
`there is a reasonable likelihood that the petitioner would prevail with respect
`to at least 1 of the claims challenged in the petition.” 35 U.S.C. § 314(a);
`see 37 C.F.R. § 42.108 (regarding institution of inter partes review);
`37 C.F.R § 42.4(a) (delegating authority to institute trial to the Board).
`Upon consideration of the Petition, we conclude that the information
`presented shows that there is a reasonable likelihood that Petitioner would
`prevail in establishing the unpatentability of at least one of the challenged
`claims of the ’554 Patent.
`
`A. Related Matters
`The parties inform us that the challenged patent is the subject of a
`district court proceeding in the District of Delaware, captioned ProMOS
`Technologies, Inc. v. Samsung Electronics Co., Ltd., No. 1:16-cv-00335-
`SLR (D. Del.). Pet. 1, Paper 4. In that action, Patent Owner has asserted
`other patents against Petitioner, and Petitioner has filed inter partes review
`petitions against those other patents in IPR2017-01412, IPR2017-01413,
`IPR2017-01414, IPR2017-01415, IPR2017-01417, IPR2017-01418, and
`IPR2017-01419. Id.
`Petitioner also identifies these inter partes review proceedings,
`initiated by petitions filed by Petitioner, as involving additional patents
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`asserted by Patent Owner against Petitioner in ProMOS Technologies, Inc. v.
`Samsung Electronics Co., Ltd., No. 1:15-cv-00898-SLR-SRF (D. Del.):
`IPR2017-00032; IPR2017-00033; IPR2017-00035; IPR2017-00036;
`IPR2017-00037; IPR2017-00038; IPR2017-00039; and IPR2017-00040.
`Pet. 1–2.
`
`B. The ’554 Patent
`The ’554 Patent is titled “Power Supply Insensitive Substrate Bias
`Voltage Detector Circuit.” Ex. 1001, [54]. The patent issued on January 9,
`2001 from an application filed on September 24, 1998. Id. at [45], [22].
`The patent is directed to “a circuit provid[ing] a bias voltage V1 which is
`substantially insensitive to variations of a power supply voltage powering
`the circuit.” Id. at Abstract, 1:6.
`
`1. The Written Description
`The ’554 Patent discloses that voltage generating circuits known as
`back-bias generators may be used in semiconductor devices which require
`the substrate region to be biased to a predetermined voltage, such as in
`dynamic random access memories (DRAM), where the substrate region is
`negatively biased to prevent the DRAM cells from losing stored information.
`Ex. 1001, 1:8–15. Such a back-bias generator includes a voltage multiplier
`circuit, commonly referred to as charge pump, for providing the negative
`Back-Bias Voltage (VBB), and usually includes a VBB detector circuit, which
`regulates the charge pump such that VBB is maintained as close to a target
`VBB value as possible. Id. at 1:15–21. The detector circuit constantly senses
`the VBB voltage level, and if VBB becomes more negative than the target VBB,
`the detector circuit turns off the charge pump thereby allowing VBB to drift
`back to the target VBB; and if VBB becomes less negative than the target VBB,
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`IPR2017-01416
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`the detector circuit turns on the charge pump to pump VBB back to the target
`VBB. Id. at 1:22–28.
`A conventional VBB detector circuit 17 is illustrated in Figure 1,
`reproduced below, along with Figure 3A illustrating an alternative,
`conventional VBB detector circuit 37.
`
`
`The conventional VBB detector circuit 17, in Figure 1, has serially
`connected resistors R1 and R2 coupled between the power supply VCC and
`VBB terminal 15, where VCC is provided by a power supply external to the
`device, and VBB is generated internally by a charge pump, which is not
`shown. Id. at 1:29–33. Inverter 12 has its input terminal connected to
`node 11 which is the node between R1 and R2, and its output connected to
`the charge pump. Id. at 1:33–37.
`Resistors R1 and R2 are selected so that the voltage VA equals the trip
`point of inverter 12, such that if the charge pump causes VBB to become
`more negative than the target value, VA drops below the trip point of
`inverter 12, causing Q10 to go high. Id. at 1:43–49. The high level at Q10
`turns off the charge pump, allowing VBB to increase back to the target value.
`Id. Alternatively, if VBB becomes less negative than the target VBB, VA rises
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`above the trip point of inverter 12, causing Q10 to go low, which turns on
`the charge pump causing VBB to become more negative. Id. at 1:49–54.
`Figure 3A also shows a prior art detector circuit 37 which prevents
`VBB from becoming positive, with that being identical to circuit 17 of
`Figure 1 except that NMOS transistor M30 is connected between node 11
`and R2, where that transistor causes the charge pump to turn on and pump
`VBB to a more negative voltage. Id. at 2:29–37.
`The ’554 Patent details that the conventional circuits have drawbacks,
`including that VBB varies with changes to VCC, such that higher voltages can
`result in increases in junction leakage. Id. at 1:55–67. As well, the
`conventional circuits may not prevent VBB from becoming positive, which
`can damage the device. Id. at 2:23–28. Because of these drawbacks, the
`’554 Patent discloses embodiments of VBB detector circuits wherein VBB is
`made insensitive to VCC variations, and also wherein the range of possible
`VBB values is increased without compromising power consumption. Id. at
`2:56–59. Figures 4A and 5A are reproduced below:
`
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`Patent 6,172,554 B1
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`Figure 4A shows a voltage detector circuit 47 where the resistor R1 of
`Figure 1 is replaced with a power-supply-voltage-insensitive current
`source 46, connected between VCC and node 11. Id. at 3:45–57. Resistor R2
`is connected between node 11 and VBB terminal 15, and inverter 12 has its
`input terminal connected to node 11 and its output terminal represents the
`output terminal Q10, which is connected to an input terminal 13 of a charge
`pump 48. Id. Figure 5A illustrates another VBB detector circuit 57 with
`transistors M51, M52, M53, and M54 collectively implementing a constant
`current source 46. Id. at 4:18–21.
`
`2. Illustrative Claims
`Petitioner challenges claims 1–3, 14–16, 22, and 28–36 of the
`’554 Patent, of which claims 1, 15, 22, and 30 are independent. Pet. 1.
`Claims 1 and 22 are illustrative of the subject matter of the challenged
`claims and read as follows:
`1. A circuit for providing a bias voltage V1 which is
`substantially insensitive to variations of a power supply voltage
`powering the circuit, the circuit comprising:
`a detector circuit for generating a signal from the power
`supply voltage and the bias voltage V1, wherein said signal is
`substantially insensitive to variations in the power supply voltage
`while being responsive to the bias voltage V1; and
`a voltage generator for generating the bias voltage V1 on
`an output terminal, wherein the voltage generator is responsive
`to said signal such that the detector circuit and the voltage
`generator are operable to maintain the bias voltage V1 at a
`substantially constant value over power supply voltage
`variations;
`wherein the detector circuit comprises:
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`a bias circuit for biasing a first node to a node voltage, the
`bias circuit receiving the power supply voltage and the bias
`voltage V1; and
`a sensing circuit for generating said signal in response to
`the node voltage at the first node;
`wherein the power supply voltage is provided across a
`power supply terminal and a reference terminal, and the bias
`circuit comprises:
`a current source connected between the power supply
`terminal and the first node, the current source being substantially
`insensitive to power supply voltage variations; and
`a resistor connected between the first node and the output
`terminal of the voltage generator circuit;
`wherein the current source comprises a first transistor
`connected between the power supply terminal and the first node,
`the first transistor being biased such that a current through the
`first transistor is substantially insensitive to power supply
`voltage variations;
`wherein the gate to source voltage of the first transistor is
`made substantially
`insensitive
`to power supply voltage
`variations;
`wherein the first transistor is a field effect transistor biased
`in the saturation mode;
`wherein the sensing circuit comprises an inverter having
`an input terminal connected to the first node, the inverter
`possessing a trip point which is substantially insensitive to power
`supply voltage variations, whereby the bias voltage V1 is
`obtained when the node voltage and the trip point of the inverter
`are substantially the same.
`
`22. A circuit comprising:
`a voltage generator for generating a bias voltage V1; and
`a detector circuit for detecting the bias voltage V1 and
`regulating the voltage generator to maintain the bias voltage V1
`at a substantially constant negative level, the detector circuit
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`allowing the bias voltage V1 to get arbitrarily close to the ground
`voltage but not allowing the bias voltage V1 to become positive.
`Ex. 1001, 6:23–7:3, 8:67–9:7.
`
`C. Asserted Grounds of Unpatentability
`Petitioner contends that claims 1–3, 14–16, 22, and 28–36 of the
`challenged patent are unpatentable under 35 U.S.C. §§ 102, 1031 based on
`the following specific grounds (Pet. 3, 9–76).
`
`Reference(s)
`
`Ito2
`Ito and Kim3
`Park4 and Baker5
`Park, Baker, and Tsukada6
`Park, Baker, and Young7
`
`Challenged Claim(s)
`Basis
`§ 102(e) 22
`§ 103
`28 and 29
`§ 103
`1–3, 14–16, 30, 31, and 36
`§ 103
`32–34
`§ 103
`35
`
`In its analysis, Petitioner relies on citations to the asserted references and the
`declaration testimony of Dr. R. Jacob Baker (Ex. 1002).
`
`
`1 The Leahy-Smith America Invents Act (“AIA”), Pub. L. No. 112–29, 125
`Stat. 284, 287–88 (2011), revised 35 U.S.C. §§ 102, 103, effective
`March 16, 2013. Because the challenged patent was filed before March 16,
`2013, we refer to the pre-AIA version of §§ 102, 103 in this Decision.
`2 U.S. Patent No. 5,744,998, filed Dec. 3, 1996, issued Apr. 28, 1998
`(Ex. 1005, “Ito”).
`3 U.S. Patent No. 5,602,506, issued Feb. 11, 1997 (Ex. 1006, “Kim”).
`4 U.S. Patent No. 5,886,567, filed Jul. 9, 1997, issued Mar. 23, 1999
`(Ex. 1007, “Park”).
`5 R. Jacob Baker et al., CMOS Circuit Design, Layout, and Simulation,
`(Stuart K. Tewksbury ed., IEEE Press 1997) (Ex. 1008, “Baker”).
`6 U.S. Patent No. 5,818,290, filed Feb. 14, 1996, issued Oct. 6, 1998
`(Ex. 1009, “Tsukada”).
`7 U.S. Patent No. 4,710,647, issued Dec. 1, 1987 (Ex. 1012, “Young”).
`8
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`II. DISCUSSION
`
`A. Principles of Law
`To establish anticipation, each and every element in a claim, arranged
`as recited in the claim, must be found in a single prior art reference.
`Net MoneyIN, Inc. v. VeriSign, Inc., 545 F.3d 1359, 1369 (Fed. Cir. 2008);
`Karsten Mfg. Corp. v. Cleveland Golf Co., 242 F.3d 1376, 1383 (Fed. Cir.
`2001). While the elements must be arranged in the same way as is recited in
`the claim, “the reference need not satisfy an ipsissimis verbis test.” In re
`Gleave, 560 F.3d 1331, 1334 (Fed. Cir. 2009); In re Bond, 910 F.2d 831,
`832–33 (Fed. Cir. 1990)). Thus, identity of terminology between the prior
`art reference and the claim is not required. “A reference anticipates a claim
`if it discloses the claimed invention ‘such that a skilled artisan could take its
`teachings in combination with his own knowledge of the particular art and
`be in possession of the invention.’” In re Graves, 69 F.3d 1147, 1152 (Fed.
`Cir. 1995). That means prior art references must be “considered together
`with the knowledge of one of ordinary skill in the pertinent art.” In re
`Paulsen, 30 F.3d 1475, 1480 (Fed. Cir. 1994). Also, “it is proper to take
`into account not only specific teachings of the reference but also the
`inferences which one skilled in the art would reasonably be expected to draw
`therefrom.” In re Preda, 401 F.2d 825, 826 (CCPA 1968).
`A claim is unpatentable under 35 U.S.C. § 103(a) if the differences
`between the claimed subject matter and the prior art are such that the subject
`matter, as a whole, would have been obvious at the time of the invention to a
`person having ordinary skill in the art. KSR Int’l Co. v. Teleflex, Inc., 550
`U.S. 398, 406 (2007). The question of obviousness is resolved on the basis
`of underlying factual determinations including (1) the scope and content of
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`the prior art; (2) any differences between the claimed subject matter and the
`prior art; (3) the level of ordinary skill in the art; and (4) objective evidence
`of nonobviousness. Graham v. John Deere Co., 383 U.S. 1, 17–18 (1966).
`Consideration of the Graham factors “helps inform the ultimate obviousness
`determination.” Apple v. Samsung Elecs. Co., 839 F.3d 1034, 1048 (Fed.
`Cir. 2016) (en banc), cert. denied, 2017 WL 948834 (U.S. Nov. 6, 2017).
`“In an [inter partes review], the petitioner has the burden from the
`onset to show with particularity why the patent it challenges is
`unpatentable.” Harmonic Inc. v. Avid Tech., Inc., 815 F.3d 1356, 1363 (Fed.
`Cir. 2016) (citing 35 U.S.C. § 312(a)(3) (requiring inter partes review
`petitions to identify “with particularity . . . the evidence that supports the
`grounds for the challenge to each claim”)). This burden of persuasion never
`shifts to Patent Owner. See Dynamic Drinkware, LLC v. Nat’l Graphics,
`Inc., 800 F.3d 1375, 1378 (Fed. Cir. 2015) (discussing the burden of proof in
`inter partes review). Furthermore, Petitioner cannot satisfy its burden of
`proving obviousness by employing “mere conclusory statements.” In re
`Magnum Oil Tools Int’l, Ltd., 829 F.3d 1364, 1380 (Fed. Cir. 2016).
`Thus, to prevail in an inter partes review, Petitioner must explain how
`a reference discloses all of the elements of a claims, or how the proposed
`combinations of prior art would have rendered the challenged claims
`unpatentable. At this preliminary stage, we determine whether the
`information presented in the Petition shows there is a reasonable likelihood
`that Petitioner would prevail in establishing that one of the challenged
`claims was anticipated by the cited prior art or would have been obvious
`over the proposed combinations of prior art.
`
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`We analyze the challenges presented in the Petition in accordance
`with the above-stated principles.
`
`B. Level of Ordinary Skill
`In determining whether an invention would have been obvious at the
`time it was made, we consider the level of ordinary skill in the pertinent art
`at the time of the invention. Graham, 383 U.S. at 17. “The importance of
`resolving the level of ordinary skill in the art lies in the necessity of
`maintaining objectivity in the obviousness inquiry.” Ryko Mfg. Co. v.
`Nu-Star, Inc., 950 F.2d 714, 718 (Fed. Cir. 1991).
`Relying on Dr. Baker’s declaration testimony, Petitioner contends that
`based on the technologies disclosed in the ’554 Patent, one of ordinary skill
`in the art relevant to the challenged patent would have had “at least a
`bachelor’s degree in electrical engineering or a similar field, and at least two
`to three years of experience in integrated circuit design.” Pet. 5–6 (citing
`Ex. 1002 ¶ 20).
`We determine that no express finding is necessary, on this record, and
`that the level of ordinary skill in the art is reflected by the prior art of record.
`See Okajima v. Bourdeau, 261 F.3d 1350, 1355 (Fed. Cir. 2001); In re
`GPAC Inc., 57 F.3d 1573, 1579 (Fed. Cir. 1995); In re Oelrich, 579 F.2d 86,
`91 (CCPA 1978).
`
`C. Claim Construction
`Petitioner points out that the ’554 Patent will expire on
`“September 24, 2018, i.e., during the pendency of the instituted proceeding”
`and contends that the challenged claims should be construed under the
`standard set forth in Phillips v. AWH Corp., 415 F.3d 1303 (Fed. Cir. 2005)
`(en banc). Pet. 10. We agree. Under the Phillips standard, claim terms are
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`given their ordinary and customary meanings, as would be understood by a
`person of ordinary skill in the art, having taken into consideration the
`language of the claims, the specification, and the prosecution history of
`record.
`Petitioner does not propose an express construction for any claim
`terms. Pet. 11. Similarly, we determine that no claim terms require express
`construction to determine whether to institute an inter partes review.
`
`D. Anticipation by Ito
`Petitioner contends that claim 22 is unpatentable under 35 U.S.C.
`§ 103(a) as anticipated by Ito. Pet. 3, 12–18. Relying in part on the
`testimony of Dr. Baker and numerous citations to the reference, Petitioner
`explains how Ito purportedly would have conveyed the claim limitations. Id.
`at 12–18. We first review Ito’s disclosure, and then discuss Petitioner’s
`contentions with respect to claim 22.
`
`1. Disclosure of Ito
`Ito relates to a substrate voltage detecting circuit for detecting a
`substrate voltage in a semiconductor memory device, such as a DRAM, and
`activating a substrate voltage generation circuit. Ex. 1005, 1:6–12. An
`embodiment of that substrate voltage detecting circuit is illustrated in Figure
`9, reproduced below:
`
`12
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`
`Ito describes that its charge pumping circuit 11 generates a negative
`substrate voltage VBB that is supplied to the semiconductor substrate. Id. at
`1:15–22. The substrate voltage detecting circuit is connected to “charge
`pumping circuit 11 in order to retain the substrate voltage VBB at a
`prescribed level.” Id. at 1:15–22, Fig. 9. When VBB is detected as more
`negative than the negative threshold voltage of PMOS transistor 5, the
`enable signal (/EN) is generated high such that the charge pumping circuit is
`off. Id. at 1:38–45. When VBB is detected as higher than the threshold
`voltage VTHP, the /EN signal is generated low such that the charge pumping
`circuit is turned on to pull VBB more negative. Id. at 1:50–57. This
`behavior of the circuit is illustrated in Figure 2 of Ito, reproduced below,
`with Petitioner’s annotations:
`
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`Pet. 15 (citing Ex. 1005, Fig. 2). In this annotated version of Ito’s Figure 2,
`Petitioner shows VBB in blue, and ON and OFF time periods for charge
`pumping circuit 11 corresponding to dotted line VBB in green and red,
`respectively. Id.
`
`2. Petitioner’s Contentions Regarding Claim 22
`With respect to independent claim 22, Petitioner addresses the
`disclosure of Ito, as discussed above. Pet. 12–18. Petitioner also contends
`that certain elements of claim 22 are equivalent to portions of Ito. Id. We
`discuss each in turn below.
`Petitioner asserts that a person of ordinary skill in the art would have
`understood that VBB refers to a back bias voltage, where that voltage is
`supplied to the semiconductor substrate. Id. at 13 (citing Ex. 1002 ¶ 69).
`We are persuaded that this is correct based on the background disclosure in
`the ’554 Patent, discussed above. Petitioner also asserts that because VBB is
`maintained at a “prescribed level” below a negative VTHP, Ito discloses
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`maintaining VBB “at a substantially constant negative level,” as claimed.
`Id. at 16–17 (citing Ex. 1005, 1:15-21, 29; Ex. 1002 ¶ 76). We agree with
`Petitioner’s interpretation of Ito.
`Additionally, Petitioner asserts that, as shown in the annotated
`Figure 2 of Ito, the dotted line version of VBB, which corresponds to the
`prior art noted in Ito, becomes less negative (closer to 0V) than the threshold
`voltage VTHP, thus the detector circuit allows substrate voltage VBB to get
`arbitrarily close to the level indicated in Figure 2 as “GND (0V),” without
`allowing the voltage to become positive. Id. at 17–18 (citing Ex. 1005,
`Fig. 2; Ex. 1002 ¶ 77). We agree with Petitioner’s interpretation of Ito.
`
`3. Conclusion
`Accordingly, based on the disclosure of Ito, we are persuaded that
`Petitioner has demonstrated a reasonable likelihood of showing that the
`disclosure of Ito would have conveyed to one of ordinary skill in the art the
`limitations recited in independent claim 22. To prevail during the inter
`partes review, however, Petitioner must demonstrate unpatentability by a
`preponderance of the evidence. 35 U.S.C. § 316(e) (“In an inter partes
`review instituted under this chapter, the petitioner shall have the burden of
`proving by a proposition of unpatentability by a preponderance of the
`evidence.”).
`
`E. Obviousness over Ito and Kim
`Petitioner contends that claims 28 and 29 are unpatentable under
`35 U.S.C. § 103(a) as obvious over Ito and Kim. Pet. 3, 18–23. Petitioner,
`relying on citations to the references and declaration testimony of Dr. Baker,
`sets forth how the references purportedly would have conveyed the claim
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`limitations and provides purported reasoning for combining the teachings of
`the references. Id. at 18–23.
`Claims 28 and 29 further recite that the bias voltage V1 biases a
`P-type region, forming a junction with an N-type region, and making the
`junction reversed biased, and that the circuit is a DRAM device,
`respectively, with claim 29 dependent on claim 28. Ex. 1001, 9:31–36. As
`discussed above, Ito discloses its substrate voltage detecting circuit for use
`with a DRAM device. Petitioner acknowledges that Ito does not provide
`express details about biasing junctions, but asserts that Kim discloses biasing
`in the general context of a memory device. Pet. 18–19.
`Kim discloses a back bias voltage generator for generating a back bias
`voltage (VBB) having a constant level, where that voltage is applied to the
`substrate of a memory device. Ex. 1006, 1:6–12, 4:6–15. Kim illustrates
`that memory devices include transistors, with each transistor having a P-type
`substrate to which the back bias voltage VBB is applied, and being in
`contact with “N+ diffusion region having a drain for inputting the
`voltage Vpp.” Id. at Fig. 6, 4:12–13.
`Petitioner alleges that it would have been obvious for one of ordinary
`skill in the art to have used Ito’s substrate voltage VBB to reverse bias the
`junction of Kim. Pet. 20–21. Petitioner asserts that one of ordinary skill in
`the art would have been motivated to make this combination because both
`references are directed to generating back bias voltages, disclose using such
`a back bias voltage to bias the substrate for a memory device, and that the
`person of ordinary skill would have known to include transistors, as
`illustrated in Kim, in DRAM devices, as described in Ito. Id. Petitioner
`makes additional arguments, applying the rationales from KSR. Id. at 22.
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`We are sufficiently persuaded that the combination of Ito and Kim
`reasonably would have suggested the limitations of claims 28 and 29.
`For the foregoing reasons, the information presented shows a
`reasonable likelihood that Petitioner would prevail in demonstrating that
`claims 28 and 29 are unpatentable for obviousness over Ito and Kim, as set
`forth in the Petition.
`
`F. Obviousness over Park and Baker
`Petitioner contends that claims 1–3, 14–16, 30, 31, and 36 are
`unpatentable under 35 U.S.C. § 103(a) as obvious over Park and Baker.
`Pet. 3, 23–73. Petitioner, relying on citations to the references and
`declaration testimony of Dr. Baker, sets forth how the references purportedly
`would have conveyed the claim limitations and provides purported reasoning
`for combining the teachings of the references. Id. at 23–73. We begin with
`a discussion of the cited references and then discuss Petitioner’s contentions
`regarding the independent and dependent claims.
`
`1. Disclosure of Park
`Park is directed to a back bias voltage level detector. Ex. 1007,
`Abstract. The back bias voltage level detector generates oscillator enable
`signal OSCEN, such that when OSCEN becomes a high, back bias voltage
`oscillator 2, as shown in Figure 1, outputs pulse OSC, and OSC is inputted
`to back bias voltage pump 3, which in turn generates the back bias voltage
`VBB. Id. at 4:58–5:45, 5:26–28, 40–45, Fig. 1. A block diagram of a
`conventional back bias voltage generator and a circuit diagram of the back
`bias voltage level detector are illustrated in Figures 1 and 5, respectively,
`reproduced below:
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`Park discloses that signal OSCEN is generated from a current IP'
`supplied by VCC through transistor P. Id. at 4:58–5:45, Fig. 5. Park also
`discloses that when the absolute value of the back bias voltage VBB is
`increased, node 51 becomes low, which is in turn used by inverter IN1 to
`generate a high or low output. Id. at 5:33–39, Fig. 5. Park also discloses
`that “[s]ince the difference VCC-VREF is constant, it is possible to obtain
`constant current IP' irrespective of the external voltage VCC.” Id. at 5:11–13.
`Similarly, current IN is also substantially insensitive to variations in VCC
`because IN depends on VGS1, which is the difference between the gate voltage
`of NMOS pull-down transistor N and VBB. Id. at 5:18–20, Fig. 5. Park also
`discloses that the gate to source voltage VGS2 of the PMOS pull-up transistor
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`P is made substantially insensitive to variations in the external voltage VCC.
`Id. at 4:60, 4:66–5:4, Fig. 5.
`Park’s back bias voltage level detector includes reference voltage
`generator 60, PMOS pull-up transistor P, resistor divider R1/R2, and NMOS
`pull-down transistor N for biasing node 51 to a voltage. Id. at 4:66–5: 39,
`Fig. 5. Inverters IN1 and IN2 generate the oscillation enable signal OSCEN
`in response to the node voltage at node 51. Id. at 5:24–27, 5:39–41, Fig. 5.
`Vcc supplies power to the reference voltage generator 60 across from ground
`voltage Vss. Id. at 4:46–47, Fig. 6.
`The output of VBB versus VCC is illustrated in Figure 8, reproduced
`below:
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`Park discloses that output c of Figure 8 has more stable back bias
`voltage, VBB, level with respect to the variation of the external voltage VCC
`“compared to the conventional circuits.” Id. at 5:12–14, 6:32–35. Park also
`discloses that “even if the external voltage VCC is varied . . . the back bias
`voltage VBB is stable.” Id. at 6:39–42.
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`2. Disclosure of Baker
`Baker is a textbook directed to CMOS circuit design and layout.
`Ex. 1008. Baker discusses the functions of inverters and details regarding
`the trip point of an inverter, referred to as a “switching point.” Id. at 204–
`05. Figure 11.1 of Baker is reproduced below:
`
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`Id. at 201. Transistors M1 and M2 are a PMOS “pull up transistor” and an
`NMOS “pull down transistor,” respectively. Id. at 151, 201. As illustrated,
`the source of transistor M1 is connected to ground and its drain is connected
`to a node labeled “Output.” Id. at Fig. 11.1. Transistor M2 has its drain
`connected to the output node and the drain of transistor M1, in effect
`coupling the transistors. See Ex. 1002 ¶ 192.
`Baker also discloses the following equation (11.4) for the switching
`point of an inverter comprising an NMOS transistor and a PMOS transistor:
`
`
`where βn and βp are transconductance parameters of the NMOS and PMOS
`transistors, respectively, in the inverter, VTHN and VTHP are threshold voltages
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`of the NMOS and PMOS transistors, respectively, and VDD is the power
`supply voltage. Ex. 1008, 205.
`
`3. Petitioner’s Contentions Regarding Claims 1, 15, and 30
`With respect to independent claims 1, 15, and 30, Petitioner addresses
`the disclosures of Park and Baker, as discussed above. Pet. 23–52, 57–70.
`Petitioner also contends that certain aspects of claims 1, 15, and 30 are
`obvious over the cited references and proffers motivation to combine the
`references. Id. We discuss each independent claim in turn below.
`With respect to claim 1, Petitioner asserts that a person of ordinary
`skill in the art would have recognized that while the OSCEN signal in the
`circuit of Figure 5 of Park is quite insensitive to power supply variations, the
`switching or “trip” point of inverter IN1 is a factor that could contribute to
`some power supply sensitivity for OSCEN. Id. at 30 (citing Ex. 1002 ¶¶ 98–
`103). Petitioner acknowledges that Park does not disclose that the “trip”
`point of inverter IN1 is substantially insensitive to variations in VCC, but
`cites to Baker based on details provided regarding inverters, discussed
`above. Id. at 30–31. Based on Baker’s equation 11.4, Petitioner asserts that
`a person of ordinary skill in the art would have recognized that the trip point
`will be “substantially insensitive” to variations in VDD if βn is set much
`larger than βp by sizing the NMOS and PMOS transistors of the inverter
`suitably, which was a task allegedly within the capability and skill of an
`ordinary artisan at the time of the invention. Id. at 31–32 (Ex. 1002 ¶¶ 108–
`109). Petitioner asserts that in view of Baker, one of ordinary skill in the art
`would have been motivated to configure Park’s circuit to have its trip point
`be substantially insensitive to power supply voltage variations, in keeping
`with Park’s overall objective of “constantly maintaining a back bias voltage
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`with respect to the variation of an external voltage.” Id. at 32 (quoting
`Ex. 1007, 3:45–57; Ex. 1002 ¶ 110). Petitioner raises additional reasons to
`combine Park and Baker. Id. at 32–34. We are persuaded that Petitioner has
`demonstrated that it would have been obvious to optimize Park’s circuit
`based on the teachings of Baker.
`Petitioner also asserts that a person of ordinary skill in the art would
`have understood that the external voltage VCC in Park is provided across the
`VCC terminal and VSS terminal because the external voltage VCC can be
`measured across the VCC terminal and VSS terminal. Id. at 41 (citing
`Ex. 1002 ¶ 124). In addition, Petitioner alleges that in the context of “a
`resistor connected between the first node and the output terminal of the
`voltage generator circuit,” recited in claim 1, a person of ordinary skill in the
`art would have understood that the NMOS pull-down transistor N of Park
`acts as a resistor between node 51 and the back bias voltage VBB. Id. at 46
`(citing Ex. 1002 ¶ 131; Ex. 1001, 3:50–51). We are persuaded that the
`various inferences and creative steps noted by Petitioner with respect to Park
`and Baker would have been within the understanding of persons of ordinary
`skill in the art.
`Claim 1 also recites that “the first transistor is a filed effect transistor
`biased in the saturation mode.” Petitioner argues that a person of ordinary
`skill in the art would have understood that for a constant current IP' provided
`by PMOS pull-up transistor P, in Park, transistor P is biased in the saturation
`mode based on the disclosure of Baker. Id. at 48–49 (citing Ex. 1002
`¶¶ 137–138; Ex. 1008, 96). We are persuaded that Petitioner has
`demonstrated that this would have been within the understanding of person
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