Q
`
`Encapsulation
`
`Technologies for
`
`Electronic Applications
`
`
`
`Halch Ardebili
`
`Michael G.Pecht
`
`Materials. and Processes for lilcclnmic Amiliculinnh Scriux
`
`NICHIA EXHIBIT 2729
`NICHIA EXHIBIT 2729
`Vizio, Inc. v. Nichia Corp.
`Vizio, Inc. v. Nichia Corp.
`Case IPR2017-01608
`Case IPR2017—01608
`
`

`

`MATERIALS AND PROCESSES FOR
`ELECTRONIC APPLICATIONS
`
`Series Editor: James J. Licari
`AvanTeco, Whittier, California, USA
`
`Coating Materials for Electronic Applications—9780815514923—
`By James J. Licari
`Adhesives Technology for Electronic Applications—9780815515135—
`By James J. Licari and Dale W. Swanson
`Encapsulation Technologies for Electronic Applications—
`9780815515760—By Haleh Ardebili and Michael Pecht
`
`

`

`William Andrew is an imprint of Elsevier
`Linacre House, Jordan Hill, Oxford OX2 8DP, UK
`30 Corporate Drive, Suite 400, Burlington, MA 01803, USA
`
`First edition 2009
`
`Copyright © 2009 Elsevier Inc. All rights reserved
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`No part of this publication may be reproduced, stored in a retrieval system or transmitted
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`
`Notice
`No responsibility is assumed by the publisher for any injury and/or damage to persons
`or property as a matter of products liability, negligence or otherwise, or from any use or
`operation of any methods, products, instructions or ideas contained in the material herein.
`Because of rapid advances in the medical sciences, in particular, independent verifi cation
`of diagnoses and drug dosages should be made
`
`British Library Cataloguing in Publication Data
`A catalogue record for this book is available from the British Library
`
`Library of Congress Cataloging-in-Publication Data
`A catalog record for this book is available from the Library of Congress
`
`ISBN: 978-0-8155-1576-0
`
`For information on all William Andrew publications
`visit our website at elsevierdirect.com
`
`Printed and bound in United States of America
`
`09 10 11 12 11 10 9 8 7 6 5 4 3 2 1
`
`

`

`Dedicated to my parents and my family, especially to my son, Arvin,
`and my husband, Pradeep.
`
`Haleh Ardebili
`
`Dedicated to my parents, my family, my students, my friends and my
`colleagues.
`
`Michael G. Pecht
`
`

`

`Page intentionally left blank.
`
`

`

`Preface
`
`The use of electronics has become intimately intertwined with human
`lives. From laptops and mobile phones to medical instruments and aircraft
`control units, electronic devices are used in most products today and in
`increasingly varying environments. The dominant trend is toward smaller,
`lighter, and faster electronic devices. Electronic packaging and plastic
`encapsulation play a signifi cant role in this trend. With advances in elec-
`tronic packaging including three-dimensional packaging (or die-stacking),
`wafer-level packaging, environmentally friendly or “green” encapsulant
`materials, and extreme high- and low-temperature electronics, a book on
`encapsulation technologies used in electronic applications has become
`essential.
`This book describes the fundamentals of plastic encapsulation, discusses
`advances in encapsulation materials and technologies, and explores the
`intersection of emerging technologies such as nanotechnology and bio-
`technology with encapsulant materials. The main emphasis of this book is
`on the encapsulation of microelectronics; however, the encapsulation of
`connectors and transformers is also addressed.
`The book is organized into eight chapters. Chapter 1 presents an overview
`of electronic packaging and encapsulation. Various types of plastic-
`encapsulated microelectronics including 2D and 3D packages are
`discussed. Chapter 2 is devoted to plastic encapsulant materials, which
`are categorized according to encapsulation technology. A separate sec-
`tion is devoted to environmentally friendly or “green” encapsulant
`materials. Chapter 3 is focused on encapsulation process technologies
`including molding, glob-topping, potting, underfi lling, and printing
`encapsulation. In this chapter, the encapsulation of wafer-level and 3D
`packages is also discussed. Chapter 4 discusses the characterization
`of encapsulant properties including manufacturing, hygro-thermo-
`mechanical, electrical, and thermal properties. Chapter 5 describes
`encapsulation defects and failures, while Chapter 6 presents defect and
`failure analysis techniques including both non-destructive and destructive
`tests. Chapter 7 is focused on qualifi cation and quality assurance of
`encapsulated microelectronics. Both virtual and product qualifi cation
`processes are discussed and accelerated tests and industry practices are
`presented.
`
`xv
`
`

`

`xvi
`
`Preface
`
`The fi nal chapter, Chapter 8, explores trends in and challenges for
`electronics, packaging, and plastic encapsulation. Moore’s law and “More
`than Moore” are presented. Evolution from integrated circuits to system-
`in-package and system-on-package is discussed. Extreme high- and low-
`temperature electronics are described. Furthermore, plastic encapsulation
`associated with microelectromechanical systems, nano-electronics and
`nanotechnology, bioelectronics and biosensors, and organic light emitting
`diodes and photovoltaics is discussed.
`This book is most suitable for the professional engineer and material
`scientist interested in electronic packaging and plastic encapsulation.
`Entrepreneurs in the electronics industry can also benefi t from this book.
`Additionally, this book can be used as a textbook in an elective course for
`senior undergraduates or fi rst-year graduate students with a background in
`material science or electronics.
`
`Acknowledgments
`
`Many people have supported and contributed to this book. We would
`like to acknowledge the contributions of the following people: Luu T.
`Nguyen, Edward B. Hakim, Rakesh Agarwal, Ajay Arora, Vikram Chandra,
`Lloyd W. Condra, Abhijit Dasgupta, Gerard Durback, Rathindra N.
`Ghoshtagore, Qazi Ilyas, Lawrence W. Kessler, Pradeep Lall, Junhui Li,
`Anupam Malhotra, Steven R. Martell, Tsutomu Nishioka, Thomas E.
`Paquette, Ashok S. Prabhu, Dan Quearry, Janet E. Semmens, and Jack
`Stein. Also, we like to acknowledge the studies published in IEEE, ASME,
`and other journals that have become invaluable references for the discussions
`in this book.
`We like to especially thank Dr. James J. Licari for his insightful and
`constructive review comments and suggestions throughout the develop-
`ment and writing of this book. We also would like to thank William
`Andrew Publishing (acquired by Elsevier). In particular we acknowl-
`edge the positive and consistent support of Martin Scrivener and Milli-
`cent Treloar. Furthermore, we would like to thank Elsevier (U.S.A.) and
`Exeter Premedia Services (India) for providing a smooth and positive
`transition during the publication process. We would like to thank the
`University of Houston’s Department of Mechanical Engineering faculty,
`staff, and students, and in particular the department chair, Professor Mat-
`thew Franchek, for their support and encouragement. We would like to
`thank the members, faculty, staff, and students at CALCE, University of
`Maryland, College Park, for their contributions to research and education
`
`

`

`Preface
`
`xvii
`
`in the fi eld of electronic packaging, which has benefi ted this book.
`Finally, we like to thank our family and friends for their support during
`this time-intensive endeavor.
`
`Haleh Ardebili
`Department of Mechanical Engineering
`University of Houston
`Houston, TX, USA
`
`Michael G. Pecht
`CALCE (Center for Advanced Life Cycle Engineering)
`University of Maryland
`College Park, MD, USA
`
`March 2009
`
`

`

`Table of Contents
`
`Preface
`
`1 Introduction
`1.1 Historical Overview
`1.2 Electronic Packaging
`1.3 Encapsulated Microelectronic Packages
`1.3.1 2D Packages
`1.4 Hermetic Packages
`1.4.1 Metal Packages
`1.4.2 Ceramic Packages
`1.5 Encapsulants
`1.5.1 Plastic Molding Compounds
`1.5.2 Other Plastic Encapsulation Methods
`1.6 Plastic versus Hermetic Packages
`1.6.1 Size and Weight
`1.6.2 Performance
`1.6.3 Cost
`1.6.4 Hermeticity
`1.6.5 Reliability
`1.6.6 Availability
`1.7 Summary
`References
`
`2 Plastic Encapsulant Materials
`2.1 Chemistry Overview
`2.1.1 Epoxies
`2.1.2 Silicones
`2.1.3 Polyurethanes
`2.1.4 Phenolics
`2.2 Molding Compounds
`2.2.1 Resins
`2.2.2 Curing Agents or Hardeners
`2.2.3 Accelerators
`2.2.4 Fillers
`2.2.5 Coupling Agents
`2.2.6 Stress-Relief Additives
`2.2.7 Flame Retardants
`
`

`

`2.2.8 Mold-Release Agents
`2.2.9 Ion-Trapping Agents
`2.2.10 Coloring Agents
`2.2.11 Market Conditions and Manufacturers of Encapsulant
`Materials
`2.2.12 Material Properties of Commercially Available
`Molding Compounds
`2.2.13 Materials Development
`2.3 Glob-Top Encapsulants
`2.4 Potting and Casting Encapsulants
`2.4.1 Dow Corning Materials
`2.4.2 General Electric Materials
`2.5 Underfill Encapsulants
`2.6 Printing Encapsulants
`2.7 Environmentally Friendly or “Green” Encapsulants
`2.7.1 Toxic Flame Retardants
`2.7.2 Green Encapsulant Material Development
`2.8 Summary
`References
`
`3 Encapsulation Process Technology
`3.1 Molding Technology
`3.1.1 Transfer Molding
`3.1.2 Injection Molding
`3.1.3 Reaction-Injection Molding
`3.1.4 Compression Molding
`3.1.5 Comparison of Molding Processes
`3.2 Glob-Topping Technology
`3.3 Potting and Casting Technology
`3.3.1 One-Part Encapsulants
`3.3.2 Two-Part Encapsulants
`3.4 Underfilling Technology 154
`3.4.1 Conventional Flow Underfill
`3.4.2 No-flow Underfill
`3.5 Printing Encapsulation Technology
`3.6 Encapsulation of 2D Wafer-Level Packages
`3.7 Encapsulation of 3D Packages
`3.8 Cleaning and Surface Preparation
`3.8.1 Plasma Cleaning
`
`

`

`3.8.2 Deflashing
`3.9 Summary
`References
`
`4 Characterization of Encapsulant Properties
`4.1 Manufacturing Properties
`4.1.1 Spiral Flow Length
`4.1.2 Gelation Time
`4.1.3 Bleed and Flash
`4.1.4 Rheological Compatibility
`4.1.5 Polymerization Rate
`4.1.6 Curing Time and Temperature
`4.1.7 Hot Hardness
`4.1.8 Post-cure Time and Temperature
`4.2 Hygro-thermomechanical Properties
`4.2.1 Coefficient of Thermal Expansion and Glass Transition
`Temperature
`4.2.2 Thermal Conductivity
`4.2.3 Flexural Strength and Modulus
`4.2.4 Tensile Strength, Elastic and Shear Modulus, and
`%Elongation
`4.2.5 Adhesion Strength
`4.2.6 Moisture Content and Diffusion Coefficient
`4.2.7 Coefficient of Hygroscopic Expansion
`4.2.8 Gas Permeability
`4.2.9 Outgassing
`4.3 Electrical Properties
`4.4 Chemical Properties
`4.4.1 Ionic Impurity (Contamination Level)
`4.4.2 Ion Diffusion Coefficient
`4.4.3 Flammability and Oxygen Index
`4.5 Summary
`References
`
`5 Encapsulation Defects and Failures
`5.1 Overview of Package Defects and Failures
`5.1.1 Package Defects
`5.1.2 Package Failures
`5.1.3 Classification of Failure Mechanisms
`
`

`

`5.1.4 Contributing Factors
`5.2 Encapsulation Defects
`5.2.1 Wire Sweep
`5.2.2 Paddle Shift
`5.2.3 Warpage
`5.2.4 Die Cracking
`5.2.5 Delamination
`5.2.6 Voids
`5.2.7 Non-uniform Encapsulation
`5.2.8 Flash
`5.2.9 Foreign Particles
`5.2.10 Incomplete Cure
`5.3 Encapsulation Failures
`5.3.1 Delamination
`5.3.2 Vapor-Induced Cracking (Popcorning)
`5.3.3 Brittle Fracture
`5.3.4 Ductile Fracture
`5.3.5 Fatigue Fracture
`5.4 Failure Accelerators
`5.4.1 Moisture
`5.4.2 Temperature
`5.4.3 Exposure to Contaminants and Solvents
`5.4.4 Residual Stresses
`5.4.5 General Environmental Stress
`5.4.6 Manufacturing and Assembly Loads
`5.4.7 Combined Load–Stress Conditions
`5.5 Summary
`References
`
`6 Defect and Failure Analysis Techniques for Encapsulated
`Microelectronics
`6.1 General Defect and Failure Analysis Procedures
`6.1.1 Electrical Testing
`6.1.2 Non-destructive Evaluation
`6.1.3 Destructive Evaluation
`6.2 Optical Microscopy
`6.3 Scanning Acoustic Microscopy
`6.3.1 Imaging Modes
`6.3.2 C-Mode Scanning Acoustic Microscope
`
`

`

`6.3.3 Scanning Laser Acoustic Microscope
`6.3.4 Case Studies
`6.4 X-ray Microscopy
`6.4.1 X-ray Generation and Absorption
`6.4.2 X-ray Contact Microscope
`6.4.3 X-ray Projection Microscope
`6.4.4 High-Resolution Scanning X-ray Diffraction
`Microscope
`6.4.5 Case Study: Encapsulation in Plastic-Encapsulated
`Devices
`6.5 X-ray Fluorescence Spectroscopy
`6.6 Electron Microscopy
`6.6.1 Electron–Specimen Interaction
`6.6.2 Scanning Electron Microscopy
`6.6.3 Environmental Scanning Electron Microscopy (ESEM)
`6.6.4 Transmission Electron Microscopy
`6.7 Atomic Force Microscopy
`6.8 Infrared Microscopy
`6.9 Selection of Failure Analysis Techniques
`6.10 Summary
`References
`
`7 Qualification and Quality Assurance
`7.1 A Brief History of Qualification and Reliability Assessment
`7.2 Qualification Process Overview
`7.3 Virtual Qualification
`7.3.1 Life-Cycle Loads
`7.3.2 Product Characteristics
`7.3.3 Application Requirements
`7.3.4 Reliability Prediction using PoF Approach
`7.3.5 Failure Modes, Mechanisms, and Effects Analysis
`(FMMEA)
`7.4 Product Qualification
`7.4.1 Strength Limits and Highly Accelerated Life Test
`7.4.2 Qualification Requirements
`7.4.3 Qualification Test Planning
`7.4.4 Modeling and Validation
`7.4.5 Accelerated Testing
`7.4.6 Reliability Assessment
`
`

`

`7.5 Qualification Accelerated Tests
`7.5.1 Steady-State Temperature Test
`7.5.2 Thermal Cycling Test
`7.5.3 Tests That Include Humidity
`7.5.4 Solvent Resistance Test
`7.5.5 Salt Atmosphere Test
`7.5.6 Flammability and Oxygen Index Test
`7.5.7 Solderability
`7.5.8 Radiation Hardness
`7.6 Industry Practices
`7.7 Quality Assurance
`7.7.1 Screening Overview
`7.7.2 Stress Screening and Burn-In
`7.7.3 Screen Selection
`7.7.4 Root-Cause Analysis
`7.7.5 Economy of Screening
`7.7.6 Statistical Process Control
`7.8 Summary
`References
`
`8 Trends and Challenges
`8.1 Microelectronic Device Structure and Packaging
`8.2 Extreme High- and Low-Temperature Electronics
`8.2.1 High Temperatures
`8.2.2 Low Temperatures
`8.3 Emerging Technologies
`8.3.1 Microelectromechanical Systems
`8.3.2 Bioelectronics, Biosensors, and Bio-MEMS
`8.3.3 Nanotechnology and Nanoelectronics
`8.3.4 Organic Light-Emitting Diodes, Photovoltaics, and
`Optoelectronics
`8.4 Summary
`References
`
`Index
`
`

`

`Page intentionally left blank.
`
`

`

` 1
`
`Introduction
`
` Electronics are used in a wide range of applications including computing,
`communications, biomedical, automotive, military, and aerospace. They
`must operate in varying temperature and humidity environments ranging
`from indoor controlled conditions to outdoor climate changes. Exposure to
`moisture, ionic contaminants, heat, radiation, and mechanical stresses can
`be highly detrimental to electronic devices and may lead to device failures.
`Therefore, it is essential that the electronic devices be packaged for protec-
`tion from their intended environment, as well as to provide handling,
`assembly, and electrical and thermal considerations.
` Electronic packaging may involve either hermetic (ceramic or metallic)
`packaging or non-hermetic (plastic) encapsulation. Currently, more than
`99% of microelectronic devices are plastic encapsulated. Improvements in
`encapsulant materials and cost incentives have stretched the application
`boundaries for plastic electronic packages. Many electronic applications
`that traditionally used hermetic packages such as military are now using
`commercial off-the-shelf (COTS) plastic packages. Plastic encapsulation
`has the advantages of low cost, availability, and manufacturability.
` Much of the focus is aimed at the research and development of new and
`improved encapsulants. With recent trends in environmental awareness,
`new environmentally friendly or “green” encapsulant materials (i.e., with-
`out brominated additives) have emerged. Plastic packages are also being
`considered for use in extreme high and low temperature electronics. 3D
`packaging and wafer-level packaging require unique encapsulation tech-
`niques. Encapsulants also play a role in emerging technologies. Modifi ed
`existing or newly developed encapsulant materials are being developed
`for microelectromechanical systems (MEMS), bio-MEMS, bioelectronics,
`nanoelectronics, solar modules, and organic light-emitting diodes. Nano-
`composite encapsulants with improved material properties are also being
`explored.
` In this chapter, a historical overview of encapsulation is provided. Elec-
`tronic packaging including package levels, encapsulated microelectronic
`devices, hermetic packages, and encapsulation methods and materials are
`discussed. Microelectronic packages including both 2D and 3D packages
`are described. Finally, a comparison of hermetic versus plastic packages is
`presented.
`
`1
`
`

`

`2
`
`Encapsulation Technologies for Electronic Applications
`
` 1.1 Historical Overview
`
` Electronic devices have been packaged in a variety of ways. Among the
`fi rst package types was a preformed package made of Kovar (an alloy of
`nickel, cobalt, manganese, and iron). Kovar, a trade name of Westinghouse
`Electric and Manufacturing Company, and invented by Howard Scott in
`1936 [1], has the advantage of a coeffi cient of thermal expansion (CTE)
`similar to that of glass. It is a suitable choice for sealing to glass because
`of lower CTE mismatch stresses.
` One of the early transistor packages is shown in Fig. 1.1 [2]. In this
`package, the emitter, collector, and base connector leads were inserted
`
`Kovar Ring
`
`Collector
`Lead
`
`Die
`
`Base Lead
`
`Wire
`
`Kovar Disc
`Cover
`
`Wire
`
`Collector
`Lead
`
`Glass
`Bushing
`
`Wire
`
`Emitter Lead
`
`(a)
`
`Die
`
`Kovar Ring
`
`Base Lead
`
`Welding
`
`Wire (to Emitter Lead)
`
`Kovar Disc Cover
`
`(b)
`
` Figure 1.1 Kovar transistor package: (a) top view; (b) side view [2].
`
`

`

`1: Introduction
`
`3
`
`through a glass bushing positioned in a Kovar ring or cylindrical housing.
`The bushing was made of a suitable electrical insulating and moisture
`impervious (hermetic) glass material. The transistor device was then
`bonded to the base lead and interconnected to the emitter and collector
`leads using wires. The Kovar disc covers were later hermetically sealed by
`welding. Ceramic packages, similar in construction to the Kovar casing,
`appeared later as less expensive alternatives.
` The fi rst plastic-encapsulated packages appeared on the market in the
`early 1950s. By the early 1960s, plastic encapsulation emerged as an
`inexpensive, simple alternative to both ceramic and metal encasings, and
`during the 1970s, virtually all high-volume integrated circuits (ICs) were
`encapsulated in plastic. By 1993, plastic-encapsulated microelectronics
`accounted for over 97% of the worldwide microcircuit production.
` Most early microelectronic devices were compression molded where
`the molding compound is heated and compressed inside the mold. Potting
`soon emerged as a suitable alternative. Potting involved positioning the
`electrical circuit in a container and pouring the liquid encapsulant into the
`cavity. Figure 1.2 shows a typical transistor encapsulated using the “can
`and header” method [3]. The transistor chip was soldered to a carrier which
`was then attached to the header assembly. The header assembly consisted
`of three parallel conductive lead-posts sealed into a button-like header
`made of pre-molded plastic encapsulant material such as a phenolic. The
`header served as a support for maintaining the relative positioning of the
`
`Carrier
`
`Chip (Die)
`
`Lead-post
`
`Plastic
`Encapsulant
`
`Wire
`
`Plastic
`Header
`
` Figure 1.2 “Can and header” transistor package [3].
`
`

`

`4
`
`Encapsulation Technologies for Electronic Applications
`
`three posts. The microelectronic chip was electrically connected to the
`side lead posts via wire bonding. The assembly of lead-posts and carrier
`was then encapsulated with commercially available plastic encapsulant
`materials such as Dow Chemical Company’s epoxy encapsulants.
` Transfer molding gained worldwide acceptance as an economical
`method best suited for mass production. In transfer molding, the micro-
`electronic chips are loaded into a multi-cavity mold and constrained, and
`the encapsulant is transferred from a reservoir into the cavity under heat
`and pressure. The encapsulant, typically a thermosetting polymer, is cured
`in the cavity to form the fi nal electronic package. In transfer molding,
`unlike compression molding, no additional pressure is applied during heat-
`ing and curing of the encapsulant. Furthermore, the closed mold design in
`transfer molding allows for more intricate chips to be encapsulated with
`better tolerances compared to compression molding.
` Figure 1.3 shows one of the fi rst molds used for transfer molding of a
`transistor device [4]. The metal lead-posts were gripped and fi rmly held
`in proper position as the multi-part lower portion of the mold was clamped
`together. The leads were bent and fl attened on top, and the semiconductor
`device was placed on one fl attened lead and wire bonded to the other two
`leads. A thin mask was placed on top with a disc-shaped exposed area,
`and the chip and the leads were passivated with metallic oxide such as
`alumina. The mask was removed and the upper portion of the mold was
`
`Plastic
`Encapsulant
`
`Chip
`
`Wires
`
`Mold Upper Portion
`
`Primary
`Runner
`
`Lead-Post
`
`Mold
`Cavity
`
`Secondary
`Runner
`
`Mold Multi-Part
`Lower Portion
`
` Figure 1.3 Transfer molding of a semiconductor chip [4].
`
`

`

`1: Introduction
`
`5
`
`then pressed on the lower portion. Powdered plastic or preforms were
`introduced through the cylindrical runner and became molten due to the
`high temperature of the upper mold portion. A piston was then pressed
`into the runner transferring the molten plastic through the gate into the
`cavity above the semiconductor device assembly. The plastic cured and
`solidifi ed in the cavity. The mold opened to release the plastic molded
`parts. One of the disadvantages of this method was that the thin wire
`bonds were frequently damaged due to the high pressure and velocities of
`the encapsulant.
` A novel approach to the problem of wire damage during transfer molding
`was to use a bottom-side gated process, in which the molding compound
`entered the cavity from the side opposite to the bond wires and in a
`motion path parallel to the wires ( Fig. 1.4 ), thereby reducing the chances
`of breaking the delicate wires.
` Although epoxy novolac was the fi rst material used for plastic encapsu-
`lation, phenolics and silicones were the dominant plastics of the 1960s.
`At that time, plastic packages were plagued by numerous reliability prob-
`lems due largely to the poor quality of the encapsulation system. Moisture-
`induced failure mechanisms, such as corrosion, cracking, and interfacial
`delamination, were signifi cant. At that time, plastic packages encountered
`formidable challenges in gaining acceptance for use in government and
`military applications. While plastic packaging offered an economically
`viable alternative, the military continued using metal and ceramic packages
`due to higher reliability, ruggedness, and traceability.
` Over the years, with improvements in encapsulant materials, die passi-
`vation, metallization technology, and assembly automation, plastics have
`
`Chip
`
`Wires
`
`Gate
`
`Mold
`
`Mold cavity
`
`Secondary runner
`
`Runner
`
` Figure 1.4 Transfer molding with bottom-side gating [5].
`
`

`

`6
`
`Encapsulation Technologies for Electronic Applications
`
`dominated the electronic packaging industry. The reliability of plastic
`packages was no longer considered a stumbling block to their widespread
`application. In 1994, after the so-called “Perry Memo” (named after then
`Defense Secretary William Perry), the US military offi cially started the
`wider use of plastic-encapsulated electronic packages. The main driving
`force for this transition was cost. A hermetically packaged ceramic IC
`can cost up to ten times more than a plastic-packaged IC—if a suitable
`one is even available on the market at all. Not surprisingly, COTS techno-
`logy plastic packages are now widely used in aerospace and military
`applications [6,7].
` In the 2000s, with major advantages in cost, size, weight, performance,
`and availability, plastic packages attracted more than 99% of the market
`share of worldwide microcircuit sales. Ceramic packages are used only in
`harsh military applications and specialized low-volume, high-performance
`systems. Much of the electronics packaging research performed today
`involves developing new smaller, lighter, cheaper, and more reliable plastic
`packages. Plastic-encapsulated microcircuits will continue to account for
`the vast share of the ICs market in coming years, but hermetic packages,
`with their special characteristics, will continue to have a unique market in
`the electronics industry.
` Over the decades numerous formulations of epoxies have been devel-
`oped with lower curing shrinkages and contamination levels. Since the
`early 1970s, epoxies have taken over as the main encapsulating material.
`Although silicones are still sometimes used, in the 2000s the typical encap-
`sulant is an epoxy resin matrix with a complex mixture of cross linkers,
`accelerators, fl ame retardants, fi llers, coupling agents, mold-release agents,
`and fl exibilizers.
` Plastic packages can be pre-molded or post-molded. In the pre-molding
`process, a package base is prepared from a pre-molded plastic (or some-
`times a metal substrate). The chip is then placed on the base and con-
`nected to an I/O fan out pattern with wire. A pre-molded plastic lid or
`housing is attached on top, using an epoxy adhesive to protect the die and
`wire bonds, and forms a cavity inside the package. Figure 1.5 shows a
`pre-molded package [8,9]. Pre-molded packages are most often used for
`high-pin-count devices or pin-grid arrays that are not amenable to fl at
`lead-frames and simple fan out patterns.
` In the post-molded package, the die is fi rst attached to a lead-frame
`and connected to an I/O fan out pattern with wire, which is then loaded
`into a multi-cavity molding tool and encapsulated in a thermoset mold-
`ing compound via the transfer molding process. Post-molded packages
`are less expensive than pre-molded ones because there are fewer parts
`
`

`

`1: Introduction
`
`7
`
`Chip
`
`Plastic lid
`
`Wire
`
`Lead
`
`Cavity
`
`Adhesive
`
`Adhesive
`
`Base
`
` Figure 1.5 A pre-molded plastic package [9].
`
`and assembly steps. About 90% of plastic packages are made using post-
`molding techniques.
`
` 1.2 Electronic Packaging
`
` The main objectives of electronic packaging are (a) the protection of the
`IC chip (or die) and (b) the interconnection of IC chips to other electronic
`components (i.e., IC chips, printed circuit boards (PCBs), transformers,
`and connectors) for transfer of electrical signals. An electronic package
`may be designed to
`
`
`
`
`
`
`
`
`
`
`
`
`
` reduce or remove heat that is either generated internally
`during device operation or due to the external environment;
` provide resistance to humidity and moisture;
` provide resistance to ionic contaminants;
` protect from radiation;
` reduce thermo-mechanical stresses; and
` provide mechanical support.
`
` Electronic packaging generally begins at the chip or wafer level.
` Figure 1.6 shows a fl owchart of a conventional plastic packaging of an IC
`chip. The passivated silicon die is cut out from the wafer using a diamond
`blade. The passivation layer is deposited by plasma-enhanced chemical
`vapor deposition, or by a spin-on technique for polyimides. The silicon
`chip is then attached to the lead-frame die-paddle using an electrically
`conductive or electrically insulative polymeric adhesive such as epoxy or
`polyimide. In some cases, metal and glass die-attachments are used for
`microcircuits or power devices that dissipate large amounts of heat or for
`high-reliability space applications where low outgassing is a requirement
`[10]. Metal or glass attachment materials, however, are more brittle, more
`
`

`

`8
`
`Encapsulation Technologies for Electronic Applications
`
`Dice
`
`Die attach
`
`Wafer
`
`Diamond blade
`
`Lead-frame
`Chip
`
`Wafer
`
`Wire bond
`
`Wire Chip
`
`Encapsulate (Mold)
`
`Encapsulant
`
`Plate, Trim, Form
`
`Mark
`
`Pack
`
` Figure 1.6 Plastic package assembly fl owchart [11].
`
`costly, and require higher processing temperatures than polymer
`adhesives.
` The lead-frame, which consists of a die-adhesive-paddle and leads,
`is fabricated by either stamping or etching process. Stamping is more
`cost effective than etching, but it is limited to two hundred pins or fewer.
`The lead-frame is usually plated with silver, a tin-lead solder, or nickel-
`palladium before encapsulation to improve the adhesion of the bond
`wires.
` After the attachment to the die-paddle, the chip is wire bonded to
`the leads for electrical connection. The bond wires are usually thermo-
`sonically bonded (ball-bonded) to the aluminum bonding pads on the
`chips and ultrasonically bonded (wedge-bonded) to the fi ngers of the
`lead-frame.
` The interconnected chip assembly is then encapsulated. Encapsulation
`techniques include molding, potting, printing, glob-top, and underfi ll.
`Before encapsulation, the lead-frame assembly is plasma cleaned to remove
`the stamping oils from the stamped lead-frame and thus improve adhesion
`during encapsulation. After encapsulation the leads are defl ashed. During
`the encapsulation process, molding compound can fl ow through the mold
`parting line and onto the leads of the device. This extra molding compound
`
`

`

`1: Introduction
`
`9
`
`is known as “fl ash.” If this fl ash is left on the leads, it will cause problems
`in the downstream operations of lead trimming, forming, and solder dipping
`and/or plating.
` Finally, the leads are trimmed and the excess lead-frame metal is cut.
`The leads are formed into various shapes, including dual in-line, gull-wing,
`or J-leads. The exposed surfaces of the lead-frame are plated with tin or a
`tin-lead alloy to prevent lead corrosion and enhance solderability during
`assembly onto the printed wiring board.
` Other methods besides wire bonding for electrical connection to the
`PCB include tape-automated bonding (TAB) and fl ip-chip bonding. TAB
`is an automated surface-mount method that can provide interconnection
`for chips with large numbers of input-output terminals ( ≤ 500). Figure 1.7
`shows the fl ow of a TAB process.
` In the TAB process, a continuous polymer tape is fabricated with fi ne-
`pitched metal lead-frames spaced along its length. A window is made in
`the center of each lead-frame where the chip is to be placed. The leads of
`the lead-frame are then bonded to the chips, on which bonding platforms,
`or “bumps,” have been deposited by electrolytic or electroless gold plating
`and liftoff photolithography. The connections to the lead-frame fi ngers are
`typically made by thermocompression bonding. The chip face may then be
`
`Pressure and
`temperature
`
`TAB tape
`
`Gang bonder
`thermode
`
`Molding
`compound
`dispenser
`
`Oven
`
`Inner lead bonding
`
`Encapsulate
`
`Cure
`
`Test
`
`Pressure and
`temperature
`
`Gang
`bonder
`thermode
`
`Outer lead bond: lead excise, form and gang bond
`
` Figure 1.7 Outline of a complete tape-automated bonding (TAB) process using
`liquid plastic encapsulants.
`
`

`

`10
`
`Encapsulation Technologies for Electronic Applications
`
`coated with liquid plastic encapsulant and cured. The reel of radial-spread,
`coated chips is then sent to the substrate (or circuit card) assembly line,
`where individual chips are excised from the tape, the leads are formed, and
`the package is bonded to the substrate.
` Electronic packaging can be classifi ed into several packaging levels as
`shown in Fig. 1.8 . The fi rst level packaging consists of the interconnection
`and encapsulation of the IC chip. As the chip itself contains integrated
`microcircuits including transistors, resistors, and capacitors, it is commonly
`considered as a zero level package.
` The second level packaging consists of the connection of the micro-
`electronic package to the PCB. Additional protection of encapsulated
`microelectronics on PCBs can be achieved by the application of a polymer
`coating [12]. PCBs may be further interconnected to a mother board,
`known as third level packaging. The fourth and fi nal packaging level is the
`packaging of the mother board (or PCBs) in an electronic system such as
`a laptop computer or a cellular phone. There are several exceptions to the
`mentioned