`
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`TOSHIBA CORPORATION, TOSHIBA MEMORY CORPORATION, AND
`TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.,
`Petitioners,
`
`v.
`
`MACRONIX INTERNATIONAL CO., LTD.,
`Patent Owner.
`____________
`
`Case IPR2017-01632
`Patent 8,035,417 B1
`____________
`
`Record of Oral Hearing
`Held: September 14, 2018
`___________
`
`
`
`
`Before KEN B. BARRETT, JENNIFER S. BISK, and JASON M. REPKO,
`Administrative Patent Judges.
`
`
`
`
`
`
`
`
`
`
`Case IPR2017-01632
`Patent 8,035,417 B1
`
`
`
`APPEARANCES:
`
`ON BEHALF OF THE PETITIONER:
`
`
`KEVIN C. HAMILTON, ESQUIRE
`GERALD T. SEKIMURA, ESQUIRE
`DLA Piper LLP (US)
`401 B Street, Suite 1700
`San Diego, California 92101
`
`
`
`ON BEHALF OF THE PATENT OWNER:
`
`
`CHRISTIAN A. CHU, ESQUIRE
`CHRIS DRYER, ESQUIRE
`Fish & Richardson, P.C.
`1000 Maine Avenue SW
`Washington, D.C. 20024
`
`
`
`
`The above-entitled matter came on for hearing on Friday, September
`
`14, 2018, commencing at 1:00 p.m., at the U.S. Patent and Trademark
`Office, Madison Building East, 600 Dulany Street, Alexandria, Virginia,
`22314.
`
`
`
`
`
`
`
`
`
`
`
`
`
`2
`
`
`
`Case IPR2017-01632
`Patent 8,035,417 B1
`
`
`P R O C E E D I N G S
`- - - - -
` JUDGE BARRETT: Good afternoon, everyone. We are on
`the record for the final hearing in IPR 2017-01632. Toshiba
`versus Macronix International.
` I'm Judge Barrett, and with me at the bench is
`Judges Bisk and Repko.
` Let's get the parties' appearances. Who do we have
` from petitioner?
` MR. HAMILTON: Your Honor, Kevin Hamilton from DLA
`Piper on behalf of petitioner. And with me is Joe Sekimura,
`also from DLA Piper.
` JUDGE BARRETT: Welcome.
` And for patent owner?
` MR. CHU: Christian Chu with Fish & Richardson on
`behalf of Macronix International. With me is my colleague,
`Christopher Dreyer.
` JUDGE BARRETT: We issued a hearing order in this
`case that set forth the procedure, but I'll remind everybody.
` Each party will have 60 minutes total time to
` present arguments. For clarity of the transcript, please
` identify the slides you are referring to. That will make
` for a much cleaner transcript.
` Petitioner will go first, and you may reserve time
` for rebuttal, patent owner will then have an opportunity to
` present its response, and then petitioner may use any
`
`1
`2
`3
`4
`5
`6
`7
`8
`9
`10
`11
`12
`13
`14
`15
`16
`17
`18
`19
`20
`21
`22
`23
`24
`25
`26
`
`3
`
`
`
`Case IPR2017-01632
`Patent 8,035,417 B1
`
` rebuttal time remaining.
` I'll be watching the clock, and I will give counsel
` a warning when you're approaching the end.
` Any questions?
` MR. CHU: No, Your Honor.
` MR. HAMILTON: No, Your Honor.
` JUDGE BARRETT: Okay. Well, with that, you may
`begin.
` MR. HAMILTON: Thank you, Your Honor. I have three
`copies of -- hard copies of petitioner's demonstratives,
`but -- would you like those?
` JUDGE BARRETT: We're okay. We have them pulled up
`on our screen. The court reporter may want a copy before the
`end of the day, though.
` MR. HAMILTON: Excellent.
` Thank you, Your Honor. Good afternoon, Your Honors.
` Good afternoon.
` Kevin Hamilton and Gerald Sekimura from DLA Piper on
` behalf of the petitioner, Toshiba Corporation.
` Your Honor, I would like to reserve 25 minutes for
` rebuttal, if that's possible.
` Your Honor, I'm pulling up Slide 2 of Toshiba's
` demonstratives.
` What is shown on Slide 2 is, on the left we have an
` excerpt from the Background section of the '417 patent, and
` on the right-hand side, we have an excerpt from the
`
`1
`2
`3
`4
`5
`6
`7
`8
`9
`10
`11
`12
`13
`14
`15
`16
`17
`18
`19
`20
`21
`22
`23
`24
`25
`26
`
`4
`
`
`
`Case IPR2017-01632
`Patent 8,035,417 B1
`
` beginning of patent owner's response.
` And what this slide shows is the -- is Macronix's
` position, and frankly, the patent's position regarding what
` the purported invention was.
` And the purported invention was, quite simply, it
` was an output buffer circuit with variable drive strength.
` That's what was the title, and that's what the invention was
` supposed to be.
` These -- both of these excerpts identified problems
` with the prior art, and the problems with the prior art
` included the fact that the prior art, the output buffer
` circuits had a fixed drive strength. You couldn't change
` the drive strength, you could only turn it on or off.
` And what that meant was, if you had -- if a designer
` needed an output buffer circuit, he either had to design an
` output buffer circuit using a one -- one-size-fits-all
` approach, which was not always efficient, or he had to go
` and customize each and every output buffer circuit for its
` particular -- for its particular use. And that was very
` time-consuming, and the specifications had an enormously
` complicated design.
` And so that's what Macronix initially says its
` patent was, an output buffer circuit having variable drive
` strength.
` But, of course, the scope of the patent is
` determined by its claims, so let's look at Claim 1.
`
`1
`2
`3
`4
`5
`6
`7
`8
`9
`10
`11
`12
`13
`14
`15
`16
`17
`18
`19
`20
`21
`22
`23
`24
`25
`26
`
`5
`
`
`
`Case IPR2017-01632
`Patent 8,035,417 B1
`
` I've pulled up Slide 3 of petitioner's
` demonstratives on the screen. And here, on the left, we're
` looking at Figure 6 of the '417 patent, and on the right we
` have Claim 1 of the '417 patent.
` There are three independent claims that are
` challenged in this petition; 1, 11, and 18.
` Claim 1 is the narrowest of the claims, and it
` recites the most limitation. And, in fact, every limitation
` recited in Claims 11 and 18 are recited in Claim 1. And so
` if you -- if a prior art reference anticipates Claim 1, then
` it anticipates Claims 11 and 18, as well, and I don't
` believe that there's any dispute between the parties on that
` issue.
` Moving to Toshiba's demonstrative number 4, Slide 4,
` we're looking at the same thing in the previous slide;
` however, this time, on the right-hand side, we have two
` portions of Claim 1 that are highlighted. There's a portion
` of the first "wherein" clause that is highlighted, and that
` represents one of the two disputed limitations between the
` parties, and a portion of the second limitation -- excuse
` me -- a portion of the second "wherein" clause is also
` highlighted, and that shows the second disputed limitation
` between the parties.
` So these are the only things that the parties
` dispute concerning whether the prior art references are
` anticipated or rendered obvious by the -- whether the prior
`
`1
`2
`3
`4
`5
`6
`7
`8
`9
`10
`11
`12
`13
`14
`15
`16
`17
`18
`19
`20
`21
`22
`23
`24
`25
`26
`
`6
`
`
`
`Case IPR2017-01632
`Patent 8,035,417 B1
`
` art references anticipate or render obvious the independent
` claims of the '417 patent.
` Moving to Slide 5. On the right-hand side, again,
` we have Claim 1 of the '417 patent and the first portion of
` the first "wherein" clause, the first disputed limitation is
` highlighted in yellow. On the left-hand side we have Yen
` Figure 3 and Yen Figure 4, and those are both annotated in
` red, as they were in the petition.
` So the limitation requires -- and I'm just going to
` read a portion of this yellow claim -- "The data output
` signal is combined to cross the plurality of output buffer
` circuits to provide a combined data output signal having a
` combined output drive strength."
` Now, Macronix concedes that the red annotations in
` Figures 3 and 4 disclose pluralities of output buffer
` circuits; however, Macronix says that these -- these figures
` are different. They're different because each of the
` figures contains what Macronix calls a default output
` buffer. The default output buffer in Figure 3 is shown at
` the top. It's -- it's a buffer and it's labeled 42. At the
` top. It's not highlighted. It's a triangle.
` And in Yen Figure 4 on the bottom, the output buffer
` circuit -- the default output buffer is the left -- left
` most four stack of transistors that is not highlighted.
` So Macronix coined this term "default output buffer
` circuit". Default output buffer is not something that's
`
`1
`2
`3
`4
`5
`6
`7
`8
`9
`10
`11
`12
`13
`14
`15
`16
`17
`18
`19
`20
`21
`22
`23
`24
`25
`26
`
`7
`
`
`
`Case IPR2017-01632
`Patent 8,035,417 B1
`
` recited in the '417 patent, it's not recited in the Yen
` reference, it's not in the claims, and there's actually
` nothing in the language of the claims that precludes the use
` of a default output buffer circuit.
` The claims recite, "Wherein the data output signal
` is combined across the plurality of output buffer circuits,"
` as shown in red, "to provide a combined output -- a combined
` data output signal having the combined output drive
` strength."
` JUDGE REPKO: So how is that combined? The top one
`isn't 42 combining with it as well, right?
` So it's like -- it seems like when it says, "A data
`output signal having a combined output drive strength," does
`that not include 42, as well?
` MR. HAMILTON: So if -- if you look at the top
`figure, you have, in red, output buffer circuit 44, 48, and
`50. Those are the red ones.
` The outputs of those -- the output signals come out
`of those on the right, and they're combined. They're
`combined in a signal that goes to the output, to the --
` Above and to the right of output buffer circuit 44,
`there's a signal there that contains the combination of those
`three output buffer circuits.
` JUDGE REPKO: So it's the signal that's coming up
`perpendicular to the signal coming from 42? Is that what
`you're saying?
`
`1
`2
`3
`4
`5
`6
`7
`8
`9
`10
`11
`12
`13
`14
`15
`16
`17
`18
`19
`20
`21
`22
`23
`24
`25
`26
`
`8
`
`
`
`Case IPR2017-01632
`Patent 8,035,417 B1
`
` MR. HAMILTON: That's correct. That's one way to
`read it. Okay?
` And in -- in Figure 4, we have the same thing. You
`have a portion of the -- of the horizontal line from 46 that
`couples the two output buffer circuits that are highlighted
`in red. That contains the combined output drive strength of
`those two plurality of output buffer circuits.
` That's not the only way to read this limitation on
`Yen.
` JUDGE BISK: Do we have to -- I'm sorry. Let me get
`the microphone. Am I okay?
` JUDGE BARRETT: Yes.
` JUDGE BISK: Do we have to do a claim construction
`for combined -- combined data output signal --
` MR. HAMILTON: No.
` JUDGE BISK: -- to say whether it includes only
`the -- for instance, like buffer enable inputs, or can it
`also include another output?
` MR. HAMILTON: So I don't think a claim construction
`is necessary. I think you read the plain meaning of the --
`of the language that's included in the claim, there's nothing
`that restricts it to "only". Now, let me explain.
` The highlighted limitation towards the second line,
` it provides, "A combined data output signal having the
` combined output drive strength."
` JUDGE BISK: Mm-hmm.
`
`1
`2
`3
`4
`5
`6
`7
`8
`9
`10
`11
`12
`13
`14
`15
`16
`17
`18
`19
`20
`21
`22
`23
`24
`25
`26
`
`9
`
`
`
`Case IPR2017-01632
`Patent 8,035,417 B1
`
` MR. HAMILTON: Right? "Having" is --
` So output buffer 46 -- buffer output 46 that is
`shown in Figure 3 and Figure 4 of Yen, that output signal
`itself has the output drive strength of the plurality of
`output buffer circuits in each, but it also has something
`else. But "have" is an open term. Let me give you an
`example.
` So there are 12 months in a year. How many of those
` months are having or have 28 days? They all do. They'll
` have 28 days. Some -- some of the months have more, some of
` them have 30, some of them have 31, but they all have 28
` days.
` But if I were to ask a different question. You have
` 12 months in the year. How many of those months have only
` 28 days? Then that's a limitation that is not in the claim.
` The claim -- the plain language of the claim is
` broader. It just says "has it". Open-ended terminology is
` nothing new in patent law.
` JUDGE REPKO: So you're saying the data output
`signal is the signal from all of the (inaudible) -- including
`42, including 44, including 48, but your year, you're saying,
`is that analogous to the output signal?
` MR. HAMILTON: In the second way that I've shown you
`to look at this, then yes. Buffer output 46 in each of
`the -- of these figures has the combined output drive
`strength of the plurality of output buffer circuits.
`
`1
`2
`3
`4
`5
`6
`7
`8
`9
`10
`11
`12
`13
`14
`15
`16
`17
`18
`19
`20
`21
`22
`23
`24
`25
`26
`
`10
`
`
`
`Case IPR2017-01632
`Patent 8,035,417 B1
`
` JUDGE BISK: And that's --
` MR. HAMILTON: But that -- and that's what the claim
`requires.
` JUDGE BISK: That's what was in your petition,
`right?
` MR. HAMILTON: Yes.
` JUDGE BISK: Okay. But using the intermediate
`output, that wasn't in your petition.
` MR. HAMILTON: So the petition says that the
`combined -- that the combined output drive strength of the
`plurality of output buffer circuits, for instance, in
`Figure 3 is -- those are combined to -- to give you that
`combined output drive strength.
` And so if you look at this here, I mean, the --
`fundamentally, I didn't necessarily say it in the same words,
`but the same argument was made.
` JUDGE BISK: Okay.
` MR. HAMILTON: So the claim language itself, it does
`not include that word "only", it's broad, that's the language
`that they chose.
` But if you're not persuaded by my argument and you
` like Macronix's default buffer argument, then it's worth
` taking a look at the Jain reference, and let's do that now.
` Moving to Toshiba's demonstrative Slide 6.
` The right-hand side, again, we have Claim 1 of the
` '417 patent with the first disputed limitation in the first
`
`1
`2
`3
`4
`5
`6
`7
`8
`9
`10
`11
`12
`13
`14
`15
`16
`17
`18
`19
`20
`21
`22
`23
`24
`25
`26
`
`11
`
`
`
`Case IPR2017-01632
`Patent 8,035,417 B1
`
` "wherein" clause is highlighted, and 4 the left-hand side we
` have Figure 6 of Jain.
` So clearly, Figure 6 of Jain discloses, "Plurality
` of output buffer circuits coupled in parallel to provide a
` combined output drive strength, and it does that without a
` default output buffer circuit." I don't think anybody's
` going to argue that that's not true.
` And looking at the limitation in question, "wherein
` the data output signal," which is 22 at the output 4 the
` right of Figure 6, "is combined across a plurality of output
` buffer circuits to provide a combined data output signal
` having the combined output drive strength of that plurality
` of output buffer circuits," and nothing else, no default
` buffer circuit.
` So it's right there. And that is the only thing
` that Toshiba is relying on -- is relying on Jain for is to
` show that an output buffer circuit with a variable drive
` strength and no default output buffer was known in the prior
` art prior to the '417 patent, which directly contradicts
` Macronix's position.
` And also, Toshiba relies upon Jain for the
` proposition that a person of ordinary skill in the art that
` Figure 3 of Yen and Figure 6 of Jain in front of them would
` understand that Yen could be implemented without using a
` default output buffer circuit.
` Now, the patent owner says, "A person of ordinary skill
`
`1
`2
`3
`4
`5
`6
`7
`8
`9
`10
`11
`12
`13
`14
`15
`16
`17
`18
`19
`20
`21
`22
`23
`24
`25
`26
`
`12
`
`
`
`Case IPR2017-01632
`Patent 8,035,417 B1
`
` in the art would not have been motivated to combine those
` two references." Let's take a closer look at that.
` I pulled Slide 7 of Toshiba's demonstratives up. On
` the left-hand side we're looking at Figure 3 of Yen
` annotated to show plurality of output buffer circuits in
` red, and Jain's Figure 6 is on the right, again, annotated
` to show plurality of output buffer circuits in red.
` Now, Macronix says that, "A person having
` ordinary" -- "A person of ordinary skill in the art looking
` at these two references would not combine them." I think
` that's a tough sell. They're almost identical.
` Other than the labeling of the inputs and outputs,
` the only difference between the two is the fact that Yen
` Figure 3 has an additional output buffer circuit 42 at the
` top that does not have a custom enable signal. It has a
` shared enable signal, but no custom enable signal.
` Now, the person in possession of Yen who looked at
` Jain might understand -- may look at Jain and say, hey,
` these guys did it a little bit different. They -- they
` added this -- this known thing, this custom buffer enable
` signal to the -- to the top most output buffer circuit, and
` that -- that gives me a little bit extra flexibility. Maybe
` I can turn that one off while I turn some of the other ones
` below on.
` That's not -- that's not a big deal. If you wanted
` that extra flexibility, then you could do that.
`
`1
`2
`3
`4
`5
`6
`7
`8
`9
`10
`11
`12
`13
`14
`15
`16
`17
`18
`19
`20
`21
`22
`23
`24
`25
`26
`
`13
`
`
`
`Case IPR2017-01632
`Patent 8,035,417 B1
`
` JUDGE BISK: I'm sorry. I have a question which
`might be a little out there. But why isn't -- why wouldn't
`Jain be anticipatory? Why -- why are we combining Yen with
`Jain at all if it's the same --
` MR. HAMILTON: So it is. So the only thing that
`Jain does not expressly disclose it clearly is a -- is the
`final "wherein" clause, which is the buffer enable signal's
`complement controlling pairs of transistors having opposite
`connectivity types. That is not expressly disclosed in Jain.
`That's the only thing.
` JUDGE REPKO: But where is Figure 4 of Yen? How
`does this factor into your analysis?
` MR. HAMILTON: So the way that it factors in is
`Figure 3 and Figure 4 are different levels of abstraction
`showing the same invention. This is a block level diagram
`that does not show transitional level implementation, it just
`shows logic symbols like triangles that represent tri-state
`buffers.
` Going back to Slide No. 5. Figure 4 of Yen is the
` same thing, it's just that one of ordinary skill in the art
` would know that a tri-state buffer is implemented --
` commonly implemented when using a four stack of transistors
` having opposite connectivity types. That's just the way
` that it's done. It's the way that it's been done forever.
` That's the only way that I know of that you can -- that you
` would implement a CMOS tri-state buffer. So there are two
`
`1
`2
`3
`4
`5
`6
`7
`8
`9
`10
`11
`12
`13
`14
`15
`16
`17
`18
`19
`20
`21
`22
`23
`24
`25
`26
`
`14
`
`
`
`Case IPR2017-01632
`Patent 8,035,417 B1
`
` implementations of the same thing.
` So when you're -- when you're looking at Figure 3 of
` Yen, you include Figure 4 of Yen because they're describing
` the same thing, just from different perspectives.
` So you could do the same thing -- the same way that
` you eliminated the output buffer circuit 42 in Figure 3, you
` could also eliminate the output buffer circuit by this
` unhighlighted stack of transistors in Figure 4.
` Okay. So Macronix also says that, "A person of
` ordinary skill in the art would not -- would not combine
` these references because it changes the fundamental nature
` of the Yen reference in such a catastrophic way that it
` wouldn't work properly," but it's not true.
` If you needed -- if you needed Jain to operate in a
` mode that had a default output buffer circuit, all you would
` need to do is tie the ADD0 signal high, and that would
` remain -- that would ensure that the -- in Jain, Figure 6 --
` that the output buffer circuit 60 at the top would stay high
` as long as the output buffer circuit were enabled using the
` output enable signal.
` These -- these two diagrams are so similar in
` nature -- another way to think of it is you could think of
` it as ADD0 as being redundant. You don't need two different
` signals, output enable and ADD0, in order to -- to turn that
` first output buffer circuit off, you just need one or the
` other. And so you could have -- you could have implemented
`
`1
`2
`3
`4
`5
`6
`7
`8
`9
`10
`11
`12
`13
`14
`15
`16
`17
`18
`19
`20
`21
`22
`23
`24
`25
`26
`
`15
`
`
`
`Case IPR2017-01632
`Patent 8,035,417 B1
`
` Jain the way that you did in Yen and saved a little bit of
` area, not used that AND gate. They're interchangeable,
` hardly any difference at all, it's a simple combination, you
` don't lose anything.
` I want to take a look at the second contested
` claim -- or second contested limitation of Claim 1. I'm
` turning to petitioner's demonstrative Slide No. 8.
` Once again, we're looking at Claim 1 of the '417
` patent on the right, and highlighted is the second contested
` limitation in the second "wherein" clause, the final "wherein" clause of the
`claim, and on the left, again, we're looking
` at Figure 6.
` The limitation in question reads, "The buffer enable
` signals and the complements of the buffer enable signals
` control pairs of transistors having opposite connectivity
` types." Yen discloses this. Let's take a look.
` Turn to Slide 9. On the left I have that same
` second "wherein" clause that contains the second contested --
` the same -- the second disputed limitation of Claim 1, and
` on the right I have Figure 4 of Yen, transistor level
` implementation of the invention, and it has some color
` annotations.
` Let's just look at the claim. "Buffer enable
` signals and the complements of the buffer enable signals."
` So looking over here in -- at Figure 4, on the bottom right
` of the figure, you have out enable, shared enable signal,
`
`1
`2
`3
`4
`5
`6
`7
`8
`9
`10
`11
`12
`13
`14
`15
`16
`17
`18
`19
`20
`21
`22
`23
`24
`25
`26
`
`16
`
`
`
`Case IPR2017-01632
`Patent 8,035,417 B1
`
` OS1 and OS2. Those are customized enable signals. Those
` are buffer enable signals.
` At the top, output enable bar, OS1 bar, and OS2 bar.
` Those are complements of the buffer enable signals. So it's
` right there. Buffer enable -- the claim requires buffer
` enable signals and the complements of the buffer enable
` signals.
` The rest of the limitation reads, "Control pairs of
` transistors having opposite connectivity types." Well,
` let's look at what these signals do.
` OS1 and output enable control transistor MN4 in
` Figure 4 of Yen, and then power being an NMOS device. And
` the complements of those signals control MP4, which is the
` transistor having opposite connectivity type.
` Likewise, signal OS2 and output enable control
` transistor MN6 in the bottom right of Figure 4 of Yen, and
` likewise, the output enable bar and OS2 bar, any buffer
` enable signals control transistor MP6 in the top right of
` Figure 4.
` JUDGE REPKO: So what's your pairs? Plural pairs?
` MR. HAMILTON: So plural pairs is one pair is MN4
`and MP4; that's a pair of transistors having opposite
`connectivity types. And then 6 and MP6 is a second pair of
`transistors having opposite connectivity types.
` That is, those signals, those buffer enable signals
`control pairs -- both pairs of transistors having opposite
`
`1
`2
`3
`4
`5
`6
`7
`8
`9
`10
`11
`12
`13
`14
`15
`16
`17
`18
`19
`20
`21
`22
`23
`24
`25
`26
`
`17
`
`
`
`Case IPR2017-01632
`Patent 8,035,417 B1
`
`connectivity types. That's it right there. Simple as that.
`Plain reading of the claim.
` JUDGE REPKO: So we have plural signals controlling
`plural pairs.
` MR. HAMILTON: Yes.
` JUDGE REPKO: What about each signal controlling?
`Why should we not read the claim like that?
` MR. HAMILTON: Well, because the claim doesn't say
`that. The word "each" doesn't appear in the claim.
` JUDGE REPKO: Is that consistent with the
`specification?
` MR. HAMILTON: Yes. Let's get into that.
` Let's talk about precisely that here. We'll start
` on the next slide.
` I'm looking at Toshiba's demonstrative Exhibit
` No. 10. And on the top, we're looking at an excerpt from
` the patent owner's response at 34, and on the bottom, again,
` we're looking at that second "wherein" clause that contains
` the second disputed limitation of Claim 1.
` Now, looking at the top here in the patent owner's
` response, it says, "Each buffer enable signal," and then
` Macronix's position, "Each buffer enable signal pair, that
` is a buffer enable signal and its complement signal,
` controls pairs, that is, more than one pair of transistors,
` where the two transistors in each transistor pair have
` opposite connectivity types." So that's Macronix's
`
`1
`2
`3
`4
`5
`6
`7
`8
`9
`10
`11
`12
`13
`14
`15
`16
`17
`18
`19
`20
`21
`22
`23
`24
`25
`26
`
`18
`
`
`
`Case IPR2017-01632
`Patent 8,035,417 B1
`
` position. They say, "Each buffer enable signal in the pair
` control multiple pairs of transistors having an opposite
` connectivity types."
` And -- but the claim doesn't say "each", right? And
` this is -- if you're not careful when you read this, you see
` that the "each" is within a quote. You see it's quoting
` here, it says, "Each buffer enable signals pair."
` If you're not careful, you think that the claim
` actually says that, but the claim doesn't, that's just
` Dickens saying that.
` The claim says, "The buffer enable signals and the
` complements of the buffer enable signals" -- it doesn't say
` "each" -- "control pairs of transistors of having opposite
` connectivity types."
` This "each" interpretation, let's look at where that
` came from.
` I'm looking at -- we're all looking at Toshiba's
` demonstrative Exhibit No. 11. On the left, again, we have
` the same second "wherein" clause that contains the second
` disputed limitation highlighted in yellow, and on the upper
` right we have that same excerpt from the patent owner's
` response that contains the "each" language in quotes.
` On the bottom right we have an excerpt from the
` patent owner's response that cites to Figure 2 of the '417
` patent, and the colors were annotated by Macronix in their
` response.
`
`1
`2
`3
`4
`5
`6
`7
`8
`9
`10
`11
`12
`13
`14
`15
`16
`17
`18
`19
`20
`21
`22
`23
`24
`25
`26
`
`19
`
`
`
`Case IPR2017-01632
`Patent 8,035,417 B1
`
` Now, what Macronix is doing to read -- when you take
` a look at how Macronix is reading -- their interpretation of
` how this claim should be read into this -- in this figure.
` So let's start with Z and ZB. Z and ZB are a shared
` enable signal and -- Z is a shared enable signal, ZB is its
` complement. So you have enable signal and its complement.
` The Z controls -- you see here in the red
` (inaudible) -- the Z controls a pair of transistors, and you
` see, because the arrow is pointing different ways, you have
` a PMOS and NMOS device, they're pair of transistors having
` opposite connectivity types.
` ZB, the complement, same thing. It's shown here in
` purple on the bottom left of the annotated figure.
` Transistors 214 and 216 are pairs of transistors
` having opposite connectivity types.
` So Z and ZB, a single pair of transistors having
` opposite -- a single pair -- I'm sorry.
` Z and ZB, a buffer enable signal and its complement,
` in the singular, control pairs of transistors having
` opposite connectivity types.
` But now let's look at what they do with OPON and
` OPONB. This is the customized enable signal.
` So OPON controls directly this -- in the turquoise
` color, the blue -- transistor number 218. We note here that
` it has an arrow pointing out.
` And also, if you follow the output of that signal,
`
`1
`2
`3
`4
`5
`6
`7
`8
`9
`10
`11
`12
`13
`14
`15
`16
`17
`18
`19
`20
`21
`22
`23
`24
`25
`26
`
`20
`
`
`
`Case IPR2017-01632
`Patent 8,035,417 B1
`
` it goes to -- if you follow the output of transistor 218, if
` you follow the blue -- blue wiring, that also goes to
` transistor 204, the bottom right of the figure.
` But look. The arrows on these two transistors point
` the same way, so those are not transistors having opposite
` connectivity types, those transistors have the same
` connectivity type.
` But then if you look at OPONB, it's the -- it's the
` logical dual. OPONB controls transistor 220 that has --
` it's a P-type device. And if you trace down to transistor
` 202, that's also a P-type device.
` So this is how Macronix -- this is just tortured
` interpretation of the claim language to say that this even
` reads on it because of the way that these transistors are
` arranged, but that -- that's their justification. And the
` fact is, the only justification they have for that is that
` this -- this embodiment that is shown in this figure, they
` say it reads -- it reads on the claim language that way.
` But it's an embodiment. They're trying to import
` that tortured interpretation of the embodiment in -- as a
` limitation into the claim, and we know that that's just
` absolutely not proper. You can't read --
` JUDGE REPKO: Are there other embodiments
`that better support your position?
` MR. HAMILTON: I'm sorry?
` JUDGE REPKO: Are there other embodiments in the --
`
`1
`2
`3
`4
`5
`6
`7
`8
`9
`10
`11
`12
`13
`14
`15
`16
`17
`18
`19
`20
`21
`22
`23
`24
`25
`26
`
`21
`
`
`
`Case IPR2017-01632
`Patent 8,035,417 B1
`
`in the patent that support your position?
` MR. HAMILTON: That support my position?
` JUDGE REPKO: Yeah.
` MR. HAMILTON: Absolutely. Let me give you an
`alternative theory.
` So I'm going to quickly look back at Slide No. 8.
` On Slide No. 8, the left-hand side, you have
` Figure 6 in the '417 patent. Figure 6 contains a plurality
` of output buffer circuits. I think it's 630, 632, 634, and
` 636. And inside of each of these output buffer circuits
` is -- going back to Toshiba Slide 11 -- is the output buffer
` circuit that's shown in Figure 2 of the '417 patent. So
` this is one of them.
` The whole idea of the '417 patent is you have
` multiple -- you have plurality of output buffer circuits,
` multiple output buffer circuits, and you control those
` output buffer circuits with these sets of enable signals and
` their complements.
` And what you can do is you can turn on different
` ones in order to achieve the drive strength that you want.
` What we're talking about here, the enable signal is
` controlling the drivers. Look. This is the driver. These
` two -- I'm looking at Slide 11 on the right-hand side of
` Figure 2.
` The driver are -- is this pair of transistors, 202
` and 204. That's the driver.
`
`1
`2
`3
`4
`5
`6
`7
`8
`9
`10
`11
`12
`13
`14
`15
`16
`17
`18
`19
`20
`21
`22
`23
`24
`25
`26
`
`22
`
`
`
`Case IPR2017-01632
`Patent 8,035,417 B1
`
` So when the patent is talking about controlling
` pairs of transistors having opposite connectivity types,
` that's not talking about it pointing to some random
` transistors, it's pointing -- it's talking about pairs of
` transistors having opposite connectivity. It's the driver.
` That's what the whole point of the patent is is to control
` different output drivers.
` This stuff is just logic. And what it does --
` that's not the point, the point is controlling the drivers.
` That -- that is what the patent's talking about in
` this claim when it's talking about controlling pairs of
` transistors having opposite connectivity types.
` JUDGE BARRETT: You have about five minutes left of
`your original 35.
` MR. HAMILTON: Thank you.
` Your Honor, I have put Slide 12 of Toshiba's
` demonstrative exhibits up on the screen.
` And what Slide 12 shows is, again, our familiar
` Claim 1 of the '417 patent. And again, it shows the
` highlighted disputed limitations in the first and second
` "wherein" clauses. But what this also does is this shows you
` the modifications that Macronix is trying to make to the
` claim in order to
Accessing this document will incur an additional charge of $.
After purchase, you can access this document again without charge.
Accept $ Charge
Still Working On It
This document is taking longer than usual to download. This can happen if we need to contact the court directly to obtain the document and their servers are running slowly.
Give it another minute or two to complete, and then try the refresh button.
A few More Minutes ... Still Working
It can take up to 5 minutes for us to download a document if the court servers are running slowly.
Thank you for your continued patience.
This document could not be displayed.
We could not find this document within its docket. Please go back to the docket page and check the link. If that does not work, go back to the docket and refresh it to pull the newest information.
Your account does not support viewing this document.
You need a Paid Account to view this document. Click here to change your account type.
Your account does not support viewing this document.
Set your membership
status to view this document.
With a Docket Alarm membership, you'll
get a whole lot more, including:
- Up-to-date information for this case.
- Email alerts whenever there is an update.
- Full text search for other cases.
- Get email alerts whenever a new case matches your search.
One Moment Please
The filing “” is large (MB) and is being downloaded.
Please refresh this page in a few minutes to see if the filing has been downloaded. The filing will also be emailed to you when the download completes.
Your document is on its way!
If you do not receive the document in five minutes, contact support at support@docketalarm.com.
Sealed Document
We are unable to display this document, it may be under a court ordered seal.
If you have proper credentials to access the file, you may proceed directly to the court's system using your government issued username and password.
Access Government Site
