United States Patent (19)
`G00drum
`
`54 EXPANSION CARD INSERTION AND
`REMOVAL
`75 Inventor: Alan L. Goodrum, Tomball, Tex.
`73 Assignee: Compaq Computer Corporation,
`Houston, TeX.
`
`USOO5922060A
`Patent Number:
`11
`(45) Date of Patent:
`
`5,922,060
`9
`9
`Jul. 13, 1999
`
`9
`
`5,680,288 10/1997 Carey et al. ............................ 361/118
`FOREIGN PATENT DOCUMENTS
`0 241905 10/1987 European Pat. Off..
`0 254 456 1/1988 European Pat. Off..
`28 50 440 5/1979 Germany.
`34 09 021 9/1985 Germany.
`WO 93/15459 8/1993 WIPO.
`
`56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`3,767,974 10/1973 Donovan, Jr. et al. ................. 317/101
`3,853,379 12/1974 Goodman et al. ........................ 339/75
`4,079,440 3/1978 Ohnuma et al. ......
`... 361/424
`4,559,456 12/1985 Yamamoto et al. ...................... 307/66
`4,596,907 6/1986 LaGreco et al. .......................... 200/50
`4,628,413 12/1986 Speraw ..............
`... 361/415
`4,835,737 5/1989 Herrig et al. .
`... 364/900
`4,875,867 10/1989 Hoo ......................................... 439/157
`4,999,787 3/1991 McNally et al......................... 364/514
`5,003,431
`3/1991 Imsdahl .........
`... 361/415
`5,010,426 4/1991 Krenz ................
`360/97.01
`5,191.970 3/1993 Brockway et al.
`... 200/335
`5,247,619 9/1993 Mutoh et al. .....
`... 395/325
`5,309,031 5/1994 Stewart et al. ............................ 307/66
`5,310.998 5/1994 Okuno ...........
`... 235/380
`5,317,482 5/1994 Bujtas ...
`... 361/798
`5,317,483 5/1994 Swindler ...
`... 361/8O1
`5,386,567
`1/1995 Lien et al. ...
`... 395/653
`5,428,507 6/1995 Chatel et al. .
`... 361/798
`5,454,080 9/1995 Fasig et al. ...
`... 395/283
`5,473,499 12/1995 Weir .......................................... 361/58
`5,504,656 4/1996 Joist ...
`... 361/754
`5,513,329 4/1996 Pecone ......
`... 395/281
`5,530.302 6/1996 Hamre et al. .....
`... 307/147
`5,555,510 9/1996 Verseput et al. ..
`... 364/514
`5,581,712 12/1996 Herrman ...........
`... 395/283
`5,617,081
`4/1997 Madnicket al.
`340/825.03
`5,625,238 4/1997 Ady et al. ..
`... 307/147
`5,629,836 5/1997 Wright .................................... 361/755
`
`Maintenance & Service Guide, Compaq Deskpro XL Series
`Dec. 31, 1996
`22 Filed:
`of Personal Computers; pp. 3-18, 5-34; Compaq Computer
`6
`p
`pp
`pad
`p
`51) Int. Cl. ...................................................... G06F 13/00
`Corp., Houston, TX.; Dec. 15, 1995.
`52 U.S. Cl. .............................................................. 710,103
`Hot Plug Receptacle Actuated Mechanical Latch, IBM Tech
`58
`Field Of S
`h ..................................... 397/282. 283
`s
`58) Field of Searc
`S55. nical Disclosure Bulletin, vol. 34, No. 6, Nov. 1991, pp.
`363-364.
`Don Anderson, PCMCIA System Architecture, PC System
`y
`y
`Architecture Series, Second Edition, pp. 21-83, 113-141,
`145-162,229–309, 321–332, Copyright (C) 1995, by Mind
`Shar, Inc., Richardson, TX.
`Don Anderson/Tom Shanley, CardBus System Architecture,
`PC System Architecture Series, pp. 17–29, 39–58, 227–236,
`321-361, Copyright (C) 1996 by MindShare, Inc., Richard
`son, TX.
`CompactPCITM Specification, PCI Industrial Computers,
`Revision 10, Nov. 1, 1995, pp. 14, 36 and 50.
`Primary Examiner-Glenn A. Auve
`Assistant Examiner Paul R. Myers
`Attorney, Agent, or Firm Sharp, Comfort & Merrett, P.C.
`57
`ABSTRACT
`The invention features a circuit card for use with a computer
`System having a card slot electrically connected to a bus. The
`card slot has electrical contacts corresponding to lines of the
`bus. The circuit card has a first pin positioned to extend into
`the card slot when the card is inserted into the slot and
`contact a first electrical contact of the slot corresponding to
`a communication line of the bus. The circuit card also has a
`Second pin positioned to extend into the card slot when the
`card is inserted into the slot and contact a Second electrical
`contact of the slot corresponding to a clock line of the bus
`before the first pin contacts the first electrical contact.
`
`COMPUTER SSTEM
`10
`y
`
`2
`
`LOCAL BUS
`
`
`
`
`
`9 Claims, 11 Drawing Sheets
`
`
`
`75 at 51b, 51c
`50e
`500
`50b
`50c
`50d
`EXPANSION CARDSLOTS
`
`
`
`50f
`
`WESTERN DIGITAL CORPORATION, EXHIBIT 1008
`Page 1 of 17
`
`

`

`U.S. Patent
`
`Jul. 13, 1999
`
`Sheet 1 of 11
`
`5,922,060
`
`
`
`
`
`
`
`WESTERN DIGITAL CORPORATION, EXHIBIT 1008
`Page 2 of 17
`
`

`

`U.S. Patent
`
`Jul. 13, 1999
`
`Sheet 2 of 11
`
`5,922,060
`
`GNO PIN 114
`
`Woc PIN 112
`
`
`
`
`
`
`
`
`
`EXPANSION CARD
`
`104 PRESENCE PIN
`106 PC CLOCK PIN
`O 1 Ooo ol
`{
`PCIBUS
`COMMUNICATION PINS N108
`
`EXPANSION
`CARD SLOT
`
`RST
`Vic
`contact"
`
`SIGNAL LINE CONTACIS N132
`FIC.. 2
`
`CLOCK
`LINE
`
`50
`
`
`
`56
`
`GRANT SIGNALS
`61 TO MISING
`
`
`
`REQUEST SIGNALS
`63 FROM MONITORING
`CIRCUITS
`
`
`
`
`
`
`
`
`
`
`
`CONFIG
`REG
`
`
`
`ARBITER
`
`60
`
`
`
`PRIMARY PC BUS
`
`22
`
`/30
`
`
`
`
`
`BUFFERS
`
`BUFFER
`CONTROL
`
`INTERRUPT || PC-PC
`ROUTING
`BRIDGE
`CIRCUIT
`
`PC
`MASTER
`
`PC
`SLAVE
`
`SECONDARY PC BUS
`FIC. 3
`
`32
`
`WESTERN DIGITAL CORPORATION, EXHIBIT 1008
`Page 3 of 17
`
`

`

`U.S. Patent
`
`Jul. 13, 1999
`
`Sheet 3 of 11
`
`5,922,060
`
`
`
`PRESENCE
`CONTACT
`
`| PRESENCE
`CONTACT
`
`51
`
`WESTERN DIGITAL CORPORATION, EXHIBIT 1008
`Page 4 of 17
`
`

`

`S. Patent
`
`Jul. 13, 1999
`
`Sheet 4 of 11
`
`5,922,060
`
`
`
`51
`
`WESTERN DIGITAL CORPORATION, EXHIBIT 1008
`Page 5 of 17
`
`

`

`U.S. Patent
`
`Jul. 13, 1999
`
`Sheet S of 11
`
`5,922,060
`
`250
`
`INSERTION/
`REMOVAL OF
`CARD
`
`
`
`
`
`CPU
`DELAYED
`REQUEST
`
`RETRYING
`MASTER
`
`
`
`
`
`
`
`
`
`
`
`WESTERN DIGITAL CORPORATION, EXHIBIT 1008
`Page 6 of 17
`
`

`

`U.S. Patent
`
`Jul. 13, 1999
`
`Sheet 6 of 11
`
`5,922,060
`
`VCC PINT-112
`VOLTAGE
`PC1
`CLOCK PIN /-106
`VOLTAGE *
`
`T
`
`- NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNN
`
`FIG. 6
`
`-O-
`
`REMAINING PCI BUS
`SIGNALS CONNECTED
`
`WCC PIN-112
`VOLTAGE
`
`PC1
`
`clock PN,06
`
`VOLTAGE
`
`RST PIN /110
`VOLTAGE
`
`PRESENCE
`PIN - 04
`VOLTAGE
`
`T
`
`4
`
`T3
`
`|
`
`t
`
`t
`
`t
`
`t
`
`FIC. 7
`
`T2
`
`--O-
`SIGNAL LINES
`DISCONNECTED
`
`WESTERN DIGITAL CORPORATION, EXHIBIT 1008
`Page 7 of 17
`
`

`

`U.S. Patent
`
`Jul. 13, 1999
`
`Sheet 7 of 11
`
`5,922,060
`
`GNTA
`
`FRAME
`
`1–in H. t
`ER F. t
`
`RST
`
`-- t
`-
`-->
`DURATION SET
`BY TIMER 224
`
`FIG. 8
`
`WESTERN DIGITAL CORPORATION, EXHIBIT 1008
`Page 8 of 17
`
`

`

`U.S. Patent
`
`Jul. 13, 1999
`
`Sheet 8 of 11
`
`5,922,060
`
`2
`
`2
`
`
`
`500
`y
`l
`al
`s
`
`EXPANSION CARD
`100
`
`PRESENCE PIN
`
`CARD 100
`BEING
`INSERTED
`INTO
`SLOT 50
`
`26
`
`12
`8
`
`GOING DOWN = H
`INS1 = L
`INS2 = H
`TIMEOUT = L.
`GOING UP = L
`
`EXPANSION CARD
`100
`-------
`
`PRESENCE PIN
`
`CARD 100
`FULLY
`INSERTED
`INTO
`SLOT 50
`AND
`POWERED UP
`
`126 128
`
`FIC. 9
`
`GOING DOWN = L
`INS1 = L
`INS2 = L
`TIMEOUT = H
`GOING UP =
`
`WESTERN DIGITAL CORPORATION, EXHIBIT 1008
`Page 9 of 17
`
`

`

`U.S. Patent
`
`Jul. 13, 1999
`
`Sheet 9 of 11
`
`5,922,060
`
`EXPANSION CARD
`100
`
`PRESENCE PIN
`
`CARD 100
`BEING
`PARTIALLY
`INSERTED
`INTO
`SLOT 50
`
`126 128
`
`GOING DOWN = H
`N: = L
`NS2 = H
`
`GOING UP = L.
`
`EXPANSION CARD
`100
`-
`
`PRESENCE PIN
`
`104 PRESENCE PIN
`
`clip
`
`REMOVED
`FROM
`SLOT 50
`E.
`INSERTION
`
`502
`y
`
`a.
`d
`s L
`
`2
`
`t
`as
`
`
`
`2
`S2
`s
`t
`
`al
`
`
`
`126 128
`
`FIC, 1 O
`
`GOING DOWN = L.
`INS1 = H
`INS2 = H
`TIMEOUT = L
`GOING UP = L
`
`WESTERN DIGITAL CORPORATION, EXHIBIT 1008
`Page 10 of 17
`
`

`

`U.S. Patent
`
`Jul. 13, 1999
`
`Sheet 10 of 11
`
`5,922,060
`
`
`
`S.
`S2
`
`EPs CARD
`-
`
`PRESENCE PIN
`
`CARD 100
`BEING
`REMOVED
`FROM
`SLOT 50
`
`504
`y
`a.
`d
`
`26 128
`
`GOING DOWN = L
`INS1 = L
`INS2 = H
`TIMEOUT = L
`GOING UP = H
`
`
`
`
`
`EXPANSION CARD
`100 -
`
`PRESENCE PIN
`
`104 PRESENCE PIN
`
`CEpo
`
`REMOVED
`FROM
`SLOT 50
`AND
`POWERED
`DOWN
`
`126 128
`
`FIC. 1 1
`
`GOING DOWN = L
`INS1 = H
`INS2H = H
`TIMEOUT = L.
`GOING UP = L.
`
`WESTERN DIGITAL CORPORATION, EXHIBIT 1008
`Page 11 of 17
`
`

`

`U.S. Patent
`
`Jul. 13, 1999
`
`Sheet 11 of 11
`
`5,922,060
`
`as
`s
`t
`S
`
`
`
`506
`y
`l
`g
`s
`
`EXPANSION CARD
`100
`
`PRESENCE PIN
`
`CARD 100
`BEING
`PARTIALLY
`REMOVED
`FROM
`SLOT 50
`
`126 128
`
`GOING DOWN = L
`INS1 = L
`INS2 = H
`TIMEOUT = L.
`GOING UP = H
`
`EXPANSION CARD
`100
`--
`
`PRESENCE PIN
`
`126 128
`
`GOING DOWN = L
`INS1 = L
`INS2 = L
`TIMEOUT = L
`FIG. 12 GOING UP = L
`
`CARD 100
`FULLY
`INSERTED
`INTO
`SLOT 50
`AND
`BEING
`POWERED UP
`AFTER
`PARTIAL
`REMOVAL
`
`WESTERN DIGITAL CORPORATION, EXHIBIT 1008
`Page 12 of 17
`
`

`

`1
`EXPANSON CARD INSERTION AND
`REMOVAL
`
`BACKGROUND
`The invention relates to inserting and removing expansion
`cards.
`Computer Systems typically have expansion card Slots for
`receiving and electrically coupling expansion cards to an
`expansion bus of the computer System. The expansion bus
`may be one of Several types, Such as an Industry Standard
`Architecture (ISA) bus, an Extended Industry Standard
`Architecture (EISA) bus, or a Peripheral Component Inter
`connect (PCI) bus.
`
`SUMMARY
`In general, in one aspect, the invention features a circuit
`card for use with a computer System having a card Slot
`electrically connected to a bus. The card slot has electrical
`contacts corresponding to lines of the bus. The circuit card
`includes a first pin positioned to extend into the card Slot
`when the card is inserted into the slot and contact a first
`electrical contact of the slot corresponding to a communi
`cation line of the bus. The circuit card also has a Second pin
`positioned to extend into the card slot when the card is
`inserted into the slot and contact a Second electrical contact
`of the slot corresponding to a clock line of the bus before the
`first pin contacts the first electrical contact.
`Implementations of the invention may include one or
`more of the following. The circuit card may have a third pin
`positioned to extend into the card slot when the card is
`inserted into the Slot and contact a third electrical contact of
`the slot corresponding to a power Supply line before the first
`pin contacts the first electrical contact. The position of the
`third pin may allow the third pin to contact the third
`electrical contact before the Second pin contacts the Second
`electrical contact when the card is inserted into the slot. The
`position of the third pin may permit the third pin and the
`Second pin to concurrently contact the Second and third pins
`when the card is inserted into the slot. The circuit card may
`have a third pin positioned to extend into the card slot when
`the card is inserted into the Slot and contact a third electrical
`contact of the slot used to indicate presence of the circuit
`card in the slot. This third pin may contact the third electrical
`contact before the first and Second pin contacts the first and
`Second electrical contacts when the card is inserted into the
`slot. The first pin may be shorter than the Second pin.
`In general, in another aspect, the invention features a
`computer System having a bus, a card slot connected to the
`bus, and an arbiter. The arbiter is configured to receive
`requests for access to the bus and Selectively grant access to
`the bus. The computer System also has a circuit connected to
`the card slot and configured to interact with the arbiter to
`request access for the bus when a card is inserted into the
`slot.
`Implementations of the invention may include one or
`more of the following. The computer System may have a
`central processing unit and another circuit connected to the
`card slot configured to detect insertion of a card into the card
`Slot and provide an indication to the central processing unit
`when the card is inserted into the slot. The circuit configured
`to interact with the arbiter may hold access to the bus when
`granted by the arbiter until the card is fully inserted into the
`slot.
`In general, in another aspect, the invention features a
`computer System having a bus, a card slot connected to the
`
`15
`
`25
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`5,922,060
`
`2
`bus, and an arbiter. The arbiter is configured to receive
`requests for access to the bus and Selectively grant access to
`the bus. The computer System also has a circuit connected to
`the card slot and configured to interact with the arbiter to
`request acceSS for the bus when the card is removed from the
`slot.
`Implementations of the invention may include one or
`more of the following. The computer System may have a
`central processing unit and another circuit connected to the
`card slot configured to detect removal of a card from the card
`Slot and provide an indication to the central processing unit
`when the card is removed from the slot. The circuit config
`ured to interact with the arbiter may hold access to the bus
`when granted by the arbiter until the card is fully removed
`from the slot.
`In general, in another aspect, the invention features a
`computer System having a central processing unit, a bus, a
`card slot connected to the bus, and a circuit. The circuit is
`connected to the card slot and configured to provide an
`indication to the central processing unit when the card is
`inserted into the slot.
`In general, in another aspect, the invention features a
`computer System having a central processing unit, a bus, a
`card slot connected to the bus, and a circuit. The circuit is
`connected to the card slot and configured to provide an
`indication to the central processing unit when the card is
`removed from the slot.
`In general, in another aspect, the invention features a
`method for use in a computer System having a bus and a card
`Slot connected to the bus. The method includes detecting
`insertion of the card into the Slot and arbitrating for control
`of the bus when insertion is detected.
`In general, in another aspect, the invention features a
`method for use in a computer System having a bus and a card
`Slot connected to the bus. The method includes detecting
`removal of the card from the slot and arbitrating for control
`of the bus when removal is detected.
`In general, in another aspect, the invention features a
`method for use in a computer System having a card Slot
`connected to the bus. The method includes detecting partial
`insertion of a card into the card slot and holding the card in
`reset between a time when the card is partially inserted into
`the card Slot and a time when the card is more fully inserted
`into the card slot.
`Implementation of the invention may include the com
`puter System having a central processing unit, and the
`method may include indicating to the central processing unit
`when the card has been inserted into the slot.
`In general, in another aspect, the invention features a
`method for use in a computer System having a card Slot
`connected to a bus. The method includes detecting removal
`of a card from the card slot and holding the card in reset
`between a time when the card is partially removed from the
`card slot and a time when the card is more fully removed
`from the card slot.
`Implementation of the invention may include the com
`puter System having a central processing unit, and the
`method may further include indicating to the central pro
`cessing unit when the card has been removed from the slot.
`In general, in another aspect, the invention features a
`method for use in a computer System having a card Slot
`connected to a bus and a central processing unit. The method
`includes detecting removal of the card from the slot and
`indicating to the central processing unit when the card has
`been removed from the slot.
`
`WESTERN DIGITAL CORPORATION, EXHIBIT 1008
`Page 13 of 17
`
`

`

`5,922,060
`
`5
`
`15
`
`3
`In general, in another aspect, the invention features a
`method for use in a computer System having a card Slot
`connected to a bus and a central processing unit. The method
`includes detecting insertion of the card into the slot and
`indicating to the central processing unit when the card has
`been inserted into the slot.
`In general, in another aspect, the invention features a
`computer System having a bus having lines for communi
`cation and having a clock line; a central processing unit
`capable of accessing the bus, and a card slot electrically
`connected to the bus. The card Slot has electrical contacts
`corresponding to the lines of the bus. The computer System
`also has a circuit card inserted into the slot having a first pin
`positioned to extend into the card slot when the card is
`inserted into the slot and contact a first electrical contact of
`the slot corresponding to one of the communication lines of
`the bus. The computer System also has a Second pin posi
`tioned to extend into the card slot when the card is inserted
`into the Slot and contact a Second electrical contact of the
`slot corresponding to the clock line of the bus before the first
`pin contacts the first electrical contact.
`In general, in another aspect, the invention features a
`circuit card for use with a bus having communication lines.
`The circuit card includes a communication pin for electri
`cally connecting to one of the communication lines of the
`bus and a clock pin being longer than the communication
`pin.
`In general, in another aspect, the invention features a
`computer System having a central processing unit and a bus
`having communication lines. The computer System also has
`a circuit card including a communication pin for electrically
`connecting to one of the communication lines of the bus and
`a clock pin being longer than the communication pin.
`Among the advantages of the invention are one or more
`of the following. Operations on a card inserted into the Slot
`are powered up in an orderly fashion. Operations on a card
`removed from the slot are halted in an orderly fashion. A
`current transaction on the bus is halted in an orderly fashion
`when a card is inserted into or removed from the slot. A
`40
`conventional slot may be used.
`Other advantages and features will become apparent from
`the following description and from the claims.
`
`25
`
`4
`pins 102-114 of the card 100) the card 100 to a secondary
`Peripheral Component Interconnect (PCI) bus 32 when the
`card 100 is fully inserted.
`For purposes of coordinating the insertion and removal of
`the card 100 with operations on the bus 32, monitoring
`circuits 51a- f (one for each of the expansion card slots
`50a-f), of design 51, interact with a PCI-PCI bridge circuit
`30 to request control of (i.e., arbitrate for) the secondary PCI
`bus 32 when one of the monitoring circuits 51a–f senses
`insertion or removal of the expansion card 100 into or from
`its slot 50. Because of the relatively long time (e.g., tenths
`of a Second as compared to microSeconds) required for
`Someone to insert or remove the card 100, before PCI
`communication pins 108 of the card 100 are electrically
`disconnected from (upon removal of the card 100) or
`connected to (upon insertion of the card 100) corresponding
`communication lines (e.g., address/data lines) of the PCI bus
`32, the bridge circuit 30 grants control of the PCI bus 32 to
`the monitoring circuit 51, thereby excluding other bus
`masters from using the bus 32. Therefore, when electrical
`connections are being made or broken, resultant glitches on
`the PCI bus 32 do not disturb operations of other bus devices
`connected to the bus 32 (e.g., other cards 100 that are
`inserted and powered up).
`The cards 100 are powered up through a power up
`Sequence and powered down through a power down
`Sequence. Portions of the power up Sequence (card 100 is
`inserted) and the power down sequence (card 100 is
`removed) are governed by the relative lengths of the pins
`102-114 of the card 100 and the movement of the pins
`102-114 within the slot 50 during insertion and removal, as
`described below.
`AS shown in FIG. 7, in the power down Sequence, the card
`100 being removed is first placed in reset (at time T,) by
`asserting a reset pin 110 of the card 100. Next, the PCI bus
`communication signals (e.g., the signals from the address/
`data lines of the bus 32) are disconnected (at time T.) from
`the card 100. The PCI clock signal is subsequently discon
`nected (at time T.) from a PCI clock pin 106 of the card 100
`before power from the card 100 is removed at time T. The
`power down Sequence reduces the propagation of false
`signals from the card 100 being removed to the bus 32
`because circuitry on the card 100 remains functional (due to
`the connection of power and the clock signal to the card 100)
`until the PCI bus communication Signals are removed.
`AS shown in FIG. 6, in the power up Sequence, the card
`100 is first configured to be in reset when power is supplied
`(at time T). Thereafter, a PCI clock signal (from the PCI bus
`32) is furnished (at time T) to the card 100 being inserted.
`Remaining PCI bus communication signals of the card 100
`are then coupled (at time Ts) to corresponding lines of the
`PCI bus 32. The card 100 being inserted is brought out of
`reset (at time Tl). Lastly, the monitoring circuit 51 and the
`PCI-PCI bridge circuit 30 interact to release control of the
`secondary PCI bus 32 and allow other bus masters to carry
`out transactions on the bus 32.
`In addition to the PCI-PCI bridge circuit 30, the com
`puter system 10 includes a central processing unit (CPU) 12,
`a level two (L2) cache 14, and a system memory 20, all of
`which are coupled to a local bus 16. A system controller/host
`bridge circuit 18 interfaces the local bus 16 to a primary PCI
`bus 22 and furnishes an interface to the system memory 20.
`The PCI-PCI bridge circuit 30, a video controller 26, and
`a PCI-Industry Standard Architecture (PCI-ISA) bridge cir
`cuit 24 are all coupled to the primary PCI bus 22. The video
`controller 26 interfaces the PCI bus 22 to a display 28, and
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`35
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`DESCRIPTION
`FIG. 1 is a block diagram of a computer System.
`FIG. 2 is a Schematic diagram of an expansion card and
`an expansion card slot.
`FIG. 3 is a block diagram of a bridge circuit of FIG. 1.
`FIGS. 4A-B are Schematic diagrams of expansion card
`circuitry.
`FIG. 5 is a state diagram showing a three-level arbitration
`Scheme.
`FIGS. 6-8 are waveforms from the computer system
`illustrating power up and power down Sequences.
`FIGS. 9-12 are illustrations of an expansion card being
`inserted into and removed from a slot.
`In the following description, the suffix "#" and the prefix
`indicate negative logic.
`As shown in FIGS. 1 and 2, a computer system 10 has six
`conventional expansion card slots 50a-fin which expansion
`cards 100 can be inserted (i.e., “hot-plugged”) and removed
`while the computer System 10 remains powered up. Each
`slot 50 has spring-like contacts 120-132 for physically
`Securing the card, 100 and for electrically connecting (via
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`sé
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`the bridge circuit 24 interfaces the PCI bus 22 to an ISA bus
`34. An Intelligent Drive Electronics (IDE) interface 36 and
`an input/output (I/O) chip38 are both coupled to the ISAbus
`34. The IDE interface 36 controls operation of a CD-ROM
`drive 46 and a hard disk drive 48. The I/O chip 38 receives
`input data from a mouse 40 and a keyboard 42. The I/O chip
`38 also controls operation of a floppy disk drive 44.
`As shown in FIG. 2, for purposes of establishing the
`connection/disconnection order in the power up and power
`down Sequences, the expansion card 100 takes advantage of
`the fact that the receiving ends of the contacts 120-132 are
`equidistant from an opening 53 of the slot 50 that receives
`the card 100. Therefore, as the card 100 is inserted into the
`slot 50 (assuming the card 100 is inserted with the bottom
`edge 101 generally parallel to the top edge of the slot 50),
`a portion of the power up Sequence is established by the
`relative lengths of the pins of the card 100, as the longer pins
`make contact first. Similarly, as the card 100 is removed
`from the slot 100 (which establishes a portion of the power
`down sequence), the shorter pins of the card 100 break
`electrical contact with the contacts 120-132 first.
`In order to reset the card 100 during the power up and
`power down sequences, the reset pin 110 of the card 100
`(corresponding to the contact 120) extends as far as any of
`the other pins 102-114 toward the bottom 101 of the card
`100. For purposes of establishing a common ground for the
`power up and power down Sequences, a ground pin 114 of
`the card 100 (corresponding to the contact 124) extends as
`far down as the reset pin 110. The voltage supply pin 112 of
`the card 100 (corresponding to the contact 122) extends
`toward the bottom 101 of the card 100 but does not extend
`as far as the reset pin 110. The PCI clock pin 106
`(corresponding to the contact 130) extends toward the
`bottom 101 of the card 100 but does not extend as far as the
`voltage supply pin 112. The PCI bus communication pins
`108 (corresponding to contacts 132) extend toward the
`bottom 101 of the card 100 but do not extend as far as the
`clock pin 106. The pins 102-114 and corresponding contacts
`120-132 are shown aligned side-by-side for illustrative
`purposes.
`For purposes of requesting control of the bus 32 and
`placing the card 100 in reset before the beginning of the
`power up and power down Sequences, the monitoring circuit
`51 senses partial insertion of the card 100 into the slot 50 and
`partial removal of the card 100 from the slot 50. For
`purposes of sensing partial insertion of the card 100 into the
`slot 50, a presence Sensing pin 102 (corresponding to the
`contact 126) extends toward the bottom 101 of the card 100
`and is of the same length as the ground pin 114. The
`presence Sensing pin 102 is electrically connected to the
`ground pin 114, and when the expansion card 100 is first
`inserted into the expansion card slot 50, the ground pin 114
`of the expansion card 100 contacts the corresponding ground
`pin contact 124 of the expansion card slot 50 (which is
`coupled to ground of the computer System 10). Because the
`presence Sensing pin 102 is of the same length of the ground
`pin 104 and electrically connected to the ground pin 104, the
`presence Sensing pin 102 is connected to ground when the
`expansion card slot 100 is partially inserted into the card slot
`50. Thus, the grounding of the presence sensing pin 102
`indicates (by the transition of the voltage level of the pin
`102) when the card 100 is first inserted into the slot 50 and
`indicates when the card 100 has entirely left the slot 50.
`Similarly, for purposes of detecting when the expansion
`card 100 has been partially removed from the slot 50, the
`ground pin 114 is also electrically connected to a presence
`sensing pin 104 which is shorter than the PCI communica
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`tion pins 108. Therefore, the disconnection of the presence
`Sensing pin 104 from ground indicates (by the transition of
`the voltage level of the pin 104) the initial removal of the
`card 100 and indicates when the card 100 is fully inserted.
`Partial insertion of the card 100 into the slot 50 may
`indicate someone has initiated insertion of the card 100 into
`the slot 50. However, partial insertion may alternatively
`indicate insertion of the card 100 has been aborted. The
`monitoring circuit 51 detects both Scenarios. AS shown in
`FIG. 9, in one example 500, the slot 50 is initially empty, and
`the card 100 is then partially inserted into the slot 50 (as
`indicated by the grounding of the presence Sensing pin 102).
`The card 100 is then fully inserted into the slot 50 (as
`indicated by the grounding of the presence Sensing pin 104)
`and powered up. However, in another example 502 (FIG.
`10), instead of fully inserting the card 100 into the slot 50,
`the card 100 is subsequently removed from the slot 50 after
`partial insertion (as indicated by the disconnecting of ground
`from the presence Sensing pin 102).
`Similarly, besides recognizing when Someone has initi
`ated a removal of the card 100 from the slot 50, the
`monitoring circuit 51 also detects when a removal of the
`card 100 has been aborted. As shown in FIG. 11, in one
`example 504, a fully inserted card 50 is partially removed
`(as indicated by the disconnecting of ground from the
`presence sensing pin 104). The card 100 is then fully
`removed from the slot 50 as indicated by the disconnecting
`of ground from the presence Sensing pin 102 and powered
`down. However, instead of being fully removed from the
`slot 50, the card 100 may subsequently be fully inserted
`(FIG. 12) into the slot 50 after partial removal. The full
`insertion of the card 100 back into the slot 50 is indicated by
`the Subsequent grounding of the presence Sensing pin 104
`after the detected partial removal of the card 100 (indicated
`by disconnection of ground from the presence Sensing pin
`102).
`AS shown in FIG. 3, for purposes of controlling access to
`the PCI bus 32, the PCI-PCI bridge circuit 30 includes an
`arbiter 60. The arbiter 60 receives PCI request signals (via
`request lines 63 separate from request lines of the bus 32)
`from the monitoring circuits 51a–f and furnishes corre
`sponding grant signals (via grant lines 61 Separate from
`grant lines of the bus 32) to the monitoring circuits 5la-f.
`Although the arbiter 60 has a programmable grant timer
`(programmed via configuration registers 56) to govern the
`maximum duration a bus master may hold the bus 32, the
`arbiter 60 allows the monitoring circuit 51 to hold access to
`the bus 32 until the monitoring circuit 51 releases the bus (at
`the completion of the power up or power down sequence),
`as described below.
`As shown in FIG. 5, the arbiter 60 has three levels 250,
`252, and 254 of arbitration. In the first level 250 (the highest
`priority level), the arbiter 60 arbitrates in a round-robin
`fashion between a request from the second level 252 (the
`level with the second highest priority) and a request 256
`from one of the monitoring circuits 51a-f. For the second
`level 252, the arbiter 60 arbitrates in a round-robin fashion
`between requests 260 from a retrying master on the bus 32,
`a third level request 254 (lowest priority level), and a CPU
`10 delayed request 258. For the third level 254, the arbiter
`60 arbitrates in a round-robin fashion between requesting
`masters 262-274 on the bus 32. Therefore, at most, only one
`transaction is performed when either the card 100 is first
`partially inserted or removed, and after the one transaction,
`the arbiter 60 grants control to the monitoring circuit 51
`requesting the bus 32.
`For transactions on the primary PCI bus 22, the bridge
`circuit 30 includes a PCI slave 54 and a PCI master 52, both
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`of which are coupled to the primary PCI bus 22. For
`transactions on the secondary PCI bus 32, the bridge circuit
`30 includes a PCI master 62 and a PCI slave 64, both of
`which are coupled to the secondary PCI bus 32. Buffers 58
`interact with buffer control logic 66 to control the flow of
`transactions between the buses 22 and 32 and preserve the
`PCI transactional ordering rules. Interrupt routing logic 68
`directs the flow of interrupt requests from the bus 32 to the
`bus 22.
`For purposes of indicating to the CPU 10 when the card
`100 has been partially inserted or removed, the monitoring
`circuit 51 furnishes an interrupt request signal INTER
`RUPTi which is asserted, or driven low, to indicate a
`detected insertion or removal and deasserted, or driven high,
`otherwise. As shown in FIG. 4A, in order to furnish the
`signal INTERRUPTH, the monitoring circuit 51 includes an
`interrupt circuit 154. The signal INTERRUPTH is furnished
`by the inverting output of a D-type flip-flop 155 which is
`clocked on the positive edge of a PCI clock signal CLK
`(from the bus 32). The input of the flip-flop 155 is connected
`to the output of an OR gate 157 which has one input
`connected to the output of an AND gate 161. The AND gate
`161 receives a signal INS1#and a signal GOING UP. The
`signal GOING UP is asserted, or driven high, to indicate
`when the card 100 is being removed from the Blot 50. The
`signal INS1 it is indicative of the voltage level of the contact
`126 (corresponding to the pin 102). Therefore, when the card
`100 is removed from the slot 50, the signal INTERRUPTH
`is asserted.
`Another input of the OR gate 157 is connected to the
`output of an AND GATE 159. The AND gate 159 receives
`a signal GOING DOWN that is asserted, or driven high, to
`indicate when the card 100 is being inserted into the slot 50.
`The AND gate 159 also receives a signal INS2# and a signal
`TIMEOUT. The signal INS2# is indicative of the voltage
`level of the contact 128 (corresponding to the pin 104). The
`signal TIME OUT is asserted, or driven high, to indicate
`when the card