United States Patent [19]
`Wang et al.
`
`[54] NETWORK CONTROLLER WHICH
`ENABLES THE LOCAL PROCESSOR TO
`HAVE GREATER ACCESS TO AT LEAST
`ONE MEMORY DEVICE THAN THE HOST
`COMPUTER IN RESPONSE TO A CONTROL
`SIGNAL
`
`[75] Inventors: Jerry Borjeng Wang. Lake Forest;
`Robert Vernon Harper. Torrance;
`Chih-Chung Shi. Yorba Linda. all of
`Calif.
`
`[73] Assignee: Toshiba American Information
`Systems, Inc.. Irvine. Calif.
`
`[21] Appl. No.: 310,298
`[22] Filed:
`Sep. 26, 1994
`
`[51] Int. Cl.6 .................................................... .. G06F 13/00
`[52] US. Cl. ............. .. 395/860; 395/200.45; 395/200.59;
`395/882; 395/836
`[58] Field of Search ....................... .. 340/825.05; 360/69;
`395/296. 500. 297. 200.43. 200.59. 860.
`882; 380/3; 439/61
`
`[56]
`
`References Cited
`
`U.S. PATENT‘ DOCUMENTS
`
`4,500,933
`4,803,485
`4.8 1 l ,205
`4,899,306
`
`2/1985 Chan ....................................... .. 360/69
`2/1989 Rypinski ............. ..
`.. 340182505
`3/1989 Normington et al.
`.... .. 345/502
`2/1990 Greer .................................... .. 395/500
`
`(List continued on next page.)
`
`OTHER PUBLICATIONS
`
`“Wireless Data Networks and the Mobile Workforce”. Ira
`Brodsky. Telecommunications. Dec. 1990. vol. 24. No. 12. p.
`31.
`‘The Engineering Monthly Index”. May 1992. p. 277.
`abstract of Cordless LANs Hit the Airwaves. Ira Brodsky.
`Telecommunications. Sep. 1991. v. 25. No. 9. 5p.
`
`US005765027A
`[11] Patent Number:
`[45] Date of Patent:
`
`5,765,027
`Jun. 9, 1998
`
`“Wireless LAN s Duel in Europe". Elizabeth Heichler. Elec
`tronic News. Apr. 25. 1994. p. 30.
`“PCMCIA Cards on Deck; Personal Computer Memory
`Card International Association Cards at Comdex/Fall 1993
`Trade Show.” Tammi Harbert. PC Week. Nov. 15. 1993. v.
`10. No. 5. p. 108.
`“Surge in Popularity Spans New Ideas for Wireless LAN S."
`Morris Edwards. Communication News. v. 31. No. 8. p. 55.
`Aug. 1994.
`
`Primary Examiner—Thomas C. Lee
`Assistant Examiner—Po C. Huang
`Attorney Agent, or Firm-Banner & Witcoff. Ltd.
`[57]
`ABSTRACT
`
`An application speci?c integrated circuit (ASIC)/?eld pro
`grammable gate array (FPGA) which is a component of a
`wireless LAN controller including a local processor and a
`memory enables the controller to interface with both PCM
`CIATM and AT” host computer systems. The ASIC/FPGA
`enables communication between a radio frequency commu
`nication module. a local processor. and the host computer.
`The ASIC/FPGA also includes a throttle feature that
`decreases the access of the host computer in comparison to
`access of the local processor in order to enable the local
`processor to rapidly generate an acknowledge signal as
`required by various RF LAN speci?cations. During opera
`tion of the controller. data to be transmitted by the host
`computer onto the network is written by the host to an
`SRAM via the ASIC/FPGA. and the host commands the
`local processor via the ASIC/FPGA to forward the trans
`mitted data to the RF communication module. Under the
`control of the ASIC/FPGA. the local processor then for
`wards the transmit data from the SRAM to the RF commu
`nication module. When data is received from the RF com
`munication module. the local processor. under the control of
`the ASIC/FPGA. receives the data and stores the received
`data in the SRAM. The received data is then forwarded to
`the host computer via the ASIC/FPGA.
`
`28 Claims, 16 Drawing Sheets
`
`m2
`1
`f1’
`Loot PROCESSOR
`l—_l_‘l_l
`rum
`aon-
`SM",
`ASIUFPGA _]_\1L] \
`I06
`
`'03
`
`“km
`
`nosr
`INTERFACE
`
`\m
`
`RF
`'04
`INTERFACE
`
`uosrconrunn
`
`.
`
`\m:
`
`arcnnnumcnlou
`_
`MODULE
`
`m]
`
`WESTERN DIGITAL CORPORATION, EXHIBIT 1019
`Page 1 of 26
`
`

`

`5,765,027
`Page 2
`
`US. PATENT DOCUMENTS
`
`4,972,470 11/1990 Farago ...................................... .. 380/3
`5,043,938
`8/1991 Ebelsole ..
`..... .. 395/2002
`
`395/836 395/500
`
`6/1992 Pant)!!! 5,121,482 5,159,684 10/1992 Kl'Oll e161. ..
`
`
`439/61
`5,163,333 11/19/92 Olsen et a1.
`439/55
`5,183,404
`2/1993 Aldous et a1. ..
`395120002
`$237,659 8/1993 Takats ........... ..
`5,241,632
`8/1993 O’Connell et a1. ................... .. 395/297
`
`4/1994 Abraham et a1. ..................... .. 395/500
`5,301,303
`4/1994 Szczepanek .......................... .. 370/855
`5,305,317
`5,367,646 11/1994 Pmmoset a1__
`_ 395,310
`5 396 602 3,1995 Aminj et 31
`395,293
`
`395/287
`8/1995 Th°mPs°n
`’ 1 5,444,855
`
`
`3951829
`5,457,784 10/1995 Wells et a],
`370/391
`5,479,399 12/1995 Grabenhorst er al-
`- 3951500
`5,481,696 H1996 LomP e991.
`5,598,542
`1/1997 Leung ................................... .. 395/297
`
`WESTERN DIGITAL CORPORATION, EXHIBIT 1019
`Page 2 of 26
`
`

`

`US. Patent
`
`Jun. 9, 1998
`
`Sheet 1 of 16
`
`5,765,027
`
`I02
`I
`/
`LOCAL PRO£ESSOR
`|___[__l__l
`FLASH
`SM"
`ROM \ ,
`ASlC/FPGA _I_ILSI \
`I06
`
`I03
`
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`
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`INTERFACE
`
`\m
`
`RF
`'04
`INTERFACE
`
`HOSTCOMPUTER \Ho
`
`-
`
`I201»
`
`RF COMMUNICATION
`
`MODULE
`
`WESTERN DIGITAL CORPORATION, EXHIBIT 1019
`Page 3 of 26
`
`

`

`US. Patent
`
`Jun. 9, 1998
`
`Sheet 2 of 16
`
`5,765,027
`
`0E/,WE/
`
`IORDI, IOWR/
`mm
`
`2m
`
`3
`
`CONTROL
`BUS mum
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`
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`
`— CONTROL
`
`I
`
`BUS
`INTERFACE
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`
`
`
`
`
`WESTERN DIGITAL CORPORATION, EXHIBIT 1019
`Page 4 of 26
`
`WESTERN DIGITAL CORPORATION, EXHIBIT 1019
`Page 4 of 26
`
`

`

`US. Patent
`
`Jun. 9, 1998
`
`Sheet 3 of 16
`
`5,765,027
`
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`WESTERN DIGITAL CORPORATION, EXHIBIT 1019
`Page 5 of 26
`
`WESTERN DIGITAL CORPORATION, EXHIBIT 1019
`Page 5 of 26
`
`
`
`
`

`

`US. Patent
`
`Jun. 9, 1998
`
`Sheet 4 of 16
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`5,765,027
`
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`WESTERN DIGITAL CORPORATION, EXHIBIT 1019
`Page 6 of 26
`
`WESTERN DIGITAL CORPORATION, EXHIBIT 1019
`Page 6 of 26
`
`
`

`

`US. Patent
`
`Jun. 9, 1998
`
`Sheet 5 of 16
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`5,765,027
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`WESTERN DIGITAL CORPORATION, EXHIBIT 1019
`Page 7 of 26
`
`WESTERN DIGITAL CORPORATION, EXHIBIT 1019
`Page 7 of 26
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`
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`
`

`

`US. Patent
`
`Jun. 9, 1998
`
`Sheet 6 0f 16
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`5,765,027
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`WESTERN DIGITAL CORPORATION, EXHIBIT 1019
`Page 8 of 26
`
`

`

`U.S. Patent
`
`Jun. 9, 1998
`
`Sheet 7 0f 16
`
`5,765,027
`
`
`
`E = 22 22.
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`
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`9: ill 22: £0” E: a.
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`WESTERN DIGITAL CORPORATION, EXHIBIT 1019
`Page 9 of 26
`
`

`

`US. Patent
`
`Jun. 9, 1998
`
`Sheet 8 0f 16
`
`5,765,027
`
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`WESTERN DIGITAL CORPORATION, EXHIBIT 1019
`Page 10 of 26
`
`

`

`US. Patent
`
`Jun. 9, 1998
`
`Sheet 9 0f 16
`
`5,765,027
`
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`WESTERN DIGITAL CORPORATION, EXHIBIT 1019
`Page 11 of 26
`
`WESTERN DIGITAL CORPORATION, EXHIBIT 1019
`Page 11 of 26
`
`
`

`

`US. Patent
`
`Jun. 9, 1993
`
`Sheet 10 of 16
`
`5,765,027
`
`FIG. 9
`
`”mm mm
`
`vcc
`
`F D R D
`
`vcc
`
`um I
`
`DATAS
`
`I
`
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`
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`
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`
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`
`WESTERN DIGITAL CORPORATION, EXHIBIT 1019
`Page 12 of 26
`
`WESTERN DIGITAL CORPORATION, EXHIBIT 1019
`Page 12 of 26
`
`

`

`US. Patent
`
`Jun. 9, 1998
`
`Sheet 11 of 16
`
`5,765,027
`
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`
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`
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`
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`
`WESTERN DIGITAL CORPORATION, EXHIBIT 1019
`Page 13 of 26
`
`

`

`US. Patent
`
`Jun. 9, 1998
`
`Sheet 12 0f 16
`
`5,765,027
`
`2 =2
`
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`
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`WESTERN DIGITAL CORPORATION, EXHIBIT 1019
`Page 14 of 26
`
`

`

`US. Patent
`
`Jun. 9, 1998
`
`Sheet 13 of 16
`
`5,765,027
`
`SOURCE
`
`HOST
`
`FIG. 12
`DESCRIPTION
`SIGNALS A0 THROUGH A25 ARE 26 ADDRESS BUS LINES CAPABLE OF
`ADDRESSING 64 MEGABYTES OF MEMORY ON THE CARD. A25 IS THE MOST
`SIGNIFICANT BIT. IN THE PCMCIA CARD, ONLY A0 TH ROUGH AI2 ARE USED.
`SIGNALS DO THROUGH DIS CONSTITUTE THE BI-DIRECTIONAL DATA BUS.
`DIS IS THE MOST SIGNIFICANT BIT.
`THE CEI/ AND CE2/ ARE CARD-ENABLE SIGNALS. THE CEI/ ENABLES EVEN
`NUMBERED-ADDRESS BYTES, CEZ/ ENABLES ODD-NUMBERED-ADDRESS
`BYTES.
`THE OE/ LINE IS THE ACT IVE-LOW. INPUT SIGNAL USED TO GATE MEMORY
`"0“ READ DATA INTOIHE PCMCIA CARD.
`HOST
`THE wE/ INPUT SIGNAL IS USED FOR smoams MEMORY WRITE DATA mm
`THE PCMCIA cm.
`
`HOST/
`LOCAL
`
`HOST
`
`NAME
`
`AO-A25
`
`Dams
`
`GE I/, GEZ/
`
`0E’
`WE,
`
`cm /
`my’
`
`LOCAL
`
`REG/
`
`HOST
`
`RESET
`
`HOST
`
`Wm’
`
`THE CDI/ AND CDZ/ SIGNALS PROVIDE FOR PROPER DETECTION OF CARD
`INSERTION. THE CDI/ AND CDZ/ SIGNALS ARE CONNECT ED TO GROUND
`INTE RNALLY ON THE PCMCIA CARD.
`WHEN THE REG/ SIGNAL IS ACTIVE. ACCESS IS LIMITED TO ATTRIBUTE
`MEMORY AND I/O SPACE. REG/ SIGNAL IS KEPT INACTIVE FOR ALL COMMON
`' MEMORY ACCESS.
`THE RESET SIGNAL CLEARS THE CARD CONFIGURATION OPTION REGISTER
`THUS PLACING A CARD IN UNCONFIGURED STATE. THE HOST WILL ACTIVATE
`THIS SIGNAL AT THE BEGINNING OF ANY CARD INSERTION.
`THE WAIT SIGNAL IS ASSERTED BY A CARD TO DELAY COMPLETION OF THE
`I00“ MEMORY-ACCESS 0H IIO-ACCESS CYCLE IN PROGRESS.
`THE INTERRUPT REQUEST (IREQI) SIGNAL IS ASSERTED 1o INDICATE THE
`mm, mm NEED OF THE HOST SOFTWARE SERVICE. IT'S AVAILABLE ONLY WHEN THE
`CARD AND THE INTERFACE ARE CONFIGURED FOR THE I/O INTERFACE. THE
`IREQ/ CAN BE EITHER LEVEL OR PULSE MODE.
`THE IORD/ SIGNAL IS MADE ACTIVE TO READ DATA FROM THE CARD'S IIO
`SPACE. THE REG/ SIGNAL AND AT LEAST ONE OF CE I/ OR CE2/ MUST ALSO
`BE ACTIVE FOR THE IIO TRANSFER TO TAKE PLACE.
`THE IOWR/ SIGNAL IS MADE ACTIVE TO WRITE DATA TO THE CARD'S I/O
`SPACE. THE REG/ SIGNAL AND AT LEAST ON OF CEII OR CE2/ MUST ALSO BE
`ACTIVE FOR THE IIO TRANSFER TO TAKE PLACE.
`THE INPACK/ SIGNAL IS ASSERTED WHEN THE PCMCIA CARD'S I/O SPACE IS
`SELECTED. THIS SIGNAL IS USED TO CONTROL THE ENABLE OF ANY INPUT
`DATA BUFFER.
`TWO VCC AND FOUR GND PINS ARE EMPLOYED TO REDUCE THE IMPEDANCE
`BETWEEN THE PCMCIA CARD AND THE SYSTEM.
`
`IORD/
`
`HOST
`
`IOWR/
`
`HOST
`
`INPACK/
`
`LOCAL
`
`VCC, GND
`
`HOST
`
`WESTERN DIGITAL CORPORATION, EXHIBIT 1019
`Page 15 of 26
`
`

`

`US. Patent
`
`Jun. 9, 1998
`
`Sheet 14 of 16
`
`5,765,027
`
`FIG. 13
`
`NAME
`
`SAO-SAI9
`
`SDMD' 5
`
`SOURCE
`
`HOST
`
`DESCRIPTION
`SIGNALS SAO THROUGH SAI9 ARE 2O ADDRESS BUS LINES CAPABLE
`OF ADDRESSING I MEGABYTES OF MEMORY ON THE CARD. SAI 9 IS
`THE MOST SIGNIFICANT BIT.
`HOW SIGNALS SDO THROUGH SDIS CONSTITUTE THE BI-DIRECTIONAL DATA
`LOCAL
`BUS. DIS IS THE MOSTSIGNIFICANT BIT.
`
`LMHAB HOST
`
`LAITTHROUGN LA23 ARE 7 UNLATCHED ADDRESS BUS
`
`AEN
`
`HOST
`
`BALE
`
`HOST
`
`ADDRESS ENABLE FOR I/O ADDRESS DECODING. WHEN HIGH, ALL
`ISA BUS ADDRESS, DATA AND COMMAND LINES ARE CONTROLLED BY
`THE DIRECT MEMORY ACCESS (DMA).
`BUS ADDRESS LATCH ENABLE INDICATES WHEN THE HOST CPU HAS A
`VALID ADDRESS ON THE ISA BUS.
`THE READY SIGNAL TO THE HOST r0 mmcm THATTIIE AT cm IS
`'OFHRDY ml READY TO WRITE or READ om IROMTHE HOST CPU.
`IORD/
`HOST
`THIS IS THE I/O READ SIGNAL.
`IOWR/
`HOST
`THIS IS THE I/O WRITE SIGNAL.
`IRQ3~4, 7,
`LOCAL
`THE INTERRUPT REQUEST (IRQ) SIGNALS ARE ASSERTED TO INDICATE
`9-I2, IS
`THE NEED OF THE HOST SOFTWARE SERVICE.
`THE MEMORY I6-BIT CHIP SELECT FOR A I6-BIT, I WAIT STATE
`MEMORY [mi
`
`MEMCSI6/
`
`LOCAL
`
`SBHE/
`SMEMR/
`SMEMW/
`RESET
`
`+5y GND
`'
`
`HOST
`HOST
`HOST
`HOST
`
`SYSTEM BUS HIGH ENABLE INDICATES A I6-BIT TRANSFER OF DATA.
`THIS IS THE MEMORY READ SIGNAL.
`THIS IS THE MEMORY WRITE SIGNAL.
`THE RESET SIGNAL IS USED TO RESET OR INITIALIZE THE AT CARD
`LOGICS AFTER POWER UP.
`H05] TWO IICC AND FOUR GND PINS ARE EMPLOYED TO REDUCE THE
`IMPEDANCE BETWEEN THE AT CARD AND THE SYSTEM.
`
`WESTERN DIGITAL CORPORATION, EXHIBIT 1019
`Page 16 of 26
`
`

`

`US. Patent
`
`Jun. 9, 1998
`
`Sheet 15 0f 16
`
`5,765,027
`
`NAME
`
`SOURCE
`
`MMI_CLK
`
`RF
`
`Mm 5'0
`—
`
`RF/
`LOCAL
`
`"ME
`
`LOCAL
`
`TXC/
`
`RF
`
`FIG. 14
`DESCRIPTION
`THIS 5 MHz CLOCK IS PART OF MODEM MANAGEMENT INTERFACE (MMI). THIS
`SIGNAL GOES INTO FPGA TO CLOCK THE DATA OUT THROUGH THE MMI__SIO
`LIN ES.
`SERIALIZED I/O DATA IS PART OF MODEM MANAGEMENT INTERFACE
`(MMI). THE SIGNAL IS ACTIVE LOW AND, WHEN IN COMBINATION WITH
`MMI_CLK. USED FOR SENDING COMMAND TO AND RECEIVING STATUS FROM
`THE RF MODULE.
`MODEM MANAGEMENT ENABLE (MME) IS AN ACTIVE HIGH SIGNAL. WHEN
`ACTIVE MME WILL ENABLE THE MODEM MANAGEMENT INTERFACE (MMI).
`THIS SIGNAL IS GENERATED AUTOMATICALLY BY FPGA/ASIC DURING MMI
`REGISTER ACCESS. IT IS DISABLED DU RING LOOPBACK TEST MODE.
`THIS IS A 2 MHz CLOCK FOR RF TRANSMITTER. THIS SIGNAL IS CONNECTED
`TO BOTH TCLKI AND TCLKI OF 68302 PORT I AND PORT 2.
`
`RXC/
`
`RF
`
`TXD
`
`LOCAL
`
`RXD
`
`RF
`
`RTS/
`
`LOCAL
`
`CTS/
`
`RF
`
`THIS IS A 2 MHz CLOCK FOR RF RECEIVER. THIS SIGNAL IS CONNECTED
`TO BOTH RCLIII AND RCLK2 OF 68302 PORT I AND PORT 2.
`TRANSMIT DATA (TIID) IS AN ACTIVE HIGH SIGNAL. THE LOCAL PROCESSOR
`WILL CLOCK THE DATA OUT VIA THIS LINE USING TXC/ WHEN CT S1 IS ACTIVE.
`THIS SIGNAL IS THE OR OUTPUT OF TXD I/ OR TXD2/ OF 68302.
`RECEIVE DATA (RXD) IS AN ACTIVE HIGH SIGNAL. THE LOCAL PROCESSOR
`WILL CLOCK DATA IN VIA THIS LINE USING RXC/ WHEN CRS/ IS ACTIVE. THIS
`SIGNAL IS CONNECTED TO BOTH RXDI AND RXD2 OF 68302.
`REQUEST TO SEND (RTSI) IS AN ACTIVE LOW SIGNAL. TIIIS SIGNAL IS THE
`OR OUTPUT OF RTSI/ OR RTS2/ OF 68302.
`CLEAR TO SEND (CTSI) IS AN ACTIVE LOW SIGNAL. THIS SIGNAL IS
`MONITORED BY FPGA/ASIC TO CREATE CT S302/ WHICH IS THEN
`CONNECTED TO BOTH CTSI/AND CT 52/ OF 68302 AT PORT I AND PORT 2.
`CARRIER SENSE. ACTIVE LOW. CRS/ BECOMES ACTIVE WHEN THE RF MODULE
`IS RECEIVING A MESSAGE WITH CORRECT NETWORK ID. CRS/ IS GENERATED
`ON THE RISING EDGE OF RKC_. THIS SIGNAL IS INVERTED BEFORE
`CONNECTED TO PB I0 OF 68302 TO GENERATE INTERRUPT. THIS SIGNAL
`ALSO CONNECTS TO BOTH CDI/ AND CD2! OF 68302 PORT I AND PORT 2.
`COLLISION DETECT (CDT!) IS AN ACTIVE LOW SIGNAL. THIS SIGNAL
`CONNECTED TO PBI I OF 68302.
`THIS ACTIVE HIGH SIGNAL WHEN ASSERTED WILL PUT THE RF MODULE INTO
`SLEEP MODE TO CONSERVE POWER. THIS SIGNAL IS CONNECTED TO PAIO OF
`68302.
`THIS ACTIVE HIGH SIGNAL WHEN ASSERTED WILL PUT THE RF INTO RESET
`“U5 “m STATE. nus SIGNAL IS CONTROLLED nmouen PAI I 0F 68302.
`+sv,
`+ m: mm + I2V AND M ARE omv REQUIRED ma 34-PIN RF MODULE. THE +sv IS
`| 2y 5m)
`REQUIRED FOR BOTH TYPES OF RF MODULES.
`
`CRS/
`
`CDT/
`
`RF
`
`RF
`
`PWR_DWN LOCAL
`
`WESTERN DIGITAL CORPORATION, EXHIBIT 1019
`Page 17 of 26
`
`

`

`US. Patent
`
`Jun. 9, 1998
`
`Sheet 16 of 16
`
`5,765,027
`
`FIG. 15
`
`IDENTIFICATION DATA TRANSMITTED FROM HOST
`COMPUTER TO CONTROLLER VIA HOST INTERFACE
`TO IDENTIFY THE ARCHITECTURE OF THE HOST \ | 5m
`
`I
`
`DATA TO BE TRANSMITTED ONTO NETWORK
`WRITTEN TO CONTROLLER BY THE HOST
`COMPUTER
`
`\ | 502
`
`v
`DATA TO BE TRANSMITTED IS FORWARDED
`FROM THE CONTROLLER TO A NETWORK
`COMMUNICATION MODULE IIIA A NETWORK \
`INTERFACE
`I503
`
`I
`
`DATA TRANSMITTED ONTO THE NETWORK BY THE
`NETWORK COMMUNICATION MODULE \
`I504
`
`WESTERN DIGITAL CORPORATION, EXHIBIT 1019
`Page 18 of 26
`
`

`

`5.765.027
`
`1
`NETWORK CONTROLLER WHICH
`ENABLES THE LOCAL PROCESSOR TO
`HAVE GREATER ACCESS TO AT LEAST
`ONE MEMORY DEVICE THAN THE HOST
`COMPUTER IN RESPONSE TO A CONTROL
`SIGNAL
`
`2
`and the network and having a control bus that carries control
`blocks coming to and from the host module and control
`characters of the FDDI frames coming to or from the storage
`memory. The controller interprets the control blocks to form
`control characters and forms control blocks from control
`characters.
`Also. US. Pat. No. 5.159.684 discloses a data commu
`nication interface integrated circuit with data-echoing and
`non-echoing communication modes which converts parallel
`data of a host module to serial data for transmission. e.g. in
`an Echoplex protocol or RS-232 protocol communication
`system via a telephone line. and translates received serial
`data into parallel data readable by the host module.
`However. these references do not disclose a controller for
`interfacing with a radio frequency local area network that is
`compatible with host computers having a portable or a
`desktop (e.g.. a PCMCIA or AT) architecture.
`SUMMARY OF THE INVENTION
`The present invention relates to an apparatus and method
`for an application-speci?c integrated circuit/?eld
`prograrnrnable gate array (ASIC/FPGA) that will enable
`both host computers having a PCMCIA architecture and host
`computers having an AT architecture to communicate in a
`wireless radio frequency local area network Embodiments
`of the present invention further relate to a design for a
`controller which enables a host computer having either a
`PCMCIATM or an ATTM architecture to communicate in a
`wireless local area network.
`A wireless LAN controller. according to embodiments of
`the present invention. includes a host interface for interfac
`ing with a host computer having a desktop or a portable
`computer architecture; a network interface for interfacing
`with a network communication module; a local processor;
`and a ?rst communication circuit for enabling communica
`tion between the host computer. the network interface. and
`the local processor. The ?rst communication circuit includes
`a circuit for communicating with the host computer via the
`host interface. a second communication circuit for commu
`nicating with the network communication module via the
`network interface. a third communication circuit for com
`municating with the local processor. a desktop interpretation
`circuit for receiving and interpreting information from the
`host computer when the host computm has a desktop
`architecture. and a portable interpretation circuit for receiv
`ing and interpreting information from the host computer
`when the host computer has a portable architecture.
`In another embodiment of the controller according to the
`present invention. the local processor is located within the
`?rst communication circuit.
`An ASIC/FPGA according to the present invention
`includes a circuit for receiving control signals and/or data
`from a host computer having a desktop computer architec
`ture via a host interface; a circuit for receiving control
`signals and/or data from a host computer having a portable
`computer architecture via the host interface; a transmitter for
`transmitting control signals and/or data to the host computer
`via the host interface; a circuit for receiving control signals
`and/or data from a network communication module via a
`module interface; a transmitter for transmitting control sig
`nals and/or data to the network communication module via
`the module interface; a circuit for receiving control signals
`and/or data from a local processor; and a transmitter for
`transmitting control signals and/or data to the local proces
`sor.
`Another ASIC/FPGA according to the present invention
`includes a circuit for receiving control signals and/or data
`
`BACKGROUND OF THE INVENTION
`The present invention relates to an integrated circuit/?eld
`programrnable gate array for use in a wireless radio fre
`quency local area network (LAN) controller which enables
`a PCMCIATM or ATTM host computer to communicate within
`the LAN.
`To meet the demand for new and ef?cient methods of
`communication. many types of local area networks (LANs)
`have been developed such as optical LANs (e.g.. FDDI
`networks) and LAN s in which users communicate via
`modem over telephone lines (e.g.. Echoplex networks).
`However. the increasing popularity of portable personal
`computers. also known as laptop or notebook computers. has
`created a demand for LANs that can be accessed from these
`portable computers without requiring the computer to be in
`some way hardwired to the network. thus allowing for fully
`portable network access. As a result. wireless LANs such as
`radio frequency (RF) LAN s have been developed in which
`packets of information including address information and
`data are transmitted wirelessly using radio frequency tech
`nology.
`The increasing popularity of portable personal computers
`has also fueled the need for small. lightweight. portable
`expansion devices which take the form of memory cards. As
`a result. many manufacturers began to produce memory
`cards of various sizes and capabilities. creating the need for
`an industry standard
`The Personal Computer Memory Card International Asso
`ciation (PCMCIA) was founded in 1989 and created the ?rst
`standard (1.0) for memory cards. Since that time. the PCM
`CIA has also released standard 2.1 which includes support
`not only for memory. but also for I/O devices. comprehen
`sive software architecture. and other changes. In general.
`PCMCIA cards include RAM. Flash memory and other
`types of ROM. I/O devices include voice. data and fax
`modems; network interface cards; and wireless communi
`cations. There are three sizes of PCMCIA cards: type I
`which are used for memory devices; type II which are used
`for modems. LANs. etc.; and type III which are used for
`devices such as ATA hard drives whose miniaturization
`technology is not as advanced.
`However. while PCMCIA technology is rapidly
`advancing. a large number of desktop computers are still in
`use. These computers have an IBMTM ATTM-type architec
`ture and use a standard ISA bus that is diiferent from the bus
`used in PCMCIA systems.
`As a result of the mixture of computer systems that are
`widely used. it is desirable to create softwarel?rmware that
`is capable of interfacing with both PCMCIA and AI‘ sys
`tems. Thus. it is desirable to create a controller that enables
`either type of host system to access a wireless local area
`network.
`A number of controllers for accessing local area networks
`are known. For example. US. Pat. 5.237.659 discloses a
`gateway device which provides a link between a host
`module and an optical ?ber token-ring network (e.g.. an
`FDDI network). The gateway device includes a controller
`that manages the transfer of frames between the host module
`
`20
`
`35
`
`45
`
`55
`
`WESTERN DIGITAL CORPORATION, EXHIBIT 1019
`Page 19 of 26
`
`

`

`5.765.027
`
`3
`from a host computer via a host interface; a transmitter for
`transmitting control signals and/or data to the host computer
`via the host interface; a circuit for receiving control signals
`and/or data from a network communication module via a
`network interface; a transmitter for transmitting control
`signals and/or data to the network communication module
`via the network interface; a circuit for receiving control
`signals and/or data from a local processor; a transmitter for
`transmitting control signals and/or data to the local proces
`sor; and a throttle circuit for enabling the local processor to
`have greater access to a memory within the controller than
`the host computer in response to a throttle signal.
`A method of enabling communication between a host
`computer having a desktop or a portable architecture and a
`local area network via a controller according to the present
`invention includes the steps of transmitting identi?cation
`data from a host computer via a host interface to a controller.
`the identi?cation data identifying the architecture of the host
`computer. and thereby con?guring the controller; writing
`data to be transmitted from the host computer onto a network
`to the controller; forwarding the data to be transmitted from
`the controller to a network communication module via a
`network interface; and transmitting the data to be transmit
`ted onto the network
`The foregoing and other features. aspects. and advantages
`of the present invention will become more apparent from the
`following detailed description when read in conjunction
`with the accompanying drawings.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`FIG. 1 provides a system level block diagram of the
`controller or card. including an ASIC/FPGA. a local
`processor. a host interface. an RF interface. an SRAM and
`a FLASH ROM.
`FIG. 2 provides a functional block diagram of the ASIC/
`FPGA according to the present invention.
`FIG. 3 provides a circuit schematic of the host decode
`circuit of the ASIC/FPGA according to the present inven
`tion.
`FIG. 4 provides a circuit schematic of the ?rst part of the
`mode register in the ASIC/FPGA according to the present
`invention.
`FIG. 5 provides a circuit schematic of the second part of
`the mode register used in the ASIC/FPGA according to the
`present invention.
`FIG. 6 provides a circuit schematic of the ?rst part of the
`timing control circuit and the bus request used in the
`ASIC/FPGA according to the present invention.
`FIG. 7 provides a circuit schematic of a ?rst part of the
`throttle circuit and a second part of the timing control circuit
`of the ASIC/FPGA according to the present invention.
`FIG. 8 provides a circuit schematic of a second part of the
`throttle circuit in the ASICIFPGA according to the present
`invention.
`FIG. 9 provides a circuit schematic of a second part of the
`address compare register and a third part of the throttle
`circuit used in the ASIC/FPGA according to the present
`invention.
`FIG. 10 provides a schematic of a ?rst part of the address
`compare register used in the ASIC/FPGA according to the
`present invention.
`FIG. 11 provides a schematic of the reset circuit used in
`the ASIC/FPGA according to the present invention.
`FIG. 12 provides a diagram of the PCMCIA/host interface
`signals.
`
`4
`FIG. 13 provides a diagram of the AT/host interface
`signals.
`FIG. 14 provides a diagram of the RF interface signals.
`FIG. 15 illustrates a method contemplated by embodi
`ments of the present invention.
`
`DEI‘ALED DESCRIPTION
`The data communication interface integrated circuit for a
`wireless local area network (LAN) controller and a wireless
`LAN controller according to the present invention will now
`be described with reference to the drawings.
`As illustrated in FIG. 1. a wireless local area network
`controller is shown as an adapter card 100 which can be for
`a desktop or a portable host computer. In the embodiments
`described below. adapter card 100 is particularly (though not
`exclusively) contemplated to be either a PCMCIA card or an
`AT card. having a number of components. The controller
`100 comprises an application-speci?c integrated circuit
`(ASIC)/?eld-programmable gate array (FPGA) 101. a local
`processor 102. a host interface 103. a radio frequency
`interface 104. a FLASH ROM 105. and an SRAM 106.
`These components comprise the network controller 100
`which enables a host computer 110 to interface with a
`wireless local area network. for example. a radio frequency
`local area network The host interface 103 interfaces with
`the host computer 110. The radio frequency (RF) interface
`104 interfaces with an RF communication module 120.
`The ASIC/FPGA 101 is designed to include all control
`glue circuits on the controller 100. The SRAM 106 is a
`read/write communication bu?er accessible by both the host
`and local processor. The FLASH ROM 105 is a progam
`memory accessible by both the host computer 110 and the
`local processor 102. Writing to the FLASH ROM 105 may
`only be accomplished during a special prog'am mode con
`trolled by a mode register within ASIC/FPGA 101; however.
`reading from the FLASH ROM 105 is allowed at any time
`by both the host 110 and the local processor 102.
`Brie?y. operation of the wireless local area network
`controller according to the present invention is as follows.
`When data is to be transmitted by a host computer 110 on to
`the network. the host computer 110 writes the transmit data
`to the SRAM 106 via host interface 103 and ASIC/FPGA
`101 and commands the local processor 102 via the ASIC/
`FPGA 101 to forward the transmitted data to the RF com
`munication module 120 via the RF interface 104. Under the
`control of the ASIC/FPGA 101. the local processor 102 then
`forwards the transmit data from the SRAM 106 through the
`local processor 102 to the RF interface 104 and then to the
`RF communication module 120. When data is received from
`the RF communication module 120. the local processor 102
`receives the data from the RF interface 104 and stores the
`received data in the SRAM 106. The local processor 102
`also generates an acknowledge signal which is transmitted
`onto the network by the RF communication module 120 via
`RF interface 104. The received data is then forwarded to the
`host computer 110 via the ASIC/FPGA 101.
`As a result. the ASIC/FPGA 101 enables communication
`between the host computer 110. the local processor 102. and
`the RF communication module 120. The ASIC/FPGA 101
`enables transmission of control signals between these three
`components and controls host computer 110 and local pro
`cessor 102 access to the SRAM 106 and the FLASH ROM
`105.
`The controller 100 according to the present invention
`includes both PCMCIA and AT form factors. When the
`controller 100 is coupled to a PCMCIA host computer 110.
`
`10
`
`25
`
`35
`
`45
`
`55
`
`65
`
`WESTERN DIGITAL CORPORATION, EXHIBIT 1019
`Page 20 of 26
`
`

`

`5.765.027
`
`5
`the controller 100 is referred to as a PCMCIA card. When
`the controller 100 is coupled to an AT host computer 110. the
`controller 100 is referred to as an AT card.
`
`According to one embodiment of the present invention.
`the PCMCIA card is designed to comply with the PCMCIA
`2.1 type 11 standard in a physical dimension of 85.6
`mmx54.0 mrn><5.0 mm This card is designed to work with
`a radio frequency communication module 120 which is
`connected through a 15-wire serial
`interface cable. One
`possible RF communication module 120 is a PCMCIA 915
`RF Modem manufactured by NCR Corporation of Dayton.
`Ohio. The PCMCIA card is also coupled to notebook
`computers through a standard 68-pin interface.
`According to another embodiment of the present
`invention. the AT card has the same functionality as the
`PCMCIA card except that the host interface is a standard
`16-bit ISA interface. The AT card may be coupled to an RF
`communication module 120. for example. an NCR WAVE-
`LANTM modern. through a 15-wire serial interface cable or
`through a 34-pin wire interface for 2.4 GHz.
`The components of the controller according to the present
`invention will now be described in detail.
`
`FIG. 2 provides a functional block diagram of the ASICI
`FPGA 101 shown in FIG. 1. The function block diagram
`shown in FIG. 2 is drawn to illustrate the host interface 103
`between the ASIC/FPGA 101 and host computer 110 on the
`left-hand side of the figure and the interface between the
`ASIC/FPGA 101 and the local processor 102. the memories
`(the SRAM 106 and FLASH ROM 105) and the RF interface
`104 on the right—hand side of the figure. As shown in FIG.
`2. the ASIC/FPGA 101 contains a control module 201 which
`converts memory access control signals from the host com-
`puter 110 format to the local processor 102 format. Bus
`request module 202 germ-ates bus arbitration handshaking
`signals when the host computer 110 is accessing the SRAM
`106 and/or FLASH ROM 105. Bus request module 202 also
`assigns higher priority to the local processor 102 in response
`to a throttle (THRTL) signal 203 generated by the address
`compare module 215. The throttle feature will be discussed
`in detail below.
`
`The control module 201 and bus request module 202 also
`include a timing control circuit which synchronizes access to
`the FLASH ROM 105 and SRAM 106 by the host 110 and
`the local processor 102. both of which ac