UNITED STATES PATENT AND TRADEMARK OFFICE
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`NIKON CORPORATION,
`Petitioner,
`
`v.
`
`ASML NETHERLANDS B.V.
`CARL ZEISS AG,
`Patent Owner.
`
`Patent No. 6,731,335
`
`
`Inter Partes Review No. IPR2018-00687
`
`
`PETITION FOR INTER PARTES REVIEW
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`UNDER 35 U.S.C. §§ 311-319 AND 37 C.F.R. § 42.100 ET SEQ.
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`Inter Partes Review of USP 6,731,335
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`TABLE OF CONTENTS
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`Page
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`I.  NOTICES AND STATEMENTS ...................................................................... 4 
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`II. 
`
`INTRODUCTION ............................................................................................. 5 
`
`III.  BACKGROUND OF THE TECHNOLOGY .................................................... 6 
`
`IV.  THE ’335 PATENT AND ITS PROSECUTION HISTORY ......................... 10 
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`A.  The ’335 Patent ........................................................................................ 10 
`
`B.  Prosecution History ................................................................................. 13 
`
`C.  Level of Ordinary Skill in the Art ........................................................... 14 
`
`V.  CLAIM CONSTRUCTION............................................................................. 15 
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`VI.  IDENTIFICATION OF CHALLENGE .......................................................... 17 
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`A.  Ground 1 – Obviousness of Claims 1-5, 7, 9, and 11 Based on Takahashi
` ................................................................................................................. 18 
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`1.  Background of Takahashi ............................................................... 18 
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`2.  Obviousness of Claims 1-5, 7, 9, and 11 ........................................ 23 
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`B.  Ground 2 – Obviousness of Claims 6, 8, 10, and 12 based on Takahashi
`and Gowda ............................................................................................... 40 
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`1.  Disclosure of Gowda ....................................................................... 40 
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`2.  Obviousness of Claims 6, 8, 10, and 12 .......................................... 41 
`
`C.  Ground 3 – Obviousness of Claims 1-5, 7, 9, and 11 based on Takahashi
`and Dickinson .......................................................................................... 44 
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`1.  Disclosure of Dickinson .................................................................. 44 
`
`2.  Obviousness of Claims 1-5, 7, 9, and 11 ........................................ 47 
`
`D.  Ground 4 – Obviousness of Claims 6, 8, 10, and 12 based on Takahashi,
`Dickinson, and Gowda ............................................................................ 49 
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`E.  Ground 5 – Obviousness of Claims 1-5, 7, 9, and 11 based on Matsunaga
` ................................................................................................................. 50 
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`1.  Background of Matsunaga .............................................................. 50 
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`2.  Obviousness of Claims 1-5, 7, 9, and 11 ........................................ 52 
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`A.  Ground 6 – Obviousness of Claims 6, 8, 10, and 12 based on Matsunaga
`and Gowda ............................................................................................... 63 
`
`B.  Ground 7 – Obviousness of Claims 1-5, 7, 9, and 11 Based on
`Matsunaga and Dickinson ....................................................................... 65 
`
`C.  Ground 8 – Obviousness of Claims 6, 8, 10 and 12 Based on Matsunaga
`with Dickinson and Gowda ..................................................................... 66 
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`VII.  CONCLUSION ................................................................................................ 67 
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`Inter Partes Review of USP 6,731,335
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`Appendix of Exhibits for Inter Partes Review of U.S. Patent No. 6,731,335
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`Exhibit Description
`U.S. Patent No. 6,731,335 to Kim et al [referenced as “’335 Patent” or,
`simply, “’335”]
`Declaration of Dr. Stuart Kleinfelder [referenced as “Kleinfelder”]
`Curriculum Vitae of Dr. Stuart Kleinfelder
`File History of U.S. Application No. 09/305/756 (“the ‘756 application,”
`which issued as the ’335 Patent) [referenced as “’335 File History”]
`U.S. Patent No. 6,107,655 to Guidash
`European Patent Application Publication No. EP0757476 to Takahashi
`U.S. Patent No. 6,115,066 to Gowda et al.
`European Patent Application Publication No. EP 0707417A2 to
`Dickinson
`U.S. Patent No. 7,113,213 to Matsunaga et al.
`File History of U.S. Application No. 09/022,339 (parent application of
`Matsunaga)
`
`Ex. #
`
`1001
`
`1002
`1003
`
`1004
`
`1005
`1006*
`1007*
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`1008*
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`1009*
`
`1010
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`*Prior art relied upon as grounds for unpatentability in this Petition.
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`Petitioner Nikon Corporation respectfully petitions for inter partes review of
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`Claims 1-12 of U.S. Patent No. 6,731,335 (“the ’335 Patent” (Ex. 1001)) in
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`accordance with 35 U.S.C. §§ 311-319 and 37 C.F.R. § 42.100 et seq.
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`I.
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`NOTICES AND STATEMENTS
`
`Pursuant to 37 C.F.R. § 42.8(b)(1), Petitioner Nikon Corporation as well as
`
`Sendai Nikon Corporation, Nikon Inc., and Nikon Americas Inc. are the real
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`parties-in-interest.
`
`Pursuant to 37 C.F.R. § 42.8(b)(2), Petitioner identifies the following related
`
`case in which the ’335 Patent is currently being asserted:
`
` Carl Zeiss AG and ASML Netherlands B.V. v. Nikon Corporation,
`
`Sendai Nikon Corporation, and Nikon Inc., Case No. Case No. 2:17-
`
`cv-03221 RGK (MRWx), filed September 26, 2017.
`
`Petitioner is a named Defendant in the above-identified pending case.
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`Pursuant to 37 C.F.R. § 42.8(b)(3), Petitioner identifies the following
`
`counsel (and a Power of Attorney accompanies this Petition):
`
`Lead Counsel
`David L. Fehrman
`dfehrman@mofo.com
`Registration No.: 28,600
`MORRISON & FOERSTER LLP
`707 Wilshire Blvd., Suite 6000
`Los Angeles, CA 90017-3543
`Tel: (213) 892-5601
`Fax: (213) 892-5454
`
`First Backup Counsel
`David T. Yang
`dyang@mofo.com
`Registration No. 44,415
`MORRISON & FOERSTER LLP
`707 Wilshire Blvd., Suite 6000
`Los Angeles, CA 90017-3543
`Tel: (213) 892-5587
`Fax: (213) 892-5454
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`Pursuant to 37 C.F.R. § 42.8(b)(4), service information for lead and backup
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`counsel is provided above. Petitioner consents to electronic service by email to
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`25888-ASML-IPR@mofo.com.
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`Pursuant to 37 C.F.R. § 42.104(a), Petitioner certifies that the ’335 Patent is
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`available for inter partes review and that Petitioner is not barred or estopped from
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`requesting an inter partes review challenging the patent claims on the grounds
`
`identified in this Petition. Petitioner was first served with a Complaint alleging
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`infringement of the ’335 Patent no earlier than September 28, 2017.
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`The entities identified in this Petition as “Patent Owners” (i.e., Carl Zeiss
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`AG and ASML Netherlands B.V.) are the two Plaintiffs in the above-referenced
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`district court case. These entities are the presumptive Patent Owners as they are
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`the Assignees on the most recently recorded assignment in the “Assignment
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`abstract of title” for the challenged patent according to the Patent Assignment
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`Search
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`database
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`on
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`the
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`USPTO
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`website
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`(https://assignment.uspto.gov/patent/index.html#/patent/search).
`
`II.
`
`INTRODUCTION
`
`This Petition presents several grounds that render obvious certain claims of
`
`the ’335 Patent. Section III of this Petition discusses the background of the
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`technology. Section IV summarizes the ’335 Patent and its prosecution history.
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`Section V concerns claim construction. Section VI sets forth the detailed grounds
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`for unpatentability in view of certain prior art. This showing is accompanied by
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`the Declaration of Dr. Stuart Kleinfelder (“Kleinfelder Decl.;” Ex. 1002).
`
`Petitioner respectfully requests a Decision to institute inter partes review of the
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`’335 Patent.
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`III. BACKGROUND OF THE TECHNOLOGY
`
`The ’335 Patent is directed to CMOS image sensor technology. In
`
`particular, the ’335 Patent is directed to a unit pixel of a CMOS image sensor and a
`
`method for operating the same.
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`FIG. 2 depicts admitted prior art unit pixels:
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`
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`FIG. 2 shows two adjacent unit pixels (100, 120) each respectively including
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`a single photodiode (101, 102), a transfer transistor (M21, M22) driven by control
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`signals (Tx1, Tx2), a sensing node (A, A2), a reset transistor (M11, M12) driven
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`by a reset signal (Rx1, Rx2), and a set of drive and select transistors (M31 and
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`M41, M32 and M42) for outputting data signals, the select transistors (M41 and
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`M42) being controlled by a select signal (Sx1, Sx2).
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`The ’335 Patent further discusses a known correlated double sampling
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`(“CDS”) operation of a unit pixel. (Ex. 1001 at 1:55-2:12.) As explained in the
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`’335 Patent, the CDS operation is described as follows: (i) a reset voltage level is
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`firstly sampled; (ii) next, a data voltage level, which is based on the reset voltage
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`level and an amount of photoelectrical charges transferred from a photodiode, is
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`sampled; and (iii) any offset is removed by subtracting the reset voltage level from
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`the data voltage level. FIG. 3 illustrates the timing operations of the prior-art unit
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`pixel (100) shown in FIG. 2, which performs the CDS operation to obtain a net
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`image data value. (Id. at 1:55-56, 2:1-12.)
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`(emphasis added)
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`As shown in FIG. 3 and also described at 2:13-58, it was known to fully
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`deplete photodiode (101) during time period A, when the transfer transistor (M21)
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`and reset transistor (M11) are turned on and the select transistor (M41) is turned
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`off. (Ex. 1001 at 2:17-20.) Before a CMOS image sensor captures an image, it is
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`desirable that any remaining charges on the photodiodes be depleted from the
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`photodiodes. The remaining charges on the photodiodes would be (a) any
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`remaining photoelectric charges generated/integrated when a previous image was
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`taken, and (b) any charges caused by dark current and the like that tend to be
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`naturally generated in the photodiodes. (See Kleinfelder Decl., Ex 1002 at ¶ 15.)
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`Thereafter, during time period B, the photodiode (101) receives light and
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`generates/integrates photoelectric charges. (Ex. 1001 at 2:21-27.) Time periods C,
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`D, and E correspond to the aforementioned CDS operation (i). Time periods F, G,
`
`and H correspond to the aforementioned CDS operation (ii). During time period
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`C, the reset voltage (Vdd) is applied to the sensing node (A) via the reset transistor
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`(M11). During time period D, the reset voltage level at the sensing node (A) is
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`settled after the reset transistor (M11) is turned off. Then, during time period E, as
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`indicated in the red circle above, the settled reset voltage level at the sensing node
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`A is sampled via the drive transistor (M31) and the select transistor (M41). (Id. at
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`2:28-39.) During time period F, the photoelectric charges generated/integrated on
`
`the photodiode (101) in response to light are transferred to the sensing node (A) via
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`the transfer transistor (M21). At the sensing node (A), the reset voltage level is
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`varied depending on the amount of the photoelectric charges transferred from the
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`photodiode (101). As the result, the data voltage level is generated at the sensing
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`node (A) based on the reset voltage level and the amount of the photoelectric
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`charges transferred from the photodiode (101). During time period G, the data
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`voltage level is settled where the reset transistor (M11) and the transfer transistor
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`(M21) are turned off. Then, during time period H, as indicated in the blue circle
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`above, the settled data voltage level at the sensing node (A) is sampled via the
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`drive transistor (M31) and the select transistor (M41). (Ex. 1001 at 2:40-55; see
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`also Kleinfelder Decl., Ex 1002 at ¶ 15.)
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`The ’335 Patent further indicates that it was known that the sampled reset
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`and data voltage levels can be converted from analog to digital signals and the
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`difference provided as an output image value. (Ex. 1001. at 2:52-55, FIG. 1 (A/D
`
`converter 30).)
`
`IV. THE ’335 PATENT AND ITS PROSECUTION HISTORY
`
`A.
`
`The ’335 Patent
`
`The ’335 Patent concerns a specific unit pixel structure that is an alleged
`
`improvement over the admitted prior art of FIG. 2. FIG. 4 shows an exemplary
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`embodiment:
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`
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`FIG. 4 differs from the prior art in FIG. 2 in that two photodiodes (401, 402)
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`and respectively coupled transfer transistors (M43, M44) share a single sensing
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`node (A) and one set of reset, drive, and select transistors (M1, M3, M4,
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`respectively) for outputting reset and data voltage levels. It is stated at 4:60-61 that
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`“a unit pixel (400) may have the same effect as two unit pixels according to the
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`prior art.”
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`FIG. 5 shows a timing operation of the structure of FIG. 4:
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`
`
`(emphasis added)
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`As shown in FIG. 5, the timing operation of the unit pixel of FIG. 4 is a logical
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`extension of the conventional reading out operation, including the CDS operations
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`(i) and (ii) shown in Fig. 3. In particular, steps A-H of FIG. 3 that are described
`
`with respect to unit pixel (101) of FIG. 2 are duplicated for each of the two
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`photodiodes (401, 402) one at a time. In other words, the circuitry associated with
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`photodiode (401) is cycled through steps A1-H1. Next, the circuitry associated with
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`photodiode (402) is cycled through steps A2-H2. (Ex. 1001 at 5:25-6:42.) That is,
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`according to FIG. 5, first photodiode (401) is fully depleted during period A1.
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`Next, photodiode (401) generates and integrates photoelectric charges during
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`period B1. Then, during period E1, as indicated in the red circle above, a settled
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`reset voltage level is sampled. This operation corresponds to the CDS operation (i).
`
`Finally, during period H1, as indicated in the blue circle above, a settled data
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`voltage level derived from the amount of the photoelectric charges transferred from
`
`the photodiode (401) is sampled. This operation corresponds to the CDS operation
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`(ii). Similarly, photodiode (402) is fully depleted during period A2. Next,
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`photodiode (402) generates and integrates photoelectric charges during period B2.
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`Then, during period E2, as indicated in the red circle above, a settled reset voltage
`
`level is sampled. This operation corresponds to the CDS operation (i). Finally,
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`during period H2, as indicated in the blue circle above, a settled data level derived
`
`from the amount of the photoelectric charges transferred from the photodiode (402)
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`is sampled. This operation corresponds to the CDS operation (ii). (See also
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`Kleinfelder Decl., Ex 1002 at ¶¶ 17-23.)
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`Referencing FIG. 3 and FIG. 5, steps (A) through (E) of the admitted prior
`
`art correspond to the following time periods set forth in FIG. 5:
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`Time Periods from
`FIG. 3 (Admitted
`Prior Art)
`A
`B
`C
`D
`E 
`
`Corresponding Time
`Periods from FIG. 5
`A1 (A2)
`B1 (B2)
`C1 (C2)
`D1 (D2)
`E1 (E2) 
`
`F
`
`G 
`H 
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`
`
`F1 (F1)
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`G1 (G2)
`H1 (H2)
`
`Reading Out Operation
`of Unit Pixel
`PD-reset
`Generate/integrate charge on
`PD
`Sensing node-Reset
`Settle reset voltage level
`Sample settled reset voltage
`level
`Transfer photoelectric
`charges from PD to sensing
`node
`Settle data voltage level
`Sample settled voltage level
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`As mentioned above, the timing operation of the unit pixel (400) of FIG. 4 is
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`simply a logical extension of the conventional reading out operation shown in FIG.
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`3. (Kleinfelder Decl., Ex 1002 at ¶ 24.)
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`B.
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`Prosecution History
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`The ’756 Application (Exhibit 1003) was filed on May 6, 1999, and included
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`27 application claims, of which claims 1-15 were apparatus claims and 16-27 were
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`method claims. (Ex. 1003 at 17-26.) In an Office Action mailed on May 22, 2003,
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`the Examiner rejected all of the claims under either 35 U.S.C. §102 or §103. (See
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`Ex. 1004 at 105.) Specifically, application claims 1, 2, 7-9, and 12-15 were
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`rejected under §102(e) as being anticipated by U.S. Patent No. 6,107,655 to
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`Guidash (Exhibit 1005). The Examiner also rejected application claims 3-6, 10,
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`11, and 16-27 under §103(a) as being unpatentable over Guidash. (Id. at 106-25.)
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`The Applicants filed an amendment on October 21, 2003, which cancelled all of
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`the apparatus claims (1-15) and amended method claims 16-18 and 26. (Id. at 130-
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`8.) As a result of the amendment, the ’756 Application no longer included any
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`apparatus claims, but only method claims for driving a unit pixel having first and
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`second photodiodes.
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`It should be noted that, in the Remarks section, the Applicants did not
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`distinguish
`
`the structure disclosed
`
`in Guidash.
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` Rather,
`
`the Applicants
`
`distinguished Guidash only by arguing that Guidash did not disclose that “the reset
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`transistor is turned off and then the first transfer transistor is turned on while the
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`reset transistor remains off” and that “the reset transistor is turned off and the
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`second transfer transistor is turned on while the reset transistor remains off” as
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`recited in amended application claim 16 (which later became claim 1 of the ’335
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`Patent). (Id. at 136-37.)
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`A Notice of Allowance issued on January 13, 2004, in which then-pending
`
`claims 16-27 were allowed. (Id. at 140-42.)
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`C.
`
`Level of Ordinary Skill in the Art
`
`As discussed in the expert Declaration of Dr. Kleinfelder, Petitioner
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`contends that one of ordinary skill in the art of the ’335 Patent at the time of the
`
`claimed invention would have had a bachelor’s degree in electrical engineering
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`with approximately four years of relevant experience image sensors, or a Masters
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`degree in electrical engineering or related field with at least two years of relevant
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`experience. (Kleinfelder Decl., Ex 1002 at ¶ 10.)
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`V. CLAIM CONSTRUCTION
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`During inter partes review, claims of an unexpired patent are to be given
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`their “broadest reasonable construction” consistent with the specification. See 37
`
`C.F.R. § 42.100(b); Cuozzo Speed Techs., LLC v. Lee, 136 S. Ct. 2131, 2144-45
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`(2016).1 The terms of the challenged claims of the ’335 Patent should be accorded
`
`their broadest reasonable interpretation as understood by one of ordinary skill in
`
`the art and consistent with the disclosure.
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`An understanding of the claims as a whole is necessary. See, e.g.,
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`Hockerson-Halberstadt, Inc. v. Converse Inc., 183 F.3d 1369, 1374 (Fed. Cir.
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`1999) (proper claim construction “demands interpretation of the entire claim in
`
`context, not a single element in isolation”).
`
`Claim 1 of the ’335 Patent includes an extensive preamble setting forth a
`
`particular structure including first and second photodiodes, followed by steps (a)-
`
`(f), a number of which include plural actions. These steps correspond to certain
`
`operational time periods described in connection with FIG. 5 and at 5:25-6:42, and
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`dependent claims 2-12 correspond to other operations described there.
`
`1 The “broadest reasonable construction” standard applies in this IPR proceeding, but claim
`construction before the district court may differ, as the standards differ.
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` Specifically, referencing FIG. 5 and 5:25-6:42, steps (a) through (f) of
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`claim 1 correspond to the following time periods set forth in FIG. 5:
`
`Claim 1
`Step
`
`Corresponding
`Time
`Periods From FIG.
`5
`A1 and A2
`B1 and B2
`C1
`F1
`C2
`F2
`Thus, the recited steps in claim 1 correspond to time periods A, B, C, and F
`
`(a)
`(b)
`(c)
`(d)
`(e)
`(f)
`
`for driving each photodiode in the unit pixel. In other words, time periods A1, B1,
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`C1, and F1 concern photodiode (401), while time period A2, B2, C2, and F2 concern
`
`photodiode (402). The operations of (i) firstly sampling the reset voltage level and
`
`then (ii) sampling the data voltage level are set forth in steps (c) and (d) for the first
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`photodiode (401) and steps (e) and (f) for the second photodiode (402).
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`Dependent claims 2 and 4 relate to time period B for the first and second
`
`photodiodes (401, 402), respectively, and recite further operations that are
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`described in the specification as taking place during those time periods.
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`Dependent claims 5 and 9 relate to time periods D and E for the first and
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`second photodiodes (401, 402), respectively, in which the reset voltage level is
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`settled and sampled. Id.
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`Dependent claims 7 and 11 relate to time periods G and H for the first and
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`second photodiodes (401, 402), respectively, in which the data voltage level is
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`settled and sampled.
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`VI.
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`IDENTIFICATION OF CHALLENGE
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`Pursuant
`
`to 37 C.F.R. § 42.104(b), Petitioner respectfully requests
`
`cancellation of Claims 1-12 of the ’335 Patent based on the grounds of invalidity
`
`set forth below. All the statutory citations are pre-AIA.
`
`Ground 1 – Obviousness under 35 U.S.C. § 103(a) of Claims 1-5, 7, 9, and
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`11 based on EP0757476 (“Takahashi,” Ex. 1006).
`
`Ground 2 – Obviousness under 35 U.S.C. § 103(a) of Claims 6, 8, 10, and
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`12 based on Takahashi in combination with U.S. Patent No.
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`6,115,066 (“Gowda,” Ex. 1007).
`
`Ground 3 – Obviousness under 35 U.S.C. § 103(a) of Claims 1-5, 7, 9, and
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`11 based on Takahashi and European Application No. 0707417
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`(“Dickinson,” Ex. 1008).
`
`Ground 4 – Obviousness under 35 U.S.C. § 103(a) of Claims 6, 8, 10, and
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`12 based on Takahashi in combination with Dickinson and
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`Gowda.
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`Ground 5 – Obviousness under 35 U.S.C. § 103(a) of Claims 1-5, 7, 9, and
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`11 based on U.S. Patent No. 7,113,213 (“Matsunaga,” Ex.
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`1009).
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`Ground 6 – Obviousness of under 35 U.S.C. § 103(a) of Claims 6, 8, 10,
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`and 12 based on Matsunaga in combination with Gowda.
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`Ground 7 – Obviousness under 35 U.S.C. § 103(a) of Claims 1-5, 7, 9, and
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`11 based on Matsunaga and Dickinson.
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`Ground 8 – Obviousness of under 35 U.S.C. § 103(a) of Claims 6, 8, 10,
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`and 12 based on Matsunaga in combination with Dickinson and
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`Gowda.
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`Below is a discussion of how the claims are unpatentable under the statutory
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`grounds raised, including claim charts specifying where each element of a
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`challenged claim is met by the prior art. 37 C.F.R. § 42.104(b)(4). The showing in
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`the ensuing sections establishes a reasonable likelihood of prevailing as to each
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`ground of invalidity with respect to the challenged claims as to that ground. This
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`showing is accompanied by the Declaration of Dr. Stuart Kleinfelder (Ex. 1002).
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`A. Ground 1 – Obviousness of Claims 1-5, 7, 9, and 11 Based on
`Takahashi
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`1.
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`Background of Takahashi
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`Takahashi published on May 2, 1997. Takahashi is prior art to the ’335
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`Patent under at least 35 U.S.C. § 102(b).
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`Takahashi discloses several embodiments of a CMOS image sensor,
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`schematically illustrated in FIGS. 1, 5, 7, and 8.
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`For example, FIG. 1 of Takahashi discloses one embodiment of an image
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`sensor having unit pixels.
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`(emphasis added)
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`
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`As indicated in the red box above, FIG. 1 discloses a “unit pixel” that
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`includes two photoelectric converters (the combinations of 1 and 2 that make up a
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`photo gate). Each photoelectric converter is (1) respectively coupled to a transfer
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`transistor (3) that connects to a single sensing node, which is in turn connected to
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`the source of a single reset transistor (4), and the gate of a single drive transistor
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`(5), which is in turn connected to a single select transistor (6). (See Ex. 1006 at
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`4:21-35.) The two transfer transistors (3) are controlled by control signals TXo0
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`and TXe0, respectively, and the reset transistor (4) is controlled by control signal
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`R0. (See id. at 4:52-5:23.) FIG. 3 of Takahashi illustrates a timing chart for FIG.
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`1:
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`(emphasis added)
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`FIG. 3 shows the timing signals of ΦS0 for controlling (turning on and
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`turning off) the select transistor (5), ΦR0 for controlling the reset transistor (4), and
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`ΦTo0 and ΦTe0 for controlling the first and second transfer transistors (3),
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`respectively. As indicated in the red and blue circles above, ΦTN and ΦTS are
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`control pulses for the CDS operation to sample (i) the reset voltage level and (ii)
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`the data voltage level, respectively. (See Ex. 1006 at 4:59 to 5:53.) The CDS
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`operation is performed successively for each photoelectric converter (1).
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`FIG. 8 of Takahashi shows another embodiment of an active unit pixel:
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`(emphasis added)
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`The unit pixel shown in FIG. 8 is identical to the unit pixel shown in FIG. 1
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`with the exception that PN photodiodes (24) are substituted for the photo gate
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`structure (1 and 2) of FIG. 1. (See Id. at 9:30-41.) The photo gate (1 and 2) has
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`the same function as that of the PN photodiode 24 in that both the photo gate and
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`the photodiode generate and integrate photoelectric charges in response to light
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`received and are then read out. (See Kleinfelder Decl., Ex 1002 at ¶ 44.)
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`2.
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`Obviousness of Claims 1-5, 7, 9, and 11
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`As detailed in the claim charts below, Takahashi discloses every element of
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`the claims, except for the initial step of fully depleting the photodiodes. However,
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`it would have been obvious to one of ordinary skill in the art to fully deplete the
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`photodiodes in order to eliminate any residual charges on the photodiode prior to
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`capturing an image. (See Kleinfelder Decl., Ex 1002 at ¶¶ 72-73.) Indeed, such is
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`consistent with the discussion of the prior art in the ’335 Patent itself, which
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`describes full depletion prior to image capture as being known in conventional
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`CMOS image sensors. One of skill in the art would recognize that the quality of
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`the output signal would be negatively impacted if the photodiode had residual
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`charges prior to performing image capture and that it would therefore be beneficial
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`to fully deplete the photodiode before taking an image. (Id.)
`
`The claim charts below specify where each claim element of Claims 1-5, 7,
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`9, and 11 is either disclosed by or obvious in view of Takahashi. The obviousness
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`discussions follow the claim charts.
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`Disclosure in Takahashi (Ex. 1006)
`Takahashi discloses a method for driving a unit pixel
`of a CMOS image sensor. (See Abstract.) FIG. 1
`discloses a “unit pixel” as claimed:
`
`
`
`
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`As shown in a portion of FIG. 1 (along with
`corresponding descriptions in the specification at
`4:21-35), Takahashi discloses:
`
` a
`
` first photoelectric converting unit (upper 1) for
`receiving light (shown as Hѵ in Fig. 2) that causes
`photoelectric charges to be generated and integrated;
`(See 4:21-24; Fig. 2.)
`
`
` a
`
` first transfer transistor (upper 3) coupled between
`the first photoelectric converting unit 1 and a single
`sensing node (the conjunction of plural transistors 3,
`4 and 5, i.e. connected to the gate of transistor 5,
`labeled as 21 in the upper left unit in FIG. 1), for
`transferring the photoelectric charges generated in
`the first photodiode to the single sensing node, in
`response to a first control signal ΦTX0;
`
`Claim of USP 6,731,335
`1. A method for driving a
`unit pixel which
`comprises
`
`
`
`
`
`
`
`
`
`
`
`
`
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`
`
`
`
`
`
`
` a
`
` first photodiode for
`receiving light from an
`object and for generating
`and integrating
`photoelectric charges;
`
` a
`
` first transfer transistor
`coupled between the first
`photodiode and a single
`sensing node, for
`transferring the
`photoelectric charges
`generated in the first
`photodiode to the single
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` a
`
` second photoelectric converting unit (lower 1) for
`receiving light (shown as Hѵ in Fig. 2) from the
`object and for generating and integrating
`photoelectric charges;
`
`
` a
`
` second transfer transistor (lower 3) coupled
`between the second photodiode 1 and the single
`sensing node for transferring the photoelectric
`charges generated in the second photodiode to the
`single sensing node, in response to a second control
`signal ΦTXe;
`
`
`
`
`
`
` a
`
` reset transistor 4 coupled between a power supply
`“VDD” and the single sensing node (the conjunction
`circuitry connected to the gate of transistor 5), for
`outputting the photoelectric charges stored in the
`single sensing node, in the response to a third control
`signal ΦR;
`
`
`
`
` a
`
` drive transistor 5 coupled to the power supply
`“VDD” for acting as a source follower in response to
`an output of the single sensing node (the conjunction
`circuitry connected to the gate of transistor 5); and
`
`
`
` a
`
` select transistor 6 coupled to the drive transistor 5,
`for outputting an image data driven by the drive
`25
`
`sensing node, in response
`to a first control signal;
`
`
` a
`
` second photodiode for
`receiving light from the
`object and for generating
`and integrating
`photoelectric charges;
`
` a
`
` second transfer
`transistor coupled
`between the second
`photodiode and the single
`sensing node, for
`transferring the
`photoelectric charges
`generating in the second
`photodiode to the single
`sensing node, in response
`to a second control signal;
`
` a
`
` reset transistor coupled
`between a power supply
`and the single sensing
`node, for outputting the
`photoelectric charges
`stored in the single
`sensing node, in the
`response to a third control
`signal;
`
` a
`
` drive transistor coupled
`to the power supply, for
`acting as a source
`follower in response to an
`output of the single
`sensing node; and
`
` a
`
` select transistor coupled
`to the drive transistor, for
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`outputting an image data
`driven by the drive
`transistor in response to
`address signals, the
`method comprising the
`steps of:
`
`transistor in response to address signals ΦS, the
`address signals being generated by the “vertical
`scanning circuit”
`
`
`
`
`Fig. 8 of Takahashi shows an identical structure as
`FIG. 1, but substitutes a PN photodiode 24 in place
`of a photo gate (the photo gate being the
`combination of 1 and 2 shown in FIG. 1). (See 9:30-
`41.)
`
`
`(a) fully depleting the
`first and second
`photodiodes;
`
`(b) receiving light in the
`first and second
`photodiodes and
`generating photoelectric
`charges;
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`
`
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`It would have been obvious to one of ordinary skill
`in the art to fully deplete the first and second
`photodiodes prior to image capture in order to
`eliminate any residual charges on the photodiodes.
`(See Kleinfelder Decl., Ex 1002 at ¶ 72.)
`
`Figs. 2, 9, and 10 each show receiving light (shown
`as hѵ) in the photodiodes; it is understood that
`photoelectric charges are generated when light is
`received at a photodiode. (See id. ¶ 44.)
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`(c) turning on the reset
`transistor, turning off the
`first and second transfer
`transistors and turning on
`a selector transistor, and
`outputting a reset voltage
`level through the single
`sensing node, the drive
`transistor and the select
`transistor;
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`Takahashi discloses step (c) at time T0 of FIG. 3:
`
`During time T0, the reset transistor ΦR and select
`transistor ΦS are both on, and transfer transistors
`ΦTXo0 and ΦTXe0 are off. The floating diffusion
`single sensing node (conjunction of transistors 3, 4,
`and 5 as shown in FIG. 1) is reset while selected for
`readout. (See also 4:58-5:11.)
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`(emphasis added)
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