Trials@uspto.gov
`571-272-7822
`
`
`Paper No. 7
`Entered: August 28, 2018
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`NIKON CORPORATION,
`Petitioner,
`
`v.
`
`ASML NETHERLANDS B.V.
`CARL ZEISS AG,
`Patent Owner.
`____________
`
`Case IPR2018-00687
`Patent 6,731,335 B1
`____________
`
`
`Before JEFFREY S. SMITH, DAVID C. MCKONE, and
`KEVIN W. CHERRY, Administrative Patent Judges.
`
`MCKONE, Administrative Patent Judge.
`
`
`
`
`DECISION
`Institution of Inter Partes Review
`37 C.F.R. § 42.108
`
`
`
`
`
`
`571-272-7822
`
`
`Paper No. 7
`Entered: August 28, 2018
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`NIKON CORPORATION,
`Petitioner,
`
`v.
`
`ASML NETHERLANDS B.V.
`CARL ZEISS AG,
`Patent Owner.
`____________
`
`Case IPR2018-00687
`Patent 6,731,335 B1
`____________
`
`
`Before JEFFREY S. SMITH, DAVID C. MCKONE, and
`KEVIN W. CHERRY, Administrative Patent Judges.
`
`MCKONE, Administrative Patent Judge.
`
`
`
`
`DECISION
`Institution of Inter Partes Review
`37 C.F.R. § 42.108
`
`
`
`
`
`
`
`IPR2018-00687
`Patent 6,731,335 B1
`
`
`I. INTRODUCTION
`
`A. Background
`Nikon Corporation (“Petitioner”) filed a Petition (Paper 2, “Pet.”) to
`institute an inter partes review of claims 1–12 of U.S. Patent No. 6,731,335
`B1 (Ex. 1001, “the ’335 patent”). Petitioner indicates that Sendai Nikon
`Corporation, Nikon Inc., and Nikon Americas Inc. are real parties in interest.
`Pet. 4. Carl Zeiss AG and ASML Netherlands B.V. (collectively, “Patent
`Owner”) filed a Preliminary Response (Paper 6, “Prelim. Resp.”). Upon
`consideration of the Petition and Preliminary Response, we conclude, under
`35 U.S.C. § 314(a), that Petitioner has established a reasonable likelihood
`that it would prevail with respect to at least one challenged claim.
`Accordingly, we institute an inter partes review of claims 1–12 of the ’335
`patent.
`
`B. Related Matter
`The parties indicate that the ’335 patent has been asserted in Carl
`Zeiss AG v. Nikon Corp., Case No. Case No. 2:17-cv-03221 RGK (MRWx).
`Pet. 4; Paper 4, 2.
`
`
`C. Evidence Relied Upon
`Petitioner relies on the following prior art:
`Ex. 1006 (“Takahashi”) EP 0 757 476 A2
`Ex. 1007 (“Gowda”)
`US 6,115,066
`Ex. 1008 (“Dickinson”) EP 0 707 417 A2
`Ex. 1009 (“Matsunaga”) US 7,113,213 B2
`
`
`
`
`
`
`Feb. 5, 1997
`Sept. 5, 2000
`Apr. 17, 1996
`Sept. 26, 2006
`
`2
`
`
`
`IPR2018-00687
`Patent 6,731,335 B1
`
`Petitioner also relies on the Declaration of Stuart Kleinfelder, Ph.D.
`
`(Ex. 1002, “Kleinfelder Decl.”).
`
`
`D. The Asserted Grounds
`Petitioner asserts the following grounds of unpatentability (Pet. 17–
`
`18):
`
`Reference(s)
`Takahashi
`
`Takahashi and Gowda
`
`Takahashi and Dickinson
`Takahashi, Dickinson, and
`Gowda
`Matsunaga
`
`Matsunaga and Gowda
`
`Basis
`§ 103(a)
`
`Claims Challenged
`1–5, 7, 9, and 11
`
`§ 103(a)
`
`§ 103(a)
`
`§ 103(a)
`
`§ 103(a)
`
`§ 103(a)
`
`6, 8, 10, and 12
`
`1–5, 7, 9, and 11
`
`6, 8, 10, and 12
`
`1–5, 7, 9, and 11
`
`6, 8, 10, and 12
`
`1–5, 7, 9, and 11
`
`6, 8, 10, and 12
`
`Matsunaga and Dickinson
`Matsunaga, Dickinson, and
`Gowda
`
`E. The ’335 Patent
`The ’335 patent describes a complementary metal oxide
`semiconductor (CMOS) image sensor including a unit pixel. Ex. 1001,
`Abstract. A unit pixel is illustrated in Figure 4, reproduced below:
`
`§ 103(a)
`
`§ 103(a)
`
`3
`
`
`
`IPR2018-00687
`Patent 6,731,335 B1
`
`
`Figure 4 is a circuit diagram of a unit pixel. Id. at 4:50–51.
`Unit pixel 400 includes two photodiodes 401, 402 connected to
`transfer transistors M43 and M44, respectively. Id. at 4:60–67. The
`photodiodes receive light from an object and generate and integrate
`photoelectric charges. Id. at 5:2–4, 5:9–11. Transfer transistor M43, M44
`
`
`
`4
`
`
`
`IPR2018-00687
`Patent 6,731,335 B1
`
`transfer the generated charges to single sensing node A in response to
`control signals Tx1 and Tx2, respectively. Id. at 5:4–8, 5:11–15. The
`photodiodes share reset transistor M1, drive transistor M3, and select
`transistor M4. Id. at 4:67–5:2. Reset transistor Ml is coupled between
`power supply Vdd and single sensing node A and outputs the photoelectric
`charges on single sensing node A in response to control signal Rx. Id. at
`5:16–19. Drive transistor M3 is coupled to power supply Vdd and acts as a
`source follower in response to an output of single sensing node A. Id. at
`5:19–22. Select transistor M4 outputs image data in response to a control
`signal Sx, which is produced by address signals. Id. at 5:22–24.
`The operation of unit pixel 400 is shown in Figure 5, reproduced
`below:
`
`5
`
`
`
`IPR2018-00687
`Patent 6,731,335 B1
`
`
`Figure 5 is a timing chart illustrating control signals to control transistors in
`unit pixel 400. Id. at 4:52–53, 5:25–26.
`In sections A1 and A2, transfer transistors M43, M44, respectively,
`are turned on and select transistor M4 is turned off, so that photodiodes 401,
`402, respectively, are fully depleted. Id. at 5:29–33, 5:41–46. In sections
`
`
`
`6
`
`
`
`IPR2018-00687
`Patent 6,731,335 B1
`
`B1 and B2, transistors M43, M44, respectively, are turned off and
`photodiodes 401, 402, respectively, generate and integrate photoelectric
`charges. Id. at 5:35–40, 5:47–53. In section C1, reset transistor M1 and
`select transistor M4 are turned on and transfer transistors M43, M44 are
`turned off such that a reset voltage level is outputted through select transistor
`M44 and drive transistor M3 is driven by sensing node A. Id. at 5:54–59. In
`section D1, reset transistor M1 is turned off to settle the voltage and in
`section E1, the reset voltage is sampled. Id. at 5:61–65. In section F1,
`transfer transistor M43 is turned on and integrated photoelectric charges
`from photodiode 401 are transferred to the output terminal through sensing
`node A, drive transistor M3, and select transistor M4. Id.at 5:66–6:6. In
`section G1, transfer transistor M43 is turned off to settle the voltage and in
`section H1, data voltage level is sampled. Id. at 6:7–11. In sections C2–H2,
`sections C1–H1 are repeated for photodiode 402 and transfer transistor M44.
`Id. at 6:12–36.
`The sampled reset and data voltages are output to an analog to digital
`converter (ADC) and the difference between the reset and data digital
`signals becomes an output image value. Id. at 6:52–65.
`Claim 1, reproduced below, is illustrative of the invention:
`1.
`A method for driving a unit pixel which comprises
`a first photodiode for receiving light from an object and for
`generating and integrating photoelectric charges; a first transfer
`transistor coupled between the first photodiode and a single
`sensing node, for transferring the photoelectric charges
`generated in the first photodiode to the single sensing node, in
`response to a first control signal; a second photodiode for
`receiving light from the object and for generating and
`integrating photoelectric charges; a second transfer transistor
`coupled between the second photodiode and the single sensing
`
`7
`
`
`
`IPR2018-00687
`Patent 6,731,335 B1
`
`
`node, for transferring the photoelectric charges generating in
`the second photodiode to the single sensing node, in response to
`a second control signal; a reset transistor coupled between a
`power supply and the single sensing node, for outputting the
`photoelectric charges stored in the single sensing node, in the
`response to a third control signal; a drive transistor coupled to
`the power supply, for acting as a source follower in response to
`an output of the single sensing node; and a select transistor
`coupled to the drive transistor, for outputting an image data
`driven by the drive transistor in response to address signals, the
`method comprising the steps of:
`(a) fully depleting the first and second photodiodes;
`(b) receiving light in the first and second photodiodes and
`generating photoelectric charges;
`(c) turning on the reset transistor, turning off the first and
`second transfer transistors and turning on a
`selector transistor, and outputting a reset voltage
`level through the single sensing node, the drive
`transistor and the select transistor;
`(d) turning off the reset transistor and then turning on the
`first transfer transistor with said reset transistor
`remaining off, and outputting a data voltage level
`of the photoelectric charges generated in the first
`photodiode through the single sensing node, the
`drive transistor and the select transistor;
`(e) turning on the reset transistor, turning off the first
`transfer transistor and outputting the reset voltage
`level through the single sensing node, the drive
`transistor and the select transistor; and
`(f) turning off the reset transistor and then turning on the
`second transfer transistor with said reset transistor
`remaining off, and outputting a data voltage level
`of the photoelectric charges generated in the
`second photodiode through the single sensing
`node, the drive transistor and the select transistor.
`
`8
`
`
`
`IPR2018-00687
`Patent 6,731,335 B1
`
`
`II. ANALYSIS
`Claim Construction
`A.
`We interpret claims of an unexpired patent using the broadest
`reasonable construction in light of the specification of the patent in which
`they appear. See 37 C.F.R. § 42.100(b); Cuozzo Speed Techs., LLC v. Lee,
`136 S. Ct. 2131, 2144–45 (2016). “Under a broadest reasonable
`interpretation, words of the claim must be given their plain meaning, unless
`such meaning is inconsistent with the specification and prosecution history.”
`Trivascular, Inc. v. Samuels, 812 F.3d 1056, 1062 (Fed. Cir. 2016). Neither
`party raises a disputed issue of claim construction that we must address at
`this stage of the proceeding.
`
`B. Asserted Grounds of Unpatentability
`A claim is unpatentable under 35 U.S.C. § 103(a) if the differences
`between the claimed subject matter and the prior art are “such that the
`subject matter as a whole would have been obvious at the time the invention
`was made to a person having ordinary skill in the art to which said subject
`matter pertains.” We resolve the question of obviousness on the basis of
`underlying factual determinations, including: (1) the scope and content of
`the prior art; (2) any differences between the claimed subject matter and the
`prior art; (3) the level of skill in the art; and (4) objective evidence of
`nonobviousness, i.e., secondary considerations.1 See Graham v. John Deere
`Co., 383 U.S. 1, 17–18 (1966).
`
`
`1 The current record does not include allegations or evidence of objective
`indicia of nonobviousness.
`
`9
`
`
`
`IPR2018-00687
`Patent 6,731,335 B1
`
`
`1. Level of Ordinary Skill
`Citing to Dr. Kleinfelder’s testimony, Petitioner contends that a
`skilled artisan would have had a Bachelor’s degree in electrical engineering
`and approximately four years of relevant experience with image sensors, or,
`alternatively, a Master’s degree in electrical engineering or related field with
`at least two years of relevant experience with image sensors. Pet. 14–15
`(citing Ex. 1002 ¶ 10). Patent Owner does not contest Petitioner’s proposal
`or provide a proposal of its own. We credit Dr. Kleinfelder’s testimony and,
`on the current record, adopt Petitioner’s proposed level of ordinary skill.
`
`
`2. Alleged Obviousness of Claims 1–5, 7, 9, and 11 over
`Takahashi
`Petitioner contends that claims 1–5, 7, 9, and 11 would have been
`obvious over Takahashi. Pet. 23–39. For the reasons given below,
`Petitioner has demonstrated a reasonable likelihood that it would prevail on
`this ground.
`
`
`a. Scope and Content of the Prior Art—Overview of
`Takahashi
`Takahashi describes a CMOS solid-state image pickup apparatus.
`Ex. 1006, 1:7–10. Figures 1 and 8 depict example circuit diagrams of
`similar embodiments. We focus primarily on the embodiment of Figure 8,
`reproduced below, although we discuss Figure 1 for components that overlap
`the two embodiments.
`
`10
`
`
`
`IPR2018-00687
`Patent 6,731,335 B1
`
`
`
`Figure 8 is a schematic circuit constructional diagram of a photoelectric
`converting device. Id. at 3:55–57. We note that most of the features of
`Figure 8 are described with respect to Figure 1. Figure 1 shows a similar
`
`11
`
`
`
`IPR2018-00687
`Patent 6,731,335 B1
`
`circuit that uses photo gate 2 to convert light to photoelectric charge. Id. at
`4:21–24, 5:17–20. “The embodiment [of Figure 8] is characterized in that
`no photo gate is used in the photoelectric converting unit but a pn
`photodiode 24 is used.” Id. at 9:31–34. Petitioner contends that Figures 1
`and 8 are otherwise identical, Pet. 22, a point that Patent Owner does not
`dispute. We agree that this is the most logical reading of Takahashi, as both
`figures share most of their numerical designations. Because claim 1 refers to
`a photodiode, rather than a photo gate, Figure 8 is the most relevant to this
`proceeding and we focus our discussion there, with reference to Takahashi’s
`discussion of Figure 1 where appropriate.
`In Figure 8, two instances of photodiode 24 are coupled to two
`instances of transfer switch MOS transistor 3, respectively. Ex. 1006, 4:24–
`25. MOS transistor for resetting 4 and source-follower amplifier MOS
`transistor 5 are coupled to power supply VDD and transfer switches 3. Id. at
`25–26. Horizontal selection switch MOS transistor 6 is coupled to amplifier
`5. Id. at 4:26–27.
`Takahashi’s circuit operation is shown in Figure 3, reproduced below:
`
`12
`
`
`
`IPR2018-00687
`Patent 6,731,335 B1
`
`
`Figure 3 is a timing chart for the embodiment of Figure 1. Id. at 3:44–45.
`Petitioner acknowledges that “Takahashi does not explicitly state that the
`timing of FIG. 3 is employed for FIG. 8,” but argues that “one of ordinary
`
`
`
`13
`
`
`
`IPR2018-00687
`Patent 6,731,335 B1
`
`skill in the art would immediately recognize that the timing chart of FIG. 3 is
`equally applicable to the pixel of FIG. 8 because the charge transfer and
`CDS [correlated double sampling] operations shown in FIG. 3 are applied
`equally to the pixel of photodiodes as well as the pixel of photo gates.”
`Pet. 37. As Petitioner notes, Takahashi describes no other timing for the unit
`pixel of Figure 8. Id. Thus, Petitioner argues, Figure 3 would be equally
`applicable to Figure 8 or, at least, would have been obvious to use with
`Figure 8. Id. at 38. Patent Owner does not advance any other reading of
`Takahashi. We agree with Petitioner that the most logical reading of
`Takahashi is that the timing diagram of Figure 3 applies equally to the
`circuit of Figure 8, at least as to the components that share the same
`numerical designations.
`With reference to Figure 3, during time T0, selection switch transistor
`6 is turned on via control pulse ɸS0 and reset transistor 4 is turned off via
`control pulse ɸR0. Ex. 1006, 4:58–5:7. During time T1, the reset voltage
`(referred to by Takahashi as “dark voltage”) is output and, subsequently, the
`top transfer switch transistor 3 is turned on via control pulse ɸTXo0. Id. at
`5:7–15. During time T2, photoelectric charge is transferred from the top
`photodiode 24 and, at time T3, the charge is output. Id. at 5:24–31. Figure 3
`shows that this process is repeated for the bottom transfer switch transistor 3
`(controlled by pulse ɸTXe0) and bottom photodiode 24. Id. at 6:6–13.
`
`
`b. Claim 1
`The preamble of method claim 1 recites a specific structure of a unit
`pixel, including “a first photodiode,” “a first transfer transistor . . . for
`transferring the photoelectric charges . . . in response to a first control
`
`14
`
`
`
`IPR2018-00687
`Patent 6,731,335 B1
`
`signal,” “a second photodiode,” “a second transfer transistor . . . for
`transferring the photoelectric charges . . . in response to a second control
`signal,” “a reset transistor,” “a drive transistor coupled to the power supply,”
`and “a select transistor.” These components are arranged in claim 1’s
`preamble in substantially the same manner as shown in the ’335 patent’s
`Figure 4, reproduced above.
`Petitioner maps the components shown in Takahashi’s Figures 1 and 8
`to these components as follows:
`top photo gate 1 (Figure 1) or top photodiode 24 (Figure 8) to
`“first photodiode” of claim 1;
`top transfer switch transistor 3 and control signal ɸTXo0 to
`“first transfer transistor” and “first control signal” of
`claim 1;
`bottom photo gate 1 (Figure 1) or bottom photodiode 24
`(Figure 8) to “second photodiode” of claim 1;
`bottom transfer switch transistor 3 and control signal ɸTXe0 to
`“second transfer transistor” and “second control signal”
`of claim 1;
`reset transistor 4 to “reset transistor” of claim 1;
`source-follower amplifier transistor 5 to “drive transistor” of
`claim 1;
`selection switch transistor 6 to “select transistor of claim 1; and
`the junction of transistors 3, 4, and 5 to the “single sensing
`node” of claim 1.
`Pet. 24–26, 36. A comparison of the ’335 patent’s Figure 4 with
`Takahashi’s Figure 8 shows that the components identified by Petitioner are
`arranged in the same manner as in the preamble of claim 1. Patent Owner
`does not contest this.
`
`15
`
`
`
`IPR2018-00687
`Patent 6,731,335 B1
`
`
`Petitioner contends that Takahashi teaches (e.g., through Figure 3 and
`its corresponding description) each step of claim 1 except for claim 1(a)
`(“fully depleting the first and second photodiodes”). Pet. 26–31, 36–38. We
`agree that Petitioner’s evidence supports a finding that Takahashi teaches
`each of steps 1(b)–1(f). Patent Owner does not contest these allegations.
`We briefly review Petitioner’s evidence as to steps 1(b)–1(f) and then
`discuss in detail Petitioner’s obviousness arguments as to step 1(a), which
`Patent Owner does contest.
`As to step 1(b), Petitioner contends that, inter alia, Figure 9 of
`Takahashi shows photodiodes 24 receiving light (hν) and generating
`photoelectric charges. Pet. 26; see also Ex. 1006, 9:37 (stating that charges
`are generated in photodiodes 24). As to step 1(c), as Petitioner notes
`(Pet. 27–28), during time T0, reset transistor 4 and selection switch
`transistor 6 are on, transfer switch transistors 3 are off, and a reset (“dark”)
`voltage is output through the junction of transistors 3, 4, and 5. Ex. 1006,
`4:58–5:11, Fig. 3. As to step 1(d), as Petitioner explains, at the end of time
`T0, reset transistor 4 is turned off; and during time T1, top transfer switch
`transistor 3 is turned on (with signal ɸTXo0) while reset transistor 4 is off,
`and charge from the top photodiode 24 is output through the junction of
`transistors 3, 4, and 5, source-follower amplifier transistor 5, and selection
`switch transistor 6. Id. at 5:7–23, Fig. 3. As to steps 1(e) and 1(f), Petitioner
`argues that Figure 3 shows that steps 1(c) and 1(d) are repeated for the
`bottom photodiode 24 and transfer switch transistor 3. Pet. 29–31, 36–37.
`We agree with Petitioner. See Ex. 1006, 6:6–13, Fig. 3.
`Petitioner concedes that Takahashi does not disclose step 1(a).
`Pet. 23. Nevertheless, Petitioner argues that it would have been obvious to
`
`16
`
`
`
`IPR2018-00687
`Patent 6,731,335 B1
`
`fully deplete Takahashi’s photodiodes “in order to eliminate any residual
`charges on the photodiode prior to capturing an image.” Id. Petitioner cites
`to Dr. Kleinfelder, who testifies:
`There are important reasons to deplete a photodiode prior to
`integration. One such reason is a phenomenon known as “dark
`current,”[2] which can cause charge to accumulate in a
`photodiode even without any light exposure. The gradual
`accumulation of this unwanted charge degrades the quality of
`an image in the form of noise. Another reason photodiodes are
`depleted before integration is that photodiodes may retain
`accumulated electric charges from a previous image if those
`electric charges were not fully transferred to the floating
`diffusion from the prior readout.
`Ex. 1002 ¶ 73.
`Dr. Kleinfelder also notes that the ’335 patent describes a step of fully
`depleting a photodiode as part of the prior art. Id. In particular, in
`describing Figures 2 and 3, which the figures themselves identify as “prior
`art,” the ’335 patent describes, as the first step of a process for a
`“conventional unit pixel”: “1) In section ‘A’ of FIG. 3, the transfer
`transistor M21 and the reset transistor M11 are turned on and the select
`transistor M41 is turned off, so that the photodiode 101 is fully depleted.”
`Ex. 1001, 2:17–20 (emphasis added), 2:59.
`Patent Owner contends that Takahashi does not teach step 1(a) of
`claim 1. Patent Owner acknowledges that the considerations identified by
`
`
`2 “Dark current” is “(3) (photoelectric device) The current flowing in the
`absence of irradiation.” IEEE 100, THE AUTHORITATIVE DICTIONARY OF
`IEEE STANDARDS TERMS 267 (7th ed. 2000). On the current record, this
`appears to be different from the “dark voltage” described in Takahashi (e.g.,
`Ex. 1006, 5:7–11) as the voltage output when a pixel is reset.
`
`17
`
`
`
`IPR2018-00687
`Patent 6,731,335 B1
`
`Dr. Kleinfelder “generally need to be taken into account in image sensor
`design.” Prelim. Resp. 17. Nevertheless, Patent Owner argues, Takahashi
`already describes mechanisms for addressing dark current and residual
`charges and, therefore, a skilled artisan would not have had a reason to
`perform step 1(a) in Takahashi’s procedure. Id. at 17–18.
`With respect to Takahashi’s Figure 8, Takahashi states that “[c]harges
`generated by the control pulse ɸTX are completely transferred to the FD
`portion.” Ex. 1006, 9:37–39. Takahashi has similar description for the
`embodiment of Figure 1. Id. at 5:17–23 (“In this instance, it is preferable to
`set to a voltage relation such as to raise a potential well extending under the
`photo gate 2 and to allow the light generation carriers to be perfectly
`transferred to the FD portion 21. Therefore, so long as the complete transfer
`can be performed, the control pulse ɸTX is not limited to a pulse but can be
`also set to a fixed electric potential.”). Takahashi also describes another
`embodiment in which
`the surface p+-type layer 26 constructs the photoelectric
`converting unit together with the n-type layer 25 and a pixel is
`formed by a buried type photodiode. With such a structure, a
`dark current which is generated in the surface can be
`suppressed. As compared with Fig. 9, since high photo charges
`of a good efficiency can be obtained, an image signal of a high
`S/N ratio and a high quality can be obtained.
`Id. at 10:6–14.
`Patent Owner argues that Petitioner “ignores these teachings when it
`assumes that it would have been obvious for a [person of ordinary skill in
`the art] to add the step of ‘fully depleting the first and second photodiodes’
`to the Takahashi system” and “does not acknowledge this structural element
`and does not explain why it would have been obvious for a [person of
`
`18
`
`
`
`IPR2018-00687
`Patent 6,731,335 B1
`
`ordinary skill in the art] to implement the step of fully depleting the
`photodiodes when a structural element is already in place for accomplishing
`this result.” Prelim. Resp. 19–20. Referring to these aspects of Takahashi,
`Patent Owner argues that
`structural elements exist in Takahashi to ensure that the electric
`charges are fully transferred to the floating diffusion during
`readout. Thus, using Dr. Kleinfelder’s own logic, it is
`unnecessary in Takahashi to fully deplete the photodiodes
`before readout as an initial step in driving a unit pixel for
`capturing the next image.
`Id. at 20. Patent Owner argues that the precondition Dr. Kleinfelder sets for
`needing step 1(a) is not met in Takahashi. Id. at 21. According to Patent
`Owner, “[s]ince the charges in the photodiode are completely transferred to
`the floating diffusion during image readout, a [person of ordinary skill in the
`art] would have recognized no need to implement a step of fully depleting
`the photodiodes before integrating a new image.” Prelim. Resp. 22. Patent
`Owner characterizes this as “a strong teaching away that militates in favor of
`non-obviousness.” Id. at 2, 29.
`At this stage of the proceeding, we credit Dr. Kleinfelder’s testimony
`that a skilled artisan would have had reasons to implement step 1(a) in
`Takahashi’s system to avoid noise and degradation of image quality due to
`dark current or retained accumulated charge in the photodiodes. Ex. 1002
`¶ 73. The ’335 patent clearly identifies this step as conventional in the art of
`CMOS image sensors. Ex. 1001, 2:17–20. Patent Owner points us to
`statements in Takahashi that it contends also solve the problems identified
`by Dr. Kleinfelder. Nevertheless, even if we fully credit these arguments,
`they do not persuade us that a skilled artisan would have been dissuaded or
`discouraged from implementing step 1(a) in Takahashi’s system. See In re
`
`19
`
`
`
`IPR2018-00687
`Patent 6,731,335 B1
`
`Mouttet, 686 F.3d 1322, 1334 (“[T]he mere disclosure of alternative designs
`does not teach away. This court has further explained that just because
`better alternatives exist in the prior art does not mean that an inferior
`combination is inapt for obviousness purposes.”) (internal citations and
`quotation marks omitted). Petitioner’s evidence supports a finding that a
`skilled artisan would have had reasons to implement step 1(a) of claim 1 in
`Takahshi’s system.
`In sum, on the current record, Petitioner has established a reasonable
`likelihood that it would prevail with respect to claim 1 as obvious over
`Takahashi.
`
`
`c. Claim 2–5, 7, 9, and 11
`Claim 2 depends from claim 1 and recites that step 1(b) includes
`“generating and integrating the photoelectric charges of the first photodiode,
`regardless of the states of the reset transistor, the second transfer transistor
`and the select transistor, while the first transfer transistor is turned off.”
`Claim 4 depends from claim 1 and adds a similar limitation as to the second
`photodiode. Petitioner argues that Figure 3 of Takahashi shows the reset
`transistor, select transistor, and other transfer transistor changing states while
`the transfer transistor for a photodiode is off (and the photodiode is
`generating and integrating charge). Pet. 31–32, 38–39. Dr. Kleinfelder
`testifies that generation and integration of photoelectric charges on a
`photodiode occur whenever the corresponding transfer transistor is turned
`off. Ex. 1002 ¶ 74. This evidence supports findings that Takahashi teaches
`the additional limitations of claims 2 and 4.
`
`20
`
`
`
`IPR2018-00687
`Patent 6,731,335 B1
`
`
`Claim 3 depends from claim 2 and recites “wherein the method
`controls a depletion time and a photo charge generating and integrating time
`by adjusting a turn-on time and a turn-off time for the first and second
`transfer transistors.” Dr. Kleinfelder testifies that “a depletion time and a
`photo charge generating and integrating time are controlled by the timing
`operations of the corresponding transfer transistor, with depletion capable of
`occurring when the transfer transistor is turned on and generation and
`integration of photoelectric charges capable of occurring when the transfer
`transistor is turned off.” Ex. 1002 ¶ 75; Pet. 39. This evidence supports
`findings that Takahashi teaches the additional limitations of claim 3.
`Claims 5, 7, 9, and 11 depend from claim 1 and account for a settling
`time between when the reset or transfer transistors are turned off and the
`respective reset or data values are sampled. For each of these claims,
`Petitioner points to evidence, shown in particular in Figure 3, that Takahashi
`incorporates “a brief pause” between when the respective transistor is turned
`off and when the reset or data value is sampled. Pet. 32–36. This evidence
`supports findings that Takahashi teaches the additional limitations of claims
`5, 7, 9, and 11.
`In sum, on the current record, Petitioner has established a reasonable
`likelihood that it would prevail with respect to claims 2–5, 7, 9, and 11 as
`obvious over Takahashi. Patent Owner does not present separate argument
`for these dependent claims.
`
`
`21
`
`
`
`IPR2018-00687
`Patent 6,731,335 B1
`
`
`3. Alleged Obviousness of Claims 6, 8, 10, and 12 over
`Takahashi and Gowda
`Petitioner contends that claims 6, 8, 10, and 12 would have been
`obvious over Takahashi and Gowda. Pet. 41–44. For the reasons given
`below, Petitioner has demonstrated a reasonable likelihood that it would
`prevail on this ground.
`
`
`a. Scope and Content of the Prior Art—Overview of
`Gowda
`Gowda describes a CMOS image sensor in which correlated double
`sampling is performed entirely in the digital domain. Ex. 1007, Abstract.
`Figure 3, reproduced below, illustrates an example:
`
`22
`
`
`
`IPR2018-00687
`Patent 6,731,335 B1
`
`
`
`Figure 3 is a schematic block diagram of an image sensor. Id. at 3:44–45.
`In Gowda’s device 20, analog to digital converters (ADC) 401 to 40N
`replace analog readout circuits to read the outputs of a plurality of pixels 30.
`Id. at 3:55–61. According to Gowda, “A/D converters 401–40N directly
`convert the reset level and signal level on the respective column busses 151–
`
`23
`
`
`
`IPR2018-00687
`Patent 6,731,335 B1
`
`15N to digital values, which are then stored in registers 421–42N.” Id. at
`3:61–64. Gowda states that
`The data stored in the registers are transferred to logic block 44
`which includes processing/subtraction circuitry to subtract the
`reset levels from the corresponding signal levels to complete a
`correlated double sampling operation. As a result, since noisy
`analog capacitors to store the reset and signal levels are
`obviated, the accuracy of the correlated double sampling is
`improved.
`Id. at 3:64–4:4.
`
`
`b. Claim 6, 8, 10, and 12
`Claim 6 depends from claim 5 and recites “wherein the sampled reset
`voltage level is outputted to an analogue-to-digital converter so that the
`sampled reset voltage level is converted into a digital signal.” Claims 8, 10,
`and 12 depend from claims 7, 9, and 11, respectively, and add substantially
`the same limitation for the sampled data voltage levels (claims 7, 11) and
`reset voltage level (claim 9).
`Petitioner argues that Gowda provides an express example of the use
`of an ADC to sample reset and data voltage levels and convert them to
`digital signals. Pet. 41–43. As explained above, Gowda describes a CMOS
`imaging device in which “A/D converters . . . directly convert the reset level
`and signal level on the respective column buses . . . to digital values, which
`are then stored in registers . . . .” Ex. 1007, 3:61–64. Petitioner argues and
`Dr. Kleinfelder testifies that Gowda includes an explicit motivation to
`combine its ADCs with the pixels disclosed in Takahashi, namely, noise
`reduction and increased accuracy. Pet. 43–44 (citing Ex. 1007, 3:64–4:4);
`Ex. 1002 ¶ 76.
`
`24
`
`
`
`IPR2018-00687
`Patent 6,731,335 B1
`
`
`Petitioner’s evidence supports findings that Gowda teaches the
`additional limitations of claims 6, 8, 10, and 12, and that a skilled artisan
`would have had reasons to combine the teachings of Takahashi and Gowda.
`In sum, on the current record, Petitioner has established a reasonable
`likelihood that it would prevail with respect to claims 6, 8, 10, and 12 as
`obvious over Takahashi and Gowda. Patent Owner does not raise separate
`arguments for this ground. Prelim. Resp. 34.
`
`
`4. Alleged Obviousness of Claims 1–5, 7, 9, and 11 over
`Takahashi and Dickinson
`Petitioner contends that claims 1–5, 7, 9, and 11 would have been
`obvious over Takahashi and Dickinson. Pet. 47–49. For the reasons given
`below, Petitioner has demonstrated a reasonable likelihood that it would
`prevail on this ground.
`
`
`a. Scope and Content of the Prior Art—Overview of
`Dickinson
`Dickinson describes an active pixel image sensor with active pixel
`circuitry shared by multiple sensing elements. Ex. 1008, Abstract. Figure 4,
`reproduced below, illustrates an example:
`
`25
`
`
`
`IPR2018-00687
`Patent 6,731,335 B1
`
`
`
`
`Figure 4 is a circuit diagram of an active pixel image sensor. Id. at 3:9–10
`Photodiodes RD, GRN, and BL capture red, green, and blue light,
`respectively, and are connected through gating elements Q4, Q5, and Q6,
`respectively. Id. at 4:5–11. Each photodiode/gating element pair is
`connected in parallel to the gate of a source follower, formed by transistors
`Q2 and Q3, and also are connected to power source Vdd through reset
`transistor Q1. Id. at 4:11–15. In operation, inter alia, “[e]ach RD, GRN and
`BL photodiode is first pre-charged by connecting each photodiode to Vdd,
`
`26
`
`
`
`IPR2018-00687
`Patent 6,731,335 B1
`
`by holding the reset signal high while pulsing each of the gate transistors
`TX1 to TX3 as shown with timing ‘A’ [of Figure 5].” Id. at 4:20–25, Fig. 5.
`
`
`b. Claim 1–5, 7, 9, and 11
`Petitioner contends that Dickinson includes an express disclosure of
`claim element 1(a), “fully depleting the first and second photodiodes.”
`Pet. 47. In particular, Petitioner contends that Dickinson’s disclosure
`relative to time period “A” of its Figure 5 (Ex. 1008, 4:
Accessing this document will incur an additional charge of $.
After purchase, you can access this document again without charge.
Accept $ Charge
Still Working On It
This document is taking longer than usual to download. This can happen if we need to contact the court directly to obtain the document and their servers are running slowly.
Give it another minute or two to complete, and then try the refresh button.
A few More Minutes ... Still Working
It can take up to 5 minutes for us to download a document if the court servers are running slowly.
Thank you for your continued patience.
This document could not be displayed.
We could not find this document within its docket. Please go back to the docket page and check the link. If that does not work, go back to the docket and refresh it to pull the newest information.
Your account does not support viewing this document.
You need a Paid Account to view this document. Click here to change your account type.
Your account does not support viewing this document.
Set your membership
status to view this document.
With a Docket Alarm membership, you'll
get a whole lot more, including:
- Up-to-date information for this case.
- Email alerts whenever there is an update.
- Full text search for other cases.
- Get email alerts whenever a new case matches your search.
One Moment Please
The filing “” is large (MB) and is being downloaded.
Please refresh this page in a few minutes to see if the filing has been downloaded. The filing will also be emailed to you when the download completes.
Your document is on its way!
If you do not receive the document in five minutes, contact support at support@docketalarm.com.
Sealed Document
We are unable to display this document, it may be under a court ordered seal.
If you have proper credentials to access the file, you may proceed directly to the court's system using your government issued username and password.
Access Government Site
