UNITED STATES PATENT AND TRADEMARK OFFICE
`
`______________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`______________
`
`KINGSTON TECHNOLOGY COMPANY, INC.
`Petitioner
`
`v.
`
`SPEX TECHNOLOGIES, INC.
`Patent Owner
`
`______________
`
`
`Case IPR: IPR2018-01003
`U.S. Patent No. 6,088,802
`
`______________
`
`Date: May 2, 2018
`
`______________
`
`PETITION FOR INTER PARTES REVIEW OF
`U.S. PATENT NO. 6,088,802
`
`
`
`
`
`
`Mail Stop Patent Board
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`

`

`Petition for Inter Partes Review of US Patent No. 6,088,802
`
`TABLE OF CONTENTS
`
`Page
`INTRODUCTION AND RELIEF REQUESTED .......................................... 1 
`I. 
`II.  GROUNDS FOR STANDING ........................................................................ 1 
`III.  PROPOSED GROUNDS OF UNPATENTABILITY .................................... 1 
`A. 
`Statutory Grounds for Challenge ........................................................... 2 
`B. 
`Prior Art Offered for the Present Unpatentability Challenges .............. 2 
`IV.  BACKGROUND ............................................................................................. 3 
`A.  Description of the ’802 Patent ............................................................... 3 
`B. 
`Technological Background .................................................................... 4 
`LEVEL OF ORDINARY SKILL IN THE ART ............................................. 4 
`V. 
`VI.  CLAIM CONSTRUCTION ............................................................................ 5 
`“defined interaction” (all Claims) and “interaction with a host
`A. 
`computing device in a defined way” (Claims 38–39) ........................... 5 
`“peripheral device” (all Claims) ............................................................ 6 
`“security means for enabling one or more security operations to
`be performed on data” (Claims 1–2, 6–7, 11–12, 23–25) and
`“means for performing the one or more security operations”
`(Claim 39) .............................................................................................. 7 
`“target means for enabling a defined interaction with a host
`computing device” (Claims 1–2, 6–7, 11–12, 23–25) .......................... 8 
`“means for enabling communication between the security
`means and the target means” (Claims 1–2, 6–7, 11–12, 23–25) ........... 9 
`“means for enabling communication with a host computing
`device” (Claims 1–2, 6–7, 11–12, 23–25) ............................................. 9 
`
`B. 
`C. 
`
`D. 
`
`E. 
`
`F. 
`
`i
`
`

`

`TABLE OF CONTENTS
`(continued)
`
`Page
`
`G. 
`
`H. 
`
`“means for operably connecting the security means and/or the
`target means to the host computing device in response to an
`instruction from the host computing device” (Claims 1–2, 6–7) ........ 10 
`“means for mediating communication of data between the host
`computing device and the target means so that the
`communicated data must first pass through the security means”
`(Claims 1–2, 11–12, 23) ...................................................................... 11 
`“means for providing to a host computing device, in response to
`a request from the host computing device for information
`regarding the type of the peripheral device, information
`regarding the function of the target means” (Claims 6–7, 23–
`25) ........................................................................................................ 11 
`“means for non-volatilely storing data” (Claims 2, 12, 25) ................ 12 
`J. 
`VII.  THE PRIOR ART RENDERS OBVIOUS CLAIMS 1–2, 6–7, 11–12,
`23–25, 38–39 OF THE ’802 PATENT .......................................................... 12 
`A.  Cited Prior Art ..................................................................................... 13 
`1. 
`Harari......................................................................................... 13 
`2. 
`PCMCIA System Architecture: 16-Bit PC Cards (1995) ......... 16 
`3.  Wang ......................................................................................... 19 
`4. 
`Dumas ....................................................................................... 21 
`B.  Ground 1: Claims 1–2, 6–7, 11–12, 23–25, and 38–39 are
`Rendered Obvious by Harari in View of PCMCIA System
`Architecture ......................................................................................... 22 
`1. Motivation to Combine Harari and PCMCIA System
`Architecture ............................................................................... 24
`Independent Claim 1 ................................................................. 25
`Dependent Claim 2 ................................................................... 42
`Independent Claim 6 ................................................................. 43
`Dependent Claim 7 ................................................................... 49
`Independent Claim 11 ............................................................... 50
`Dependent Claim 12 ................................................................. 50
`Independent Claim 23 ............................................................... 50
`
`I. 
`
`2.
`3.
`4.
`5.
`6.
`7.
`8.
`
`ii
`
`

`

`TABLE OF CONTENTS
`(continued)
`
`Page
`Independent Claim 24 ............................................................... 51
`9.
`10. Dependent Claim 25 ................................................................. 51
`11.
`Independent Claim 38 ............................................................... 51 
`12. 
`Independent Claim 39 ............................................................... 53 
`C.  Ground 2: Claims 1–2, 11–12, 23, and 39 are Rendered Obvious
`by Harari in View of Wang ................................................................. 56 
`1.  Motivation to Combine Harari, Wang, and PCMCIA
`System Architecture .................................................................. 56
`2. Wang Discloses Means for Mediating Communication of Data
`Between the Host Computing Device and the Target Means So
`That the Communicated Data Must First Pass Through the
`Security Means (Elements [1F], [11E], [23E], [39C]) ............. 57 
`D.  Grounds 3-4: Claims 1–2, 11–12, 23, and 39 are Rendered
`Obvious for the Same Reasons as Grounds 1-2 when
`Considered Further in View of Dumas. .............................................. 61 
`1. Motivation to Combine Dumas with Harari, PCMCIA System
`Architecture, and Wang ............................................................ 62
`Dumas Discloses Mediating Communication of Data Between
`the Host Computing Device and the Target Means So That the
`Communicated Data Must First Pass Through the Security
`Means (Elements [1F], [11E], [23E], and [39C]) ..................... 63 
`VIII.  MANDATORY NOTICES ........................................................................... 64 
`IX.  CONCLUSION .............................................................................................. 67 
`
`
`2.
`
`iii
`
`

`

`TABLE OF AUTHORITIES
`
`Cases
`Phillips v. AWH Corp.,
`415 F.3d 1303 (Fed. Cir. 2005) (en banc) ............................................................ 8
`In Re Rambus Inc.,
`694 F.3d 42 (Fed. Cir. 2012) ................................................................................ 8
`Randall Mfg. v. Rea,
`733 F.3d 1355 (Fed. Cir. 2013) .......................................................................... 15
`SPEX Techs., Inc. v. Western Digital Corp.,
`Case No. 8:16-cv-01799 (C.D. Cal.) .................................................................. 67
`Williamson v. Citrix Online, LLC,
`792 F.3d 1339 (Fed. Cir. 2015) ............................................................................ 8
`Statutes
`35 U.S.C. § 102(b) ..................................................................................................... 3
`35 U.S.C. § 102(e) ..................................................................................................... 2
`35 U.S.C. § 103 ........................................................................................................ 15
`35 U.S.C. § 311(c) ..................................................................................................... 1
`Regulations
`37 C.F.R. § 42.6(e) ..................................................................................................... 1
`37 C.F.R. § 42.10(b) ................................................................................................ 68
`37 C.F.R. § 42.100(b) ................................................................................................ 8
`
`
`
`iv
`
`

`

`
`
`
`Exhibit List
`
`
`
`Exhibit Number
`1001
`
`Document
`U.S. Patent No. 6,088,802 (“the ’802 Patent”)
`
`1002
`
`1003
`
`1004
`
`1005
`
`1006
`
`1007
`
`1008
`
`1009
`
`1010
`
`1011
`
`1012
`
`1013
`
`1014
`
`1015
`
`1016
`
`Omitted
`
`File History of the ’802 Patent
`
`U.S. Patent No. 5,887,145 to Harari et al. (“Harari”)
`
`U.S. Patent No. 6,199,163 to Dumas et al. (“Dumas”)
`
`Don Anderson, PCMCIA SYSTEM ARCHITECTURE: 16-
`BIT PC CARDS (MindShare, Inc., 2nd ed. 1995)
`(“PCMCIA Architecture”)
`
`U.S. Patent No. 5,822,196 to Hastings et al. (“Hastings”)
`
`U.S. Patent No. 5,922,060 to Goodrum (“Goodrum”)
`
`U.S. Patent No. 5,941,965 to Moroz et al. (“Moroz”)
`
`U.S. Patent No. 5,943,482 to Culley et al. (“Culley”)
`
`U.S. Patent No. 6,009,151 to Staples (“Staples”)
`
`Windows Developers Journal, Vol. 7, No. 8 (Aug. 1996)
`
`Claim Construction Briefing in SPEX Techs., Inc. v.
`Western Digital Corp., Case No. 16-cv-01799 (C.D. Cal.)
`(“SPEX Claim Construction Brief”)
`
`Tentative Order Regarding Claim Construction, Case No.
`16-cv-01799 (C.D. Cal.) (“Tentative Constructions”)
`
`Declaration of Dr. Martin Kaliski, Ph.D. (“Kaliski Decl.”)
`
`Exhibit A (Updated) to Defendants’ Reply Claim
`
`i
`
`

`

`
`
`Construction Brief
`
`1017
`
`1018
`
`1019
`
`1020
`
`Reporter’s Transcript of Proceedings in SPEX Techs, Inc.
`v. Kingston Tech. Corp., et al., Case No. 16-cv-01790
`(C.D. Cal.) (“Markman Hearing Transcript”)
`
`Declaration of Sylvia Hall-Ellis, Ph.D. (“Hall-Ellis Decl.”)
`
`U.S. Patent No. 5,765,027 to Wang et al. (“Wang”)
`
`MARC Record
`
`ii
`
`

`

`
`
`I.
`
`INTRODUCTION AND RELIEF REQUESTED
`Kingston Technology Company, Inc. (“Petitioner”) petitions for institution of
`
`inter partes review of U.S. Patent No. 6,088,802 (“the ’802 Patent”) (Ex. 1001). The
`
`’802 Patent issued on July 11, 2000, and is assigned to SPEX Technologies, Inc.
`
`(“Patent-Owner”). Petitioner respectfully requests cancellation of claims 1–2, 6–7,
`
`11–12, 23–25, and 38–39 of the ’802 Patent based on the grounds of unpatentability
`
`detailed herein. The prior art and other evidence offered with this Petition
`
`establishes that all elements in the challenged claims of the ’802 Patent were well
`
`known as of the earliest alleged priority date, and that the claimed devices and
`
`methods recited in the ’802 Patent are obvious.
`
`II. GROUNDS FOR STANDING
`Petitioner certifies that the ’802 Patent is available for review under 35 U.S.C.
`
`§ 311(c) and that Petitioner is not estopped from requesting an inter partes review
`
`challenging claims 1–2, 6–7, 11–12, 23–25, and 38–39 on the grounds identified in
`
`this Petition.
`
`III. PROPOSED GROUNDS OF UNPATENTABILITY
`The present Petition relies on prior art references that have not been
`
`considered by the Patent Office in the file history of the ’802 Patent, Ex. 1003, and
`
`details how the challenged claims are obvious.
`
`1
`
`

`

`
`
`Statutory Grounds for Challenge
`
`A.
` Ground 1: Harari in view of PCMCIA System Architecture renders claims 1–2,
`
`6–7, 11–12, 23–25, and 38–39 obvious under §103(a);
`
` Ground 2: Harari in view of Wang and in further view of PCMCIA System
`
`Architecture renders claims 1–2, 11–12, and 23 obvious under § 103 (a);
`
` Ground 3: Harari in view of Dumas and PCMCIA System Architecture renders
`
`claims 1–2, 11–12, 23, and 39 obvious under § 103(a); and
`
` Ground 4: Harari in view of Dumas, Wang and PCMCIA System Architecture
`
`renders claims 1–2, 11–12, and 23 obvious under § 103 (a).
`
`B.
`Prior Art Offered for the Present Unpatentability Challenges
`Grounds 1-4 rely on the following patents and printed publications:
`
` U.S. Patent No. 5,887,145 to Harari et al. (“Harari”) (Ex. 1004) was filed on
`
`January 9, 1997; this reference is prior art at least under pre-AIA 35 U.S.C. §
`
`102(e) (the ’802 Patent’s earliest claimed priority date is June 4, 1997).
`
` U.S. Patent No. 5,765,027 to Wang et al. (“Wang”) (Ex. 1019) was filed on
`
`September, 26 1994; this reference is prior art at least under pre-AIA 35
`
`U.S.C. § 102(e).
`
` U.S. Patent No. 6,199,163 to Dumas et al. (“Dumas”) (Ex. 1005) was filed on
`
`March 26, 1996; this reference is prior art at least under pre-AIA 35 U.S.C. §
`
`102(e).
`
`2
`
`

`

`
`
` Don Anderson, PCMCIA System Architecture: 16-Bit PC Cards (MindShare,
`
`Inc., 2nd ed. 1995) (Ex. 1006). PCMCIA System Architecture was published
`
`in 1995, making it prior art at least under pre-AIA 35 U.S.C. § 102(b).
`
`PCMCIA System Architecture bears a copyright date of 1995 and a Library of
`
`Congress Cataloging-in-Publication with ISBN and been referenced as prior
`
`art in numerous patents filed before the earliest claim of priority in this case,
`
`including U.S. Patent No. 5,822,196 (filed June 5, 1996) (Ex. 1007); U.S.
`
`Patent No. 5,922,060 (filed December 31, 1996) (Ex. 1008); U.S. Patent No.
`
`5,941,965 (filed July 12, 1996) (Ex. 1009); U.S. Patent No. 5,943,482 (filed
`
`June 5, 1996) (Ex. 1010); U.S. Patent No. 6,009,151 (filed August 27, 1996)
`
`(Ex. 1011), to name a few. It also appears in a number of applications
`
`incorporated by reference or as admitted prior art by the applicant as well,
`
`including in the ’965 Patent (Ex. 1009) at 3:3336 and the ’151 Patent (Ex.
`
`1011) at 4:34-37, listed above. In addition, PCMCIA System Architecture was
`
`reviewed as a “recent title” in the August 1996 edition of the Windows
`
`Developer’s Journal. Ex. 1012 at 61-63. PCMCIA System Architecture was
`
`published and publicly available by September 22, 1995 according to its
`
`MARC record. See Hall-Ellis Decl., Ex. 1018 at ¶20; Ex. 1020.
`
`IV. BACKGROUND
`A. Description of the ’802 Patent
`
`3
`
`

`

`
`
`The ’802 Patent relates to a peripheral device that “communicate[s] with a
`
`host computing device to enable one or more security operations to be performed by
`
`the peripheral device on data stored within the host computing device, data provided
`
`from the host computing device to the peripheral device, or data retrieved by the host
`
`computing device from the peripheral device.” ’802 Patent, Ex. 1001, 1:21- 27. The
`
`’802 Patent illustrates the aim of the invention through figures that contrast the
`
`claimed invention with the prior art.
`
`Each challenged claim is directed to a “peripheral device” or a method “[f]or
`
`use in a peripheral device.” Claims 1–2, 6–7, 11–12, and 23–25 are device claims
`
`with means-plus-function elements related to providing security, a defined
`
`interaction, and establishing communications between various computer structures.
`
`Claims 38–39 are method claims with limitations that parallel the elements in the
`
`device claims.
`
`B.
`Technological Background
`By the early-to-mid 1990s, computers were household items with ever-
`
`increasing capabilities and an ever-expanding array of available peripheral devices
`
`(i.e., external devices that communicate with a computer) usable with a computer.
`
`Kaliski Decl., Ex. 1015, ¶25. To protect sensitive data and to limit access to
`
`authorized users, skilled artisans developed ways to secure data, such as by
`
`restricting access to data using passwords and encryption. Id., ¶27. LEVEL OF
`
`4
`
`

`

`
`
`ORDINARY SKILL IN THE ART
`
`A person of ordinary skill in the art of the ’802 Patent would have at least a
`
`Bachelor’s degree in electrical engineering or computer science, and at least one year
`
`of experience in computer security and/or computer architecture for peripheral
`
`devices or equivalent education or experience. Kaliski Decl., Ex. 1015, ¶16.
`
`V. CLAIM CONSTRUCTION
`Claims of an expired patent in inter partes review are construed according to
`
`the standard applied in the district courts under Phillips v. AWH Corp., 415 F.3d
`
`1303 (Fed. Cir. 2005) (en banc).
`
`Patent-Owner and Petitioner submitted claim construction briefing in the DCT
`
`Litigation. And the Court issued tentative constructions. Ex. 1014. This petition is
`
`based on the claim constructions urged by Patent-Owner in the DCT Litigation, or
`
`as the parties agreed. See Patent-Owner’s Opening Claim Construction Br. (“Claim
`
`Construction Br.”), Ex. 1013.
`
`A.
`
`“defined interaction” (all Claims) and “interaction with a host
`computing device in a defined way” (Claims 38–39)
`Patent-Owner argued that “defined interaction” is “a specific, predefined
`
`functionality of the device, such as a data storage, data communication, data input
`
`and output, or user identification.” Ex. 1013 at 3. Patent-Owner also asserted that
`
`“interaction with a host computing device in a defined way” is an “interaction with
`
`5
`
`

`

`
`
`a host computing device using a specific, predefined functionality of the device, such
`
`as data storage, data communication, data input and output, or user identification.”
`
`Ex. 1013 at 3-4. Outside the claims, the ’802 Patent mentions “defined interaction”
`
`only in the Abstract and the Summary of the Invention where it states “the peripheral
`
`device can be adapted to enable, in a single integral peripheral device, performance
`
`of one or more security operations on data, and a defined interaction with a host
`
`computing device that has not previously been integrated with security operations in
`
`a single integral device.” ’802 Patent, Ex. 1001, at Abstract; 3:28-33. The
`
`description further explains, “defined interactions can provide a variety of types of
`
`functionality (e.g., data storage, data communication, data input and output, user
`
`identification).” Id. at 3:33-35. The district court tentatively rejected that
`
`construction, and construed these terms as meaning: “an interaction [with a host
`
`computing device] that can provide a variety of functionalities.” Ex. 1014 at 6.
`
`B.
`“peripheral device” (all Claims)
`The ’802 Patent provides a definition of “peripheral device” stating,
`
`“‘peripheral device’ can refer to any device that operates outside of a host computing
`
`device and that is connected to the host computing device.” ’802 Patent, Ex. 1001,
`
`4:52-55. Patent-Owner thus proposed construing this term as “any device that
`
`operates outside of a host computing device (i.e. the keyboard-computer-screen
`
`system) and that is connected to the host computing device. Typical peripheral
`
`6
`
`

`

`
`
`devices include but are not limited to a disk drive and a printer.” Ex. 1013 at 6. The
`
`district court tentatively rejected that construction, and construed these terms as
`
`meaning: “a device that operates outside of a host computing device and that is
`
`connected to the host computing device, including such devices in the same housing
`
`as the host computing device.” Ex. 1014 at 9.
`
`C.
`
`“security means for enabling one or more security operations to
`be performed on data” (Claims 1–2, 6–7, 11–12, 23–25) and
`“means for performing the one or more security operations”
`(Claim 39)
`The parties agree that this is a means-plus-function term and that the recited
`
`function is “enabling one or more security operations to be performed on data”
`
`(Claims 1–2, 6–7, 11–12, 23–25) and “performing the one or more security
`
`operations” (Claim 39). Patent-Owner proposed that the corresponding structures
`
`are: (1) a cryptographic processing device 801 (processor capable of performing the
`
`cryptographic operations) based on ’802 Patent, Ex. 1001, at 15:63–64, Fig. 8; (2) a
`
`security token device that performs security operations and that includes one or more
`
`mechanisms (such as, for example, use of a hardware random number generator
`
`and/or protected memory) to provide security for the content of those operations
`
`based on 5:35–39; (3) a specific hardware component programmed or configured to
`
`perform a security operation based on 18:1–47; (4) a special purpose embedded
`
`processor, embodied on a single integrated chip and designated as MYK-82 (and
`
`7
`
`

`

`
`
`referred to by the name Capstone), which includes an ARM6 processor core and
`
`several special purpose cryptographic processing elements that have been developed
`
`by the Department of Defense based on 16:1–6; or (5) equivalents thereof. Ex. 1013
`
`at 8–9.
`
`The district court tentatively agreed with the proposed function, but limited
`
`the structures to: (1) a specific hardware component programmed or configured to
`
`perform a security operation disclosed in ’802 Patent at 18:1-47 or (2) a special
`
`purpose embedded processor, embodied on a single integrated chip and designated
`
`as MYK-82 (and referred to by the name Capstone), which includes an ARM6™
`
`processor core and several special purpose cryptographic processing elements that
`
`have been developed by the Department of Defense (’802 Patent at 15:67-16:8). Ex.
`
`1014, at 13–14.
`
`D.
`
`“target means for enabling a defined interaction with a host
`computing device” (Claims 1–2, 6–7, 11–12, 23–25)
`The parties agreed on the construction in the DCT Litigation of this means-
`
`plus-function term, subject to Defendants’ argument regarding the indefiniteness of
`
`the term “defined interaction.” Ex. 1016, at Page 5. The recited function is
`
`“enabling a defined interaction with a host computing device.” The agreed
`
`corresponding structures based on the disclosure in the specification, and in view of
`
`the parties’ proposed constructions for “defined interaction,” are: (1) a memory
`
`8
`
`

`

`
`
`module adapted to enable non-volatile storage of data (’802 Patent at 13:27–29); (2)
`
`a communications module adapted to enable communications between the host
`
`computing device and a modem or LAN transceiver (’802 Patent at 13:50–62); (3)
`
`a smart card reader (’802 Patent at 15:24–28); (4) biometric device (’802 Patent at
`
`14:10–19); or (5) equivalents therefore.
`
`E.
`
`“means for enabling communication between the security means
`and the target means” (Claims 1–2, 6–7, 11–12, 23–25)
`The parties agreed to the construction in the DCT Litigation for this means-
`
`plus-function term. Ex. 1016, at Page 6. The recited function is “enabling
`
`communication between the security means and the target means.” In the DCT
`
`Litigation, the parties agreed that the corresponding structure is conventional
`
`computer bus 615 based on the disclosure at 6:40-45. Ex. 1016, at Page 6.
`
`F.
`
`“means for enabling communication with a host computing
`device” (Claims 1–2, 6–7, 11–12, 23–25)
`This function for this means-plus-function term is “enabling communication
`
`with a host computing device.” Patent-Owner’s proposed corresponding structure
`
`includes: (1) Input/Output (I/O) device, for example a conventional computer bus
`
`based on 6:37-40; (2) PCMCIA based on 5:5-10; (3) Cord between housing and
`
`matching receptacle based on 7:3-5; (4) Wireless communication based on 5:5-10;
`
`(5) Smart card interface based on 5:5-10; (6) Serial interface (such as RS-232) based
`
`on 5:5-10; (7) Parallel interface based on 5:5-10; (8) SCSI interface based on 5:5-
`
`9
`
`

`

`
`
`10; (9) IDE interface based on 5:5-10; or (10) equivalents thereof. Ex. 1013 at 15.
`
`The district court tentatively agreed with Patent-Owner. Ex. 1014 at 32–33.
`
`G.
`
`“means for operably connecting the security means and/or the
`target means to the host computing device in response to an
`instruction from the host computing device” (Claims 1–2, 6–7)
`This means-plus-function term’s function is “operably connecting the security
`
`means and/or the target means to the host computing device in response to an
`
`instruction from the host computing device.”
`
`Patent-Owner proposed the corresponding structure is: (1) PCMCIA interface
`
`and memory section 612a; and (2) PCMCIA interface and a device or host driver.
`
`Ex. 1013 at 18–19 (citing structures from the ’802 Patent at 7:60–8:14).
`
`The district court tentatively found that “operably connecting” did not require
`
`construction and then agreed with Patent-Owner’s proposed function and
`
`corresponding structures. Id. The district court tentatively determined, however,
`
`that the plain language of the “operably connecting” language requires two of the
`
`three following modes to be available: (i) a security and target mode; (ii) a security
`
`or target mode; and (ii) a combination of all three possible modes. Id.at 23;
`
`Markman Hearing Transcript, Ex. 1017, at 37–38.
`
`10
`
`

`

`
`
`H.
`
`“means for mediating communication of data between the host
`computing device and the target means so that the communicated
`data must first pass through the security means” (Claims 1–2, 11–
`12, 23)
`This means-plus-function term’s function is “mediating communication of
`
`data between the host computing device and the target means so that the
`
`communicated data must first pass through the security means.”
`
`Patent-Owner proposed that the corresponding structure is: (1) a field
`
`programmable gate array (FPGA); and (2) interface control device 910 (as shown in
`
`Figure 9B). Ex. 1013 at 20. If an algorithm is necessary for the FPGA, Patent-
`
`Owner asserts that the algorithm is (1) receiving data from host computing device;
`
`(2) depending on configuration settings, providing data to be processed by a
`
`cryptographic processor; and (3) transferring data to target means. Ex. 1013 at 20
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`(citing ’802 Patent at Fig. 9A, 16:58–17:7).
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`The district court tentatively agreed with Patent-Owner’s proposed function,
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`but rejected that the FPGA was a corresponding structure. Ex. 1014 at 24–25.
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`Instead, the district court tentatively found that the corresponding structure is
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`interface control device 910 (as shown in Figure 9B). Id.
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`I.
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`“means for providing to a host computing device, in response to a
`request from the host computing device for information regarding
`the type of the peripheral device, information regarding the
`function of the target means” (Claims 6–7, 23–25)
`This means-plus-function term’s function is “providing to a host computing
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`device, in response to a request from the host computing device for information
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`regarding the type of the peripheral device, information regarding the function of the
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`target means.” Patent-Owner asserts that the corresponding structure is memory
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`section 612a. Ex. 1013 at 23 (relying on ’802 Patent, Ex. 1001, at 7:60–8:14). The
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`district court tentatively found, however, that the term is invalid for indefiniteness.
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`Ex. 1014 at 30.
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`J.
`“means for non-volatilely storing data” (Claims 2, 12, 25)
`This means-plus-function term’s function is “non-volatilely storing data.”
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`The parties in the DCT Litigation agreed that the corresponding structure is “non-
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`volatile memory devices” based on 13:27-29 and 16:10-12. Ex. 1016, at Page 5.
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`VI. THE PRIOR ART RENDERS OBVIOUS CLAIMS 1–2, 6–7, 11–12, 23–
`25, 38–39 OF THE ’802 PATENT
`Under 35 U.S.C. § 103, a patent claim is obvious and invalid “if the
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`differences between the subject matter sought to be patented and the prior art are
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`such that the subject matter as a whole would have been obvious at the time the
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`invention was made to a person having ordinary skill in the art to which said subject
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`matter pertains.” Multiple pieces of prior art along with the general knowledge of
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`those of ordinary skill in the art render the challenged claims of the ’802 Patent
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`obvious. Randall Mfg. v. Rea, 733 F.3d 1355, 1362 (Fed. Cir. 2013).
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`Each challenged claim, where the prior art teaches or suggests each element
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`of the claim and why a person of ordinary skill would have been motivated to modify
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`the base reference as outlined in the obviousness combination, is discussed below
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`with citations to the Declaration of Dr. Martin Kaliski, Ex. 1015.
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`Brackets are used to identify claim elements (e.g., “[1C]”) and claim numbers
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`(e.g., “[2]”).
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`A. Cited Prior Art
`1. Harari
`Harari describes a “peripheral in the form of a PC card that can be removably
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`connected to a host system.” Harari, Ex. 1004, 3:9–12. Harari teaches that “[t]he
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`externally removable PC card is constituted from a mother card portion and a
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`daughter card portion. The daughter card portion is removably coupled
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`mechanically and electrically to the mother card by means of a mother/daughter
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`interface.” Id. at 3:50–54. An overall objective in Harari is to separate portions of
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`a peripheral that are common to all or many peripherals from the portions that are
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`necessarily unique in each peripheral. Harari, Ex. 1004, 3:50–4:33, 3:61–5:6.
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`Figure 1, below, shows a schematic of the mother/daughter PC card and its
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`connectivity with a host computer.
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`
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`Id., Fig. 1. “Partitioning the externally removable PC card into a mother card and
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`daughter card portion allows the functional components of a peripheral . . . to be
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`advantageously partitioned.” Id. at 3:60-63.
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`Figure 3, below, shows the partitioning of components for a flash EEPROM
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`system between the mother card and the daughter card:
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`
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`
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`Id., Fig. 3. The daughter card, as illustrated in Figure 3, provides memory
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`functionality; Harari teaches that it can also provide other functionalities such as “a
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`modem[,] other communication peripherals such as [a] LAN adapter, or wireless fax
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`modem.” Id. at 4:65–5:1; id. at 8:40–45 (identifying additional peripheral
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`functionality such as a “modem or other communication peripherals”). To identify
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`the type of daughter card, “the removable daughter card has identifying data that is
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`readable by the mother card or the host system coupled thereto.” Id. at 5:38–40.
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`While daughter cards provide a variety of functionality, the mother card
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`provides general functions beneficial to each daughter card. Harari explains that the
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`“mother card portion contain[s] the common functional components of a number of
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`peripherals.” Id. at 4:22–25. To achieve this, the mother card can include “one or
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`more functional modules” as illustrated in Figure 5B and reproduced below. Id. at
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`8:58–60.
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`
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`
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`“The functional module 42 may provide error detection and correction, encryption
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`and decryption, compression and decompression of data, image, audio and voice, as
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`well as other features useful in the mobile computing environment.” Id. at 8:60–64.
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`The mother card, daughter card, and host system each contains connectors that
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`enable each part to communicate with the others. “The daughter card 10 has an edge
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`connector 24 and it directly plugs into the mother card by mating with the connector
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`14 on the mother card.” Id. at 7:4–6. The mother card contains a memory controller
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`40 that “interfaces with the host system via a host interface 54, and with the flash
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`memory via a memory interface 56.” Id. at 7:37–54. “In the preferred embodiment,
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`the host interface 54 communicates with the host system 200 in accordance with
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`PCMCIA specifications or any other standard card interface.” Id. at 7:54–57.
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`2. PCMCIA System Architecture: 16-Bit PC Cards (1995)
`PCMCIA was developed to create a standard PC Card interface. PCMCIA
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`System Architecture: 16-Bit PC Cards by Don Anderson, Ex. 1006, was published
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`in 1995 and provides instructional information on implementing the PCMCIA
`
`Standards. The book “is intended for use by hardware and software designers and
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`support personnel” who are implementing PCMCIA Standards. PCMCIA System
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`Architecture, Ex. 1006, at 6.
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`PCMCIA System Architecture provides an overview of the development of
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`and purposes for the PCMCIA Standards. “PCMCIA was formed to promote the
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`standardization and interchangeability of PC Cards” and “defines the following
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`major issues: [p]hysical design of the PC Card, [p]hysical design of the connector
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`(socket), [e]lectrical interface to PC Cards, [and] [s]oftware architecture.” PCMCIA
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`System Architecture, Ex. 1006, at 14–15. PCMCIA can be used to implement “a
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`wide range of memory and I/O devices. Memory devices include RAM, FLASH
`
`memory and various types of ROM.” Id. at 15. An even greater array of I/O devices
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`exist including: “voice, data and FAX modems; network interface cards; wireless
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`communications . . . ; AT Attachment (ATA) Hard Drives . . . ; small computer
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`system interface (SC