IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`Applicants:
`
`Ravindraraj Ramaraju, David R. Bearden, Wilham C. Moyer
`
`Assignee:
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`Freescale Semiconductor, Inc.
`
`Title:
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`Moalt-Core System On Chip
`
`Serial No.:
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`12/648,311
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`Filed:
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`November 13, 2009
`
`Exammer:
`
`Kenneth Tang
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`Group Art Unit:
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`2199
`
`Docket No.:
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`NM45703HH
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`Customer No.:
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`53364
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`Filed Electronically
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`December 28, 2012
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`AMENDMENT AND RESPONSE TO FINAL OFFICE ACTION
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`This paper is responsive to the Office Action dated October 12, 2012, having a shortened
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`statutory period expirmg on Decermber 12, 2012. Further oxamination and reconsideration are
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`respectfully requested in view of the amendments and remarks set forth below.
`
`1
`
`INTEL 1011
`INTEL 1011
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`

`

`
`AMENDMENTS TO THE CLAIMS
`
`1.
`
`(Previously Presented)
`
`A method for operating a multi-core processing
`
`device, comprising:
`
`moasuring a processing speed parameter for each of a plurality of cores;
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`storing cach measured processing speed parameter for each ofthe plurality of cores in a
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`storage device; and
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`upon identifying a processing task that can not be run by the plurality of cores, selecting 4
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`core from the plurality of cores having a fastest measured processing speed parameter to run the
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`processing task.
`
`2.
`
`(Original
`
`The method of claini 1, where measuring the processing speed
`
`parameter comprises measuring a maximum operating frequency parameter for each of the
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`pluralityof cores.
`
`3.
`
`(Original)
`
`The methodof claim 1, where measuring a processing speed
`
`parameter comprises periodically measuring the processing speed parameter on a predetermined
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`basis,
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`4.
`
`(Original
`
`The method of claim 1, where measuring the processing speed
`
`parameter comprises measuring a maximumoperating frequency parameter for cach ofthe
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`plurality of cores using a critical path monitoring circuit located at each core.
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`5.
`
`(OriginaD
`
`The method of claim 1, where storing cach measured processing
`
`speed parameter comprises storing cach measured processing speed parameter in a device control
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`register,
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`6.
`
`(Original)
`
`The method of claim 1, where storing cach measuredprocessing
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`speed parameter comprises tagging each core with a corresponding measured maximum
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`operating speed parameter.
`
`7.
`
`(Original)
`
`The method of claim 1, where an operating system selects the core
`
`having the fastest measured processing speed parameter to run the processing task,
`
`

`

`&.
`
`(Original
`
`The method of claim 1, where the multi-core processing device is
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`constructed on a single integrated circuit system on a chip.
`
`&,
`
`(Original
`
`The method of claim 1, where moasuring the processing speed
`
`parameter for each of the plurality of cores comprises:
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`measuring afirst processing speed parameter for each of the plurality of cores operating
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`with a first operating supply voltage; and
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`measuring a second processing speed parameter for each ofthe plurality of cores
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`operating with a second operating supply voltage that is different fromthe first operating supply
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`voltage.
`
`10.
`
`(Original)
`
`A multi-core system on chip (SOC), comprising:
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`a plurality of cores, each core comprising a performance measurement circuit for
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`measuring a performance parameter value for said core; and
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`at least a first storage device for storing the performance parameter values for the
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`plurality of cores for use in selecting a core having maximized or minimized performance
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`parameter value to run a processing task that can not be run by the phurality of cores,
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`il.
`
`(Original
`
`The multi-core SOC of claim 10, where the performance
`
`measurement circuit at each core comprises a critical path monitoring (CPM)circuit.
`
`12.
`
`(Original)
`
`The multi-core SOC of claim 10, where the first storage device
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`comprises a device control registry located at a first core.
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`13.
`
`(Original)
`
`The multi-core SOC of claim 10, where the first storage device
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`comprises a device control registry which stores a core identification value and a measured
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`maximumoperating frequency value for cach core.
`
`14.
`
`(Original)
`
`The multi-core SOC of claim 10, where thefirst storage device
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`comprises a device control registry which stores, for cach core, a core identification value, a
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`moasured maximum operating frequency value and a corresponding operating voltage value.
`
`=]
`
`

`

`15.
`
`(Original
`
`The nmilti-core SOC of claim 10, where the plurality of coresall
`
`share a common external voltage supply.
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`16.
`
`(Original)
`
`The nmilti-core SOC of claim 10, where a plurality of external
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`voltage supplies are provided to the plurality of cores.
`
`17,
`
`(Original
`
`The multi-core SOC of claim 10, where cach of the plurality of
`
`cores comprises a core-specific clock circuit for applying a clock multiplier value to a received
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`clock reference signal.
`
`18.
`
`(Original)
`
`The multi-core SOCof claim 10, where the at least a first storage
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`device stores a maximumoperating frequency value for each of the plurality of cores for use in
`
`selecting a core having the fastest maximumoperating frequencyvalue to run the processing task
`
`that can not be run bythe plurality of cores.
`
`19,
`
`(Original
`
`The multi-core SOCof claim 10, further comprising control logic
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`for selecting a sub-plurality of cores to run a processing task that can not be run bythe plurality
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`of cores by using the performance parameter values to identify the fastest sub-plurality ofcores.
`
`20.
`
`(Original
`
`Ina multi-core processor comprising multiple cores which are
`
`controlled by system logic, a method for executing single core applications and multi-core
`
`applications comprising:
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`measuring a maximum processing speed value for each of the multiple cores for at least a
`
`first operating voltage value;
`
`storing cach measured maximum processing speed value for each of the multiple cores;
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`running a multi-core application on a plurality of the multiple cores by contrallmg each
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`of the plurality of the multiple cores to run at a speed whichis identified fromthe stored
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`maximumprocessing spoed values to be the slowest maximumprocessing speed of the plurality
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`of the multiple cores; and
`
`running a single core application on a single core whichis identified fromthe stored
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`maximum processing speed values for the multiple cores as berg the fastest core.
`
`

`

`21.
`
`(Original
`
`The method of claim 20, where storing cach measured maximum
`
`processing speed value comprises storing cach measured maximumprocessing speed value for
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`each of the multiple cores in a device control registry along with an operating voltage value at
`
`which the maximum processing speed value is measured.
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`22.
`
`(Currently Amended) The method of claim 20 [[19]], where storing each
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`measured maximamprocessing speed value comprises storing cach measured maximum
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`processing speed value for each of the multiple cores in a device control registry along with an
`
`operating voltage value at which the maximum processing speedvalue is measured.
`
`as
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`

`

`REMARKS
`
`tn the Office Action dated October 12, 2012, claims 1-8, 10-13, 15-20, and 22 were
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`rejected under as obvious over a number ofreferences, inchiding primary reference U.S. Patent
`
`Publication No. 20090055826 to Bernstein et al, Pursuant to 37 C\F.R. § 1.116, Applicants
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`respectfully request that the amendment presented herein be entered to place the claims tn better
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`form for consideration on appeal or otherwise place the application in condition for allowance
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`
`Consideration of Reponses After Final Rejection under 37 CFR $1.116(b} under the After Final
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`ConsiderationPilot(AFCP) (April 2012).
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`In particular, Applicants have amended claim 22 to
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`clarify a typographical error and clarify the plainly understood dependencyto claim 20. To the
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`extent that the amendment to claim 22 appears to conform to the Examiner’s understanding of
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`the claim, Applicants submit that amendment requires only a limited amount of further
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`consideration or search, and therefore should be entered and considered.
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`As for the rejection of claims over the base combinations of Bernstein and Ghiasi (claims
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`20) or Bernstein and Kim, alone (claims 1-8, 10-13, 16, and 18} or in combination with four
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`other cited references (namely, Wang (claim 15), Chu (claim 17), Vestal (claim19), and Vestal
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`and Ghiasi (claim 22}}, Applicants respectfully request that the rejection be reconsidered and
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`withdrawn because the Examiner has fundamentally misunderstood the requirements ofthe
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`claims and/or mischaracterized the disclosure of the cited art.
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`In support of this request,
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`Applicants would note that the Examiner cites Bernstein’s disclosure (Bernstein Fig. 2, Abstract,
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`and paragraphs 3-4, 11, 16-17, 29-30, and 33) forits teaching of “identifying cores that have a
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`sleep/idie state such that tasks cannot be run,” and upon conceding that “Bernstein does not
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`specifically teach identifying a processing task that cannot be run by a plurality of cores,” the
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`Examinerasserts that the missing claim requirements are met by Kim’s disclosure (Kim,
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`With this rejoction analysis, the Examiner mischaracterizes claims 1-19 as requiring “identifying
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`cores that have a sleep/idie state suchthat tasks cannot be run.” See, Office Action, pp. 3 and 5.
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`There is simply no such requirement recited, and claims 1-19 are not directedto identifying
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`sleeping tasks as tasks that cannot be run on multiple cores. Instead, Applicants have plainly
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`disclosed and claimed a method and multi-core system of chip which identifies a processing task
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`

`

`that cannot be executed across a plurality of cores so that tasks that cannot run across multiple
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`processors (single-core tasks} are confined to not do so:
`
`sing data structure 216, the
`[O20] Usingthe information in the DC
`R 215/ta
`
`
`
`operatingsystemcanrunajobthatcannotbedistribuledacrossmultiplecoresbyfirst
`eading the DCR215 to identify the core having the fastest Fmax value, and then sending
`the job to the core tagged with the highest operating frequency, thereby onabling the
`identified core to operate at its maximumoperating frequency for the sare nominal
`
`voltage. This approach allows single core applications to have improved performance by
`runningontheSoC’sfastestavailablecore. The improved performance may be obtained
`
`without significantly increasing the power consumption. This results from the fact that
`static powerleakage 1s the same across all cores, regardless of operating frequency, and
`can be the dominant component of power consumption as comparedto the dynamic
`power. As a result, the operation of the fastest core changes only the dynamic power, not
`the static power, so there is no substantial power increase by running the single core
`application through the fastest core.
`
`[022] Figure3dlustratesaflowdiagram300fortheoperationofamulli-core
`processor system which performs iobs that can not be distributed across multiple cores by
`sendingthe job to the core having the highest operating frequency. Cince the sequence
`
`
`begins at step 301, the critical path monitoring (CPM) circuit is used to measure each
`core to determine or estimate the maximum operating frequency (MOF) at a given
`voltage (step 302).
`In selected embodiments, the measurement step 302 may be repeated
`to obtain MOF values for different operating voltage or performance classes so that a low
`voltage MOFand high voltage MOFare obtained. Additional or other performance
`parameters can be measured by the CPMcircuit to assist with evaluating and selecting a
`core for running an application, task, or job. At step 303, cach core is tagged with tts
`maxinium operating frequency (MOF) value. The tagging may be accomplished by
`storing the MOF value in one or more device control registers that can be read by the
`operating systern when deciding howto distribute the work load.
`[023] Subseguently at step 304,
`the operating systemassesses a particular
`
`
`
`305), the operating system assigns the application/task to the appropriate cores for
`execution (step 306), after which the sequence returns to evaluate the next
`application/task (step 304). However,iftheapplication/taskcannotmakeuseof
`
`multiple cores (negative outcome to decision 305),
`the operating systern identifies core
`havingthe highest MOFvalue at step 307. This may be accomplished by accessing the
`device control regisiry(s) to determine which core identifier has the highest MOF value
`ard is available for use (though the availability determination may be made separately}.
`At step 308, the operating system assigns the application/task to the identified core
`having the fastest speed for execution, after which the sequence returns to evaluate the
`ext application/task (step 304}.
`
`See, Application, paragraphs 20, 22-23 (emphasis added).
`
`

`

`In short, the rejection analysis argument -- that a sleeping task is a task that cannot be run
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`on multiple cores -- misses the pomt entirely. This is seen quite plainly fromthe claim
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`requirement of “selecting a core from the plurality of cores having a fastest measured processing
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`speedparameter to run the processing task.” See, claim 1 (ernphasis added}. Underthe
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`Examiner’s interpretation, the fastest core is selected to run a sleeping task. Applicants
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`respectfully submit that a person having ordinaryskall in the art would not viewthe claim
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`requirernent or the cited art disclosure in this way. Since the claims do not require selection of a
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`core having the fasted measured processing speed to run a sleeping task, and since the cited art
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`references fail to disclose or suggestion identifying tasks “that cannot be ran bythe plurality of
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`cores” and assigning such single-core tasks to the fastest core, Applicants respectfully submit
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`that a prima_facie case of obviousness has not been established because the rejection analysis
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`does not make “a searching comparison of the claimed invention — including all its limitations ~
`
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`with the teaching of the prior art.” In re Ochiai, 71 F.3d 1565, 1572 (Fed. Cir, 1995) (emphasis
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`added). Because ofat least these defictencies, Applicants respectfully request that the
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`obviousness rejection of claims 1-8, 10-13, 15-20, and 22 be reconsidered and withdrawn, and
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`that the claims be allowed.
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`CONCLUSION
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`In view of the amendment and remarks set forth herein, Applicants respectfully request
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`that the armendment be entered, and subrmut that all pending claims are in condition for
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`allowance. Accordingly, Applicants request that a Notice of Allowance be issued. Nonetheless,
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`should any issues remain that might be subject to resolution through a telephone interview, the
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`Examiner is requested to telephone the undersigned at 512-338-9100,
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`Reg. No. 34,791
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`CERTIFICATE OF TRANSMISSION
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`that on December 28, 2012. this correspondence
`Thereby c¢
`is being transmitted via the US. Patent & Tr.
`rk Office’s
`electronic filing system.
`/Michael Recca Cannatti/
`
`Respectfully submitted,
`
`‘Michael Rocca Canmattt/
`
`Michael Rocco Cannatti
`Attorney for Appheants
`
`