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`Portland, Oregon, USA
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`' August 27-29, 2007
`Computing Machinery
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`Association for
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`28/92/98
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`’ August 27—29, 2007
`Computing Machinery
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`ti’ortland, Oregon, U
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`Association for
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`Advancing Computing as a Science & Profession
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`Association for
`Computing Machinery
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`Advancing Computing as a Science & Profession
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`Table of Contents
`
`ISLPED 2007 Organization................................................. xi
`
`Program Committee ........................................................................
`
`........................................... xii
`
`Sponsors &Supporters................ xv
`2006 Design Contest Winners .....
`.......................................
`.................xvi
`
`Keynote
`
`. Nanotechnology for Low-Power and High-Speed Nanoelectronics Applications ................... 1
`Robert Chau (Intel)
`
`Session 1: Emerging Device Technologies for Low Power
`Session Chair: Yehia Massoiid (Rice University
`Co-Chair: Chn's Kim (Universig/ ofMinnesota)
`
`'
`
`. CompactMcdeling of Carbon Nanotube Transistor
`for Early Stage Process-Design Exploration ....................
`Ash'a Balijepalli. Sautabh Sinha. Yu_ Cao (Arizona State University)
`
`............................................................... 2
`
`’- A Floating-Body Dynamic Supply Boosting Technique
`for Low-Voltage PDISOI CMOS SRAM in Nanoscale
`Rajiv Joshi, Rouwaida Kanj, Kcunwoo Kim, Richard Williams, Ching-Te Chuang (IBM)
`
`..... 8
`
`- Low Power FPGA Design Using Hybrid CMOS-NEMS Approach ...........................................
`Yu Zhou, Shijo Thekkel, Swamp Bhunia (Case Western Reserve University
`
`14
`
`- Design and Analysis of Thin-BOX FDISOl Devices
`for Low-Power and Stable SRAM in sub-50nm Technologies. ................................................... 20
`Saibal Mukhopadhyay, Keunwoo Kim Citing-Te Chuang flBM TJ. Watson Research Center)
`
`0 Clocking Structures and Power Analysis for Nanomagnet—Based Logic Devices ................ 26
`M. T. Niemicr,.'X. S. Hu. M. Alain. G. Bernstein, W. Porod, M. Pumey, I'DeAngelis
`(University afNotre Dame)
`
`Session 2: Power-Efficient CMP Design
`Chair: Massimo Poncino (Polirecnico di Tarina)
`Co-chair: Qing Wu (State University ofNew York at Binghamton)
`
`. Energy Efficient Near-threshold Chip Mum-processing ................................................................ 32
`B0 Zhai, Ronald G- Dreslinski, DavidBlaauw, Trevor Mudge, Dennis Sylvester (University ofMichigan)
`
`- Analysis of Dynamic Voltage/Frequency Seating”In Chip-Multiprocessors............................38
`Sebastian Herbert, Diana Marculescu (Carnegie Mellon University)
`a Evaluating Design Trade-offs in On-Chip Power Management for CMPs44
`Joseph Shaficey.(Assured Information Security, Inc),
`Alper Buyuktosunoglu, Pradip Bose HEM TJ. Watson‘Resez'zrch Center)
`
`0
`
`impact. of Die-to-Die and Within-Die Parameter'Variations
`on the Throughput Distribution of Multi—Core Processors ............................................................ 50
`KeithA. Bowman, Alaa R Alameldecn, Srikanth T. Srinivasan, Chris B. Wilkerson (Intel Carporanon)
`
`. A Reusability-Awar'e Cache Memory Sharing Technique
`for High-Performance Low-Power CMPs with Private L2 Caches ...........................
`Sungjune Youn (LG Electronics Inc), Hyunhee Kim, Jihong Kim (SeoulNalionnl UniVersity)
`
`.......... 56
`
`
`
`7 M (Q [2%.]:
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`[0 My} 25»?
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`[Page 50f10]
`[Page 5 of 10]
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`Session 3: Low—power Techniques for Logic,
`Clock Distribution, and interconnect
`Chair: Brian Otis {University of Washington)
`Co~chair: Saibai Mukhopadhay (IBM)
`
`Dual Signal Frequencies and Voltage Levels for Low Power
`and Temperature-Gradient Tolerant Clock Distribution ................................................................ 62
`Sherif A. Tawfik, Voikan Kursun (University of Wisconsin-Madison)
`
`A Robust Edge Encoding Technique for Energy-Efficient Multi-Cycie interconnect ........... 68
`Jaeesun Sec, Dennis Syither. David Blaauw (University ofMichigan),
`Himanshu Kaui, Ram Kn’shnamurthy (Intel Corporation)
`
`Low-Power Process-Variation Tolerant Arithmetic
`
`Units Using input-Based Elastic Clocking ......................................................................................... 74
`chabrata Mohapatra, Georgios Karakonstantis Kaushik Roy (Purdue University)
`
`Sleep Transistor Sizing and Control for Resonant Supply Noise Damping ............................ 80
`lie Gu Hanyong Eom, Chris H. Kim (University ofMinnesota)
`'
`
`Thermal-Aware Methodology for Repeater insertion in Low-Power VLSi Circuits ............... 86
`la Chun Kn, Yehea lsmaii (Northwestern University)
`
`Session 4: Power Considerations at the Physical Level
`Chair: Eli Chiprout (Intel Corporation)
`(Io—chair: Azadeh Davoodi (University of Msconsin)
`I
`
`Post-Placement Leakage Optimization
`for Partially Dynamically Reconfigurable FPGAs ............................................................................ 92
`Chi—Fang Li, Ping-Hung Yuh, Chin-Lin Yang. 3’30.ch Chang (National Taiwan Universizy)
`
`Power Optimal MTCMOS Repeater insertion for Global Buses .................................................. 98
`Hanif Fatemi, Behnam Ameiifard, Massoud Pedram (University ofSouthern California)
`.
`
`Timing-Driven Row-Based Power Gating ......................................................................................... 104
`Ashoka Sathanur. Antonio Puliini (Politecnico di Torino), Luca Benini (Universitd di Bologna),
`Alberto Macii, Enrico Macii, Massimo Pcucino (Politecnico di Torino)
`
`Detailed Placement for Leakage Reduction
`Using Systematic Through-Pitch Variation ..................................................................................... 110
`Ancircw B Kahng Swamy Muddu, Puncet Shanna (University ofCalifornia at San Diego)
`
`Early Power Grid Verification Under Circuit Current Uncertainties...
`Imad A Fcrzii Farid N. Najm (University ofTammo) Lars Krusc (Magma Design Automation)
`
`i 16
`
`Special Session
`
`Future of On-Chip interconnection Architectures ......................................................................... 122
`Shckhar Borkar (Intel Corporation), Bill Dally (Stanford University)
`
`Session 5: Software and System Power Optimization
`Chair: Jocrg chkci (University ochzrlsruhe)
`Clo-Chair: Yiran Chen (Seagate LLC)
`0
`
`Towards a Software Approach to Mitigate Voltage Emergencies ............................................ 123
`Mecta Shanna Gupta, Krishna K. Rangan. Michael D. Smith, Gu-Yeon Wei. David Brooks (Harvard University)
`
`Improving Disk Reuse for Reducing Power Consumption ......................................................... 129
`Mahmut Kandemir, Seung Woo Son (77m Pennsylvania State University), Mustafa Karakoy (Imperial (Ellege)
`
`PVS: Passive Voltage Scaling for Wireless Sensor Networks ................................................... 135
`Youngjin Cho, Younghyun Kim, Naehyuck Chang (Seoul National University)
`
`A Programming Environment with Runtime Energy Characterization
`for Energy-Aware Applications ........................................................................................................... 141
`Changiiu Xian. Yungflsiang Lu. Zhiyuan Li (Purdue Universin»)
`
`vi
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`Session 6: Leakage-Aware Architectural Synthesis
`Chair: Ron Zhang (Qualcomm).
`Co-Chairi Yung-Hsiang Lu (Purdue University)
`
`A Process Variation Aware Law Power Synthesis Methodology
`for Fixed-point FIR filters .............................................................................................., ........................ 147
`Nilanjan Baneljcc, Jung Hwan Choi, Kaushik Roy (Purdue UniVem‘ty)
`
`Voltage- and ABE-island Optimization in High Level Synthesis..................... ................... .. ...... 153
`Domenjk Helms, Olaf Meyer, Marko Hoyer (OFFIS Research Institute),
`Wolfgang Nobel (University afOla’enburg)
`
`Power~0ptimal RTL Arithmetic Unit Soft-Macro Selection
`Strategyfor Leakage-Sensitive Technologies......l....................V.V...V........, ............._........................ 159
`Simone Medardoni, Davide Bertozzi (ENDIF-University ofFerraro)
`Enrico. Macii (Palitecnico di Torino)
`
`Power Signal Processing: A New Perspective:
`for Power Analysis and Optimization”. ............................................................................................ 165
`Quming Zhou, Lin Zhong, Kjartik Mohanram (Rice University)
`"
`I
`
`Session 7: Low-Power Memory Design and NBTl Detection
`Chair: Gunjan Paudya (Intel Corporation)
`Co—chair: Voikan Kursun (University of Wisconsin)
`
`A 160 mV, Fully Differential, Robust Schmitt Trigger Based Sub-threshold SRAM ........... 171
`Jaydeep P. Kulkami, ‘Keejong Kim, Kaushik Roy fl’urdue University)
`
`A. Low-Power SRAM Using Bit-Line Charge-Recycling Technique..................
`Keejong Kim fl’urdue University), Hamid Mahmoodi (San Francis‘co State University),
`Kaushik Roy (Purdue University)
`
`........._.......... 177
`
`Minimizing Power Dissipation during Write Operation to Register Files................................ 183
`Kimish Patel, Wonbok Lee, Massoud Pedrarnvmrtiversity ofSouthern Calg’omia)
`
`‘An Orr-Chip NBTI Sensor for Measuring PMOS Threshold Voltage Degradation ................ 189
`John Keane, Tat-:«Hyoung’Kim, Chris H. Kim (University ofMinnesota)
`
`Variable-latency Adder (VL-Adder):
`New Arithmetic Circuit Design Practice to Overcome NBTl ............................................ , .......... 195
`Yirau Chen, Hai Li (Seagc‘z't'e Technology), Jing Li, Cheng-Kok Koh (Purdue Universig)
`
`Session 8: DVS and Thermal Management
`Chair: Zhijian Lu (Marvell Semiconductors)
`Co~chair: Jun Yang Wuiversity ofPittsburgh)
`
`Throughput of Multi-core Processors Under Thermal Constraints ......................................... 201-
`Ravishankar Rae, Sauna Vrudhula, Chaitaii Chakrabarti (Arizona State University)
`
`Dynamic Voltage Frequency Scaling
`for MuitI-tasking Systems Using Online Learning...». ..................................................................... 207
`Gaurav Dhiman, Tajana Simunic Rosing (Universfw of California, San Diego)
`
`Thermal-Aware Task Scheduling at the System Software Level .....-.....21'3
`Jcongbwan Choi, Chcn-Yong Cher Huhcrtus Franks, Hendrik Hamann‘, Alan Wager, Pradip Bose
`(IBM TJ Watson Research Center)
`
`Thermal Response to DVFS: Analysis with an Intel Pentium M .................... . ........................... 2'19
`Heather Hanson. Stephen W. 'Keckler (The University ofTexas, Austin),
`Soraya Ghiasi, Karthick Rajamani, Freeman 'Raw‘son, Juan Rubio (IBMAustin Research Laboratory)
`
`Approximation Algorithms for Power Minimization
`of Earliest Deadline First and Rate Monotonic Schedules.225
`Sushu Zhang Karam S. Chatha, Goran Konjevod (Arizona State University)
`
`Vii
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`Plenary l
`
`- The Parailel Computing Landscape: A Berkeley View ........v......................................................... 231
`David Patterson (University ofCalifiimia, Berkeley}
`
`Session 9: Signal Processing, Wireless, and Communication
`Chair: Chaitali Chakrabarti (Arizona State University)
`Co-chair: Farzan Fallah (Fijutsu Laboratories)
`
`. Low Power Soft-Output Signal Detector Design
`for Wireless MiMO Communication Systems ................................................................................. 232
`Sizhong Chen, Tong Zhang (Renrselaer Polytechnic Institute)
`
`. A Low Power Multimedia 506 with Fully Programmable 3D Graphics
`and MPEG4IH.264IJPEG for Mobile Devices ................................................................................... 238
`lacing-Ho Woo, Ju—Ho Sohn, Hyejung Kim (KAISD.
`Jongcheol Jeong. Euljoo Jsong, SukJoong Lee (Corelogic, Inc), Hoi~Jun Yoo (KAISY)
`
`x
`’
`. An Architecture For Energy Efficient Sphere Decoding ....................................................._. ........ 244
`Ravi Jenkal, RhettDavis Worth Carolina State University
`
`. On the Seiection of Arithmetic Unit Structure
`in Voltage Overscaled Soft Digital Signai Processing ................................................................. 250
`Yang Liu, Tong Zhang (Rensselaer Polytechnic Institute)
`
`. Low-power H.264IAVC Baseline Decoder for Portable Applications ....................................... 256
`Kc Xu, Chit-l Sing Choy (The Chinese University ofHong Kong)
`
`Session 10: Architectural Power Optimization
`Chair: Geoffrey Yeap (Qualcomm)
`(Jo-chair : Yu Cao (Arizona State University)
`
`. A 0.4-V UWB Baseband Processor .................................................................................................... 262
`Vivienne Sze, Anantha Pi Chandrakasan Massachusetts Institute ofTechnology)
`
`. Resource Area Dilation to Reduce Power Density in Throughput Sewers ........................... 268
`Michaei D. Powell (Intel Massachusetts, Inc. and Purdue Universfbi), T. N. Vijaykumar (Purdue University)
`
`. Locality-Driven Architecturai Cache Sub-banking for Leakage Energy Reduction......,.....274
`Olga Gclubcva. Mirko Loghi, Enrico Macii, Massimo Poncino (Palitecnico di Torino)
`
`- A Multi-Model Power Estimation Engine for Accuracy Optimization ...................................... 280
`Felipe Klein, Guido Araujo dustitute of Computing, UNICAMP). Rodolfo Azevedo (UNICAMP),
`Roberto Leao, Luiz C. V. Santos (UFSC)
`
`Session 11: DCIDC Converters
`Chair: William Li (Intel)
`Couchair: Domine Lccnaerts (NXP)
`
`. A Fast-Transient Over—Sampled Delta-Sigma Adaptive
`DC—DC Converter for Power-Efficient Noise-Sensitive Devices.......;........................................ 286
`Minkyu Song. Dongsheng Ma (The University ofArizona)
`
`. High-Efficiency Synchronous Dual-Output Switched-Capacitor
`DC-DC Converter with Digital State Machine Control .................................................................. 292
`Shiming Han, Xiaobo Wu (Zhejiang University. Yang Lin (Analog Devices, Inc)
`
`— A Micro Power Management System and Maximum Output
`Power Control for Solar Energy Harvesting Applications .......................................................... 298
`Hui Shae. Chi—Ying Tsui, Wing—Hung Ki (The Hong Kong University ofScience and Technology)
`
`viii
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`Advanced Thermal Sensing Circuit and Test Techniques Used
`in a High Performance 65nm Processor.........
`...................................................... 304
`David E. Duane, Greg. Taylor, Kong L. Wong, ‘Usrnan A. Mughal, George L. Gcannopoulos
`(Intel Corporation)
`
`Single inductor, Multiple Input, Multiple Output (SIMIMO)
`Power Mixer-Charger-SupplySystem........................................ 310
`Min Chen, Gabriel A. RjnconaMor‘a (Georgia Institute of Technology)
`
`Session 12; Energy and Power Delivery
`Chair: Nemani Mahadev (Intel Corporation)
`Co-chair: Swamp Bhunia (Case Westem University)
`Vibration Energy Scavenging and Management for Ultra Low Power Applications ..........316
`Lu Chao, C’hi-Ying Tsui, Wing-Hung Ki (Hong Kong University ofScience'ond Technology)
`Energy Management of DVS-DPM Enabled Embedded Systems Powered
`by Fuel Cell—Battery Hybrid Source ...................,.................................................................................. 322
`y
`!
`Jianli Zhuo, Chaitali Chakrabarti (Arizona Slate University,
`Naehyuck Chang (Seoul National Universioz)
`
`Design of an Efficient Power Delivery NetWork
`in'an Soc-to Enable Dynamic Power Management...;....». ........,......» 328
`VBchnam Amelifard, Massoud Pedram.(University ofSouthern California)
`Energy-Efficient and Performance-Enhanced Disks Using Flash-Memory Cache..............334
`Jen~Wci Hsich (National Chiayi University), Tei—Wci Kuo, Po-Liang Wu (National Taiwan Unil'zersity).
`Yu-Chung Huang (Genesys Logic, Inc.)
`
`SAPP: Scalable and Adaptable Peak Power Management in NoCs...,....................................... 340
`Pravden S. Bhojwani, Jason D. Lee, Rabi N. Mahapatra (Tera: A&M.University)
`
`Plenary II
`All WattsConsidered.....................346
`Luiz AndréBanoso (Gaogle)
`
`Posters
`
`Av65-nm Pulsed Latch with a Single Clocked Transistor
`Martin Saint—Laurent, Baker Mohammad, Paul Bassett (Qualcommlnc)
`
`..... 347
`
`A Methodology for Analysis and Verification
`of Power Gated Circuitswith Correlated Results ...................................................................
`Aveek Sarkar, Sheri Lin. Kai Wang (Apache Design Solutions)
`
`.
`...... 35.1
`
`Vl‘ Balancing and Device Sizing TOWards High Yield
`of Subethreshold Static Logic Gates;...........
`.................................................................................. 355
`'Yu Pu (Technische Universiteit Eindhouen, NMJ Research Eindhoven andNational Univeroig' ofSingapore),
`José Pineda do Gy'vcz. (Technische Universiteit Eindhaven and NXP Research),
`Honk Corporazl (Technische Universiteit Eindhoven), Yajun Ha (National University ofSingapore}
`
`.......»........-
`Power-Efficient LDPC Code Decoder Architecture ......
`Kazunori Shimizu, Nozomu Togawa, Takeshi Ikenag‘a, Satos'hi Goto (Wasedo University
`
`A Low-Power CSCD Asynchronous Viterbi Decoder for Wireless Applications 363
`Mohamed Kawokgy‘ C, André T. Salama (University ofTaranto)
`
`Reddcing Cache Energy Consumption by Tag Encoding
`in Embedded Processors .............................................................
`Mingming Zhang Xiaolao. Chang, Ge Zhang
`(liutimte ofComputing Technology, Chinese Academy ofSciences)
`
`.............
`
`.............p.367
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`. On Reducing Energy-Consumption by Late—inserting
`Instructions into the Issue Queue ...................................................................................................... 371
`Emic Morancho, Jose Maria Liaberia, Angst Olivé (Universital Politécnica de Catalunya)
`
`-
`
`Power—Aware Operand Delivery .......................................................................................................... 375
`Erika Gunadi, Mikko H. Lipasti (University of Wisconsin}
`
`0 On the Latency, Energy and Area of Checkpointed.
`Superscalar Register Alias Tables ..................................................................................................... 379
`Elham Safi, Patn'ck Aki, Andreas Moshovos, Andreas Veneris (University of Toronto),
`Aggeliki Arapoyiaxmi (Universigx ofA them)
`
`- Adaptive Analog Biasing -— A Robustness-Enhanced Low-Power Technique
`for Analog Baseband Design .............................................................................................................. 383
`Zhonhua Wang (N)? Semiéona‘uctors)
`
`. Slope interconnect Effort: Gate—interconnect interdependent Delay Model
`l
`‘
`for CMOS Logic Gates with Scaied Supply Voltage ...............‘. ..................................................... 387
`Myeong—Eun Hwang (Purdue Universigl), Seong-Ook Jung (Yoruei University),
`Kaushik Roy (Purdue University)
`
`. Electromigration and Voltage Drop Aware Power Grid Optimization
`for Power Gated le ................................................................................................................................ 391
`Aida Todd (University ofCalifornia, Santa Barbara), Shih~Chieh Chang (NTHU),
`Malgorzata Marek-Sadowska (University ofCaszomia, Santa Barbara)
`
`. Reducing Display Power in DVS-enabled Handheld Systems .................................................. 395
`Jung—hi Min, Hojung Cha {Yonsei University) '
`
`. V Multicasting based Topology Generation and Core Mapping
`for a Power Efficient Networks—on-Chip
`.................................................................. 399
`Balasubramanian Sothuraman, Range Vemuri (University osz'ncinnan)
`
`. Phase-aware Adaptive Hardware Selection
`for Power-efficient Scientific Computations ................................................................................... 403
`Konrad Maikowski, Padma Ragham Mahmut Kandemir, Mary Jane irwin (The Pennsylvania State Uniwnsigx)
`
`- Signoff Power Methodology for Contaotless Smartcards........................................................... 407
`Julian Mercia (STMcroeIectronics), Christian Dufaza (LZMP). Mathieu Lisart (STMicroeIectronics)
`
`. An lLP Based Approach to Reducing Energy Consumption in N06 Based CMPs ............. 411
`Ozcan Ozturk, Mahmut Kandemir, Seung Woo Son (Pennsylvania State University
`
`Author Index .............................................................................................. 415
`
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