United States Patent (19)
`Balopole et al.
`
`(54)
`
`(75)
`
`VIDEO SPLIT SCREEN TECHNIQUE
`
`Inventors: Harvey L. Balopole, Whitestone;
`Thomas H. Traynor, Lindenhurst,
`both of N.Y.
`
`(73)
`
`Assignee: Fairchild-Weston Systems Inc.,
`Syosset, N.Y.
`
`21
`
`Appl. No.: 230,182
`
`22)
`
`Filed:
`
`Jan. 30, 1981
`
`(51)
`(52)
`(58)
`
`Int. Cl. ............................................... H04N 5/22
`U.S. Cl. ..................................... 358/183; 358/180
`Field of Search ................. 358/22, 180, 181, 183,
`358/191. 1, 182, 108, 134, 140
`
`11
`(45)
`
`4,399,462
`Aug. 16, 1983
`
`
`
`56)
`
`References Cited
`U.S. PATENT DOCUMENTS
`3,982,063 9/1976 Brown et al. ....................... 358/134
`4,139,860 2/1979 Micic et al...
`... 358/183
`4,266,242 5/1981 McCoy ................................ 358/183
`Primary Examiner-John C. Martin
`Attorney, Agent, or Firm-Thomas Langer
`57
`ABSTRACT
`A technique is provided for simultaneously displaying
`on a television screen juxtaposed pictures from two
`independent image sources. The required picture com
`pression is achieved by storing analog samples of the
`video signals in an analog memory at one frequency and
`retrieving the samples at a higher frequency for display.
`A 2 to 1 picture compression is attained, for example, by
`retrieving the samples at twice the frequency at which
`they are stored.
`
`11 Claims, 5 Drawing Figures
`
`
`
`camataaf
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`U.S. Patent
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`Aug. 16, 1983
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`Sheet 1 of 3
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`4,399.462
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`U.S. Patent
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`Aug. 16, 1983
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`Sheet 2 of 3
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`4,399,462
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`IPR2018-01045
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`U.S. Patent
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`Aug. 16, 1983
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`Sheet 3 of 3
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`4,399.462
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`10
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`4,399,462
`1.
`2
`stores all the available information but, for retrieval
`from memory, addresses only selected memory loca
`VIDEO SPLIT SCREEN TECHNIQUE
`tions. This, again, results in the use of a reduced number
`BACKGROUND OF THE INVENTION
`of digitized picture samples and provides picture com
`pression dependent on the ratio of samples stored to
`This invention relates to a technique for video display
`samples retrieved.
`and more particularly to a split screen display which is
`obtained by compressing independently derived images
`Each of the above-mentioned techniques results in
`some information being lost from the detected image in
`and juxtaposing them on the screen of a television moni
`the process of compressing the picture. This is particu
`tor for simultaneous presentation.
`Several approaches are known for simultaneously
`larly aggravated, of course, in the first-mentioned
`displaying two independently derived images on the
`"chopping' approach. However, the second approach
`of eliminating selected digitized samples also can reduce
`same screen. One approach superimposes the two im
`resolution and picture quality. Futhermore, the latter
`ages. U.S. Pat. No. 3,569,966 and 4,001,499 are exem
`plary of this approach. Another approach is to juxta
`approach requires A/D circuitry and a sizeable mem
`pose the two images for simultaneous display on the
`15,
`ory which add to the complexity, cost, size and weight
`same screen. For some purposes superimposition is not
`of the apparatus yet still fail to retain in the compressed
`desirable because the resulting picture would be mean
`picture a significant portion of the detected image.
`ingless or confusing. For example, the military requires
`SUMMARY OF THE INVENTION
`a split screen display in its combat aircraft for training
`purposes. More specifically, training aircraft now em
`20
`The primary object of the invention is to provide
`ploy a television camera in the cockpit which looks out
`picture compression with a minimum loss of image
`of the windscreen at the view available to the pilot. In
`information in the displayed picture.
`addition, it has within its field of view the heads-up
`Another object of the invention is to simplify the
`display available in modern aircraft which presents
`apparatus required to generate a compressed picture.
`important information to the pilot on the surface of the
`25
`A further object of the invention is reduce the
`windscreen superimposed on the outside scene. In addi
`weight, size and cost of picture compression apparatus.
`tion to the cockpit camera, the aircraft is equipped with
`Still another object of the invention is to juxtapose
`radar. It is advantageous to the pilot, after he is back on
`two independently derived images for simultaneous
`the ground, to see the video outputs from the cockpit
`display on one screen.
`camera and the radar juxtaposed on the same screen.
`30
`Yet another object of the invention is to provide
`This enables him, as well as his instructor, to review and
`picture compression apparatus to readily combine two
`evaluate his actions and thereby learn from them.
`independently derived images in juxtaposition on a
`Picture compression of what would otherwise cover
`screen flexible enough to handle a variety of image
`the entire screen of a television monitor is obviously
`required in order to juxtapose the independently de
`SOLCCS.
`35
`In order to accomplish these and other objects of the
`rived images on one screen. One technique accom
`invention, one aspect of the invention is directed to an
`plishes the picture compression by chopping off one or
`apparatus for producing horizontal compression of a
`both sides of the picture and utilizes only the middle
`raster scan television picture comprising a source of
`portion. Just enough of each picture is eliminated so
`analog video signals; analog memory means coupled to
`that it, along with another similarly chopped picture, fit
`40
`said source for storing said video signals; timing means
`on the screen. This technique is useful when the elimi
`coupled to said analog memory means for storing said
`nated portions of the picture are relatively unimportant,
`video signals in said analog memory means at a given
`such as with separate views of the pitcher and base
`frequency and for retrieving the stored video signals
`runner in a televised baseball game. The compressed
`from said analog memory means at a frequency higher
`picture eliminates part of the baseball field and other
`45
`than said given frequency for input to a television moni
`fielders from each picture but retains the most interest
`ing elements, namely the pitcher and baserunner. How
`tor.
`The compressed picture thus produced can be used to
`ever, for some cases such as in the combat aircraft envi
`juxtapose two independently derived images on one
`ronment discussed by way of example above, the entire
`screen. For example, each image can be compressed by
`picture is significant and, therefore, picture compres
`50
`two so both will have room on one screen. The inven
`sion must be accomplished in some other manner. One
`tion thus further involves synchronization of the two
`solution has been to selectively eliminate the video
`sources, and control of the retrieval of stored samples
`information for a selected number of points along the
`such that one compressed picture appears for each first
`raster scan line. U.S. Pat. No. 4,134,128 generates a
`half of a scan line and the other compressed picture
`given number of samples of the received analog televi
`55
`appears for the second half of the scan line.
`sion signal for conversion to digital form and subse
`quent storage in a digital memory. The stored informa
`BRIEF DESCRIPTION OF THE DRAWINGS
`tion is then recalled and displayed. To compress the
`picture, every other sample of the digitized picture, for
`FIG. 1 is a block diagram depicting the preferred
`example, is eliminated and consequently not written
`embodiment of the invention.
`FIG. 2 is a timing diagram which symbolically de
`into the memory. Thus, when the stored information is
`picts the storing and retrieval of image samples by the
`clocked out of the memory at the normal rate, a 2 to 1
`picture compression is achieved. U.S. Pat. No.
`circuit of FIG. 1.
`4,152,719 and published U.K. pat, application Ser. No.
`FIG. 3 is a block diagram showing the master control
`2,016,857 disclose alternative techniques for selectively
`block of FIG. 1 in greater detail.
`65
`storing less information than is available. Retrieval from
`FIG. 4 shows partially schematically and partially in
`memory at the normal rate then acts to suitably vary the
`block diagram from details of the clock generator of
`picture size. U.S. Pat. No. 4,220,965, on the other hand,
`FIG. 1.
`
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`4,399,462
`4.
`3.
`FIG. 5 is a block diagram of the analog memory of
`retrieval of these analog samples forms an important
`part of the invention and will be dealt with in greater
`FIG. showing how the timing clock signals from the
`clock generator are connected to the memory.
`detail below.
`At this point, it is appropriate to discuss the circuitry
`DETAILED DESCRIPTION OF THE
`responsive to the cockpit camera signals. It will be
`DRAWINGS
`apparent that this circuitry is very similar to that re
`FIG. 1 shows the invention in block diagram form.
`sponsive to the radar video signals. More specifically,
`Although it will be apparent that any two indepen
`AGC 21 is connected to input B which receives the
`dently derived images compatible with accepted televi
`cockpit camera composite video signal. The output of
`sion standards, such as RS 170, can be juxtaposed on a
`the AGC is connected to analog memory 23 which is
`10
`television screen in accordance with the principles of
`also, in the preferred embodiment, the dual shift register
`the invention, the drawings and related disclosure
`Fairchild CCD321 charge coupled device. Shift regis
`which follows will refer to a radar unit and a cockpit
`ters 25 and 27 of memory 23 each have a 455 bit capac
`camera as the sources of the video signals since the
`ity as is the case with registers 9 and 11. The output of
`preferred embodiment is contemplated for use in com
`15
`shift registers 25 and 27 is connected to switch 29 which
`bat aircraft. The circuit receives at A the radar compos
`is also of the single pole double throw variety. Pole 30
`ite video signal. This signal can be obtained directly
`alternates between contacts 31 and 32 of switch 29
`from a radar unit which is adapted to provide video
`under the control of output 14 from clock generator 13.
`signals compatible with an RS 170 video source or from
`In this manner, the contents of only one shift register
`a television camera aimed at the radar scope. This signal
`20
`are outputted while the other is simultaneously storing
`includes horizontal and vertical sync information which
`samples.
`is why the term "composite' is appropriately used.
`Master control 5, which is discussed in greater detail
`Such signals can have a 1 to 10 volt peak to peak volt
`with relation to FIG. 3, functions primarily to generate
`age and are therefore processed by an automatic gain
`timing signals and is synchronized to the incoming
`control (AGC) circuit 1 which provides a regulated 1.6
`25
`video signals by the horizontal and vertical sync signals
`volt peak to peak voltage. The AGC output signal in
`it obtains from composite sync separater 3. The timing
`cludes both horizontal sync and vertical sync informa
`signals are combined by logic circuitry in the clock
`tion which are separated by composite sync separater 3
`operator to form the clock signals. In addition, master
`for input to the cockpit camera (not shown) and master
`control 5 provides a horizontal clamp signal to clamp
`control 5. The sync signal supplied to the cockpit cam
`30
`circuits 22, 24, 26 and 28 (for black reference) at the
`era is utilized to synchronize the camera to the radar
`input of each shift register, respectively. Clamp circuits
`signal by any well known technique such as, for exam
`22, 24, 26 and 28 are series connected to capacitors 2, 4,
`ple, gen lock. The utilization by the master control of
`6 and 8, master control 5 also provides a horizontal
`the sync signals will be discussed below.
`clamp signal to clamp circuit 38. Circuit 38 is series
`The AGC output, which of course is an analog signal,
`connected with amplifier 33 and capacitor 35 to the
`is input to analog memory 7 such as a charge coupled
`combined outputs of switches 15 and 29. The outputs of
`device (CCD) shift register. In the preferred embodi
`switches 15 and 29 are combined by line 40 connecting
`ment the analog memory is a Fairchild CCD321 having
`the fixed contact of the moveable pole.
`shift registers 9 and 11. At the input of each register, in
`Switch 37 is a single pole, triple throw switch which
`accordance with standard practice, is a capacitor to
`is connected to the outputs of the AGC 1, AGC 21 and
`block stray d.c. levels. Two shift registers connected to
`op amp 32. Switch 37, is in the preferred embodiment,
`the radar signal are required because one is storing
`an electronic switch but, here again, it is shown as a
`samples while the other is simultaneously outputting its
`contact switch for purposes of simplifying this descrip
`samples as discussed in greater detail below.
`tion. The pole position of switch 37 is controlled by
`The CCD memory samples the analog video signal at
`45
`external mode-select circuit 39 to select a picture show
`a selected frequency and stores the analog sample. The
`ing solely the radar output, solely the cockpit camera
`analog sample is then shifted from input to output at the
`output, or the combined (multiplexed) radar and cock
`clock frequency in the manner common to digital shift
`pit camera picture. The signals generated by this circuit
`registers. However, the analog value of the samples is
`to set each mode is, respectively, RADAR, COCKPIT
`retained as it is being thus shifted.
`CAMERA, and SPLIT. The output of switch 37 is
`Master control 5 outputs a number of timing signals,
`coupled via buffer amplifier 41 to the output terminal of
`together represented as bundle 21, to clock generator
`the depicted circuit which, in turn, is used as an input to
`13. The 52.3 microseconds of active video plus one
`a television monitor or to a video tape recorder for
`microsecond of pre-video (for black reference) in the
`recording and later display on a video monitor.
`RS 170 format are divided into 455 time units and each
`Turning now to the technique used for compressing
`register has a corresponding 455 bit capacity. The 455
`the radar and cockpit camera pictures with the inven
`bits are clocked into and out of the register under the
`tion so that both images can simultaneously be juxta
`control of output 12 of clock generator 13. Output 14 of
`posed on a single screen, the key element is the timing
`clock generator 13 controls switch 15. Switch 15, repre
`used for inputting and outputting samples into the ana
`sented as a single pole, double throw switch, is con
`60
`log memories. More specifically, output 12 of clock
`nected to the output of shift registers 9 and 11. This
`generator 13 clocks the 455 samples into the analog shift
`switch is, in the preferred embodiment, an electronic
`registers at 8.25 MHz and outputs the 455 samples at a
`switch but for the purpose of simplifying the explana
`frequency 16.5 MHz. Since the same information is
`tion at this stage of the disclosure, a contact switch is
`retrieved from memory at twice the frequency at which
`shown instead. Pole 17 of switch 15 will alternate be
`65
`it is stored, a 2 to 1 picture compression is thus obtained.
`tween contacts 18 and 19 of switch 15 at a rate set by the
`A similar timing control is applied to memory 23 by
`master control 5 to output the contents of each register
`output 12" of clock generator 13.
`at the appropriate time. The specifics of storage and
`
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`The timing diagram of FIG. 2 may be helpful in un
`from which the various clocks utilized in the circuitry
`derstanding how the video signals from the radar unit
`and described below are derived. Frequency divider 52
`divides the oscillator frequency into 11 submultiple
`and cockpit camera are stored, retrieved and combined
`frequencies. The latter are fed into timing logic circuit
`by the invention. Four horizontal reference lines la
`belled 9, 11, 25 and 27 are shown which correspond by
`54 which comprises standard gating circuits to generate
`number to the four shift registers. A line drawn above
`a start of line (SOL) signal, a center of line (COL) and
`an end of line (EOL) signal. These signals perform the
`the reference line is indicative of sample storage, a line
`drawn below the reference line is indicative of sample
`exact functions implied by their names. Thus, in re
`sponse to the timing units provided from the frequency
`retrieval, and a line along the reference line indicates
`divider, the SOL signal is provided after a suitable delay
`that the shift register is inactive. The interval between
`successive vertical lines represents the time required for
`allowing for horizontal clamp (black reference), and the
`EOL signal is provided 455 timing units later, with the
`the raster scan to travel to the center of the screen, or
`COL signal being provided half way between. Master
`53.3/2 microseconds. Thus, two successive intervals
`control 5 also generates EVEN and ODD signals from
`represents one horizontal line. The two such lines on
`toggle circuit 56. These indicate whether an even line or
`FIG. 2 have been marked to show whether an even or
`an odd line is being scanned. One of the inputs to toggle
`odd numbered line is being scanned on the screen. It
`will be readily apparent that for the time period 0 to
`circuit 56 is from vertical blanking time generator 58. It
`deactivates the toggle circuit during the vertical flyback
`53.3 microseconds in which an odd line is being
`scanned, shift registers 9 and 25 are storing samples
`and then reactivates it for the entire field. Clamp timing
`whereas shift registers 11 and 27 are outputting samples.
`circuit 60 generates INCLAMP and OUTCLAMP
`signals in response to the outputs of timing logic circuit
`Samples are clocked into shift registers 9 and 25 for this
`entire period at a frequency of 8.25 MHz from outputs
`54 and a 4.125 MHz frequency signal from frequency
`12 and 12 of clock generator 13. However shift regis
`divider 52. The function of these output signals is stan
`dard and has been mentioned above. Components 52,
`ters 11 and 27 will clock out samples for only selected
`portions of this period. More specifically, register 11
`54, 56, 58, and 60 of master control 5 are all referenced
`to the sync signal obtained from composite sync separa
`remains inactive for the first half of this period whereas
`it clocks out all its stored 455 samples during the second
`tor 3.
`Although only the logic high version of the various
`half of this period at a frequency of 16.5 MHz. Register
`signals generated by master control 5 are shown in FIG.
`27, on the other hand, clocks out all its 455 samples
`during the first half of the period whereas it remains
`3, it should be understood that the inversions of these
`signals are also available. The inverted signals are uti
`inactive for the second half. For the even line scan, the
`lized in FIG. 4 and are represented there by the conven
`reverse arrangement applies with registers 11 and 27
`storing samples and registers 9 and 25 clocking them
`tional line over the symbol of the signal such as "SOL”.
`FIG. 4 discloses in more detail the components of
`Out.
`The combined signal displayed on the television
`clock generator 13, NAND gates 62, 64, 66, and 68
`generate signals which control the switch (see FIG. 5)
`screen will be the cockpit camera output for the first
`connected to each of the outputs of shift registers 9, 11,
`half of the raster line whereas the second half of the line
`25, and 27. NAND gate 62 is responsive to signals COL
`will display the output from the radar unit. Thus, the
`and ODD to generate output R1A. NAND gate 64 is
`images from the radar and the camera will be juxta
`responsive to signals ODD and COL to generate signal
`posed simultaneously on the television monitor after the
`40
`disclosed picture compression has taken place without
`R1B. NAND gate 66 is responsive to signals COL and
`EVEN to generate signal R2B. NAND gate 68 is re
`loss of any video information. Although horizontal
`sponsive to signals EVEN and COL to generate signal
`distortion will clearly take place due to the compres
`R2A. Thus, when toggle circuit 56 indicates that an odd
`sion, the retention of all video information is considered
`line is being scanned, NAND gates 62 and 64 have a
`more significant for the intended purpose and conse
`45
`logic high at their respective ODD inputs. In the first
`quently the distortion is tolerated. Moreover, such dis
`part of the scan line, i.e. when COL is high, output
`tortion is not of such a magnitude as to render the pic
`signal R1B will be generated (i.e. switch to its logic
`ture unintelligible. In fact, in the environment contem
`plated for this invention, namely combat aircraft, the
`low) whereas in the second half of the scan line signal
`COL will be high and output R1A will be generated.
`distortion does not pose any problem in interpreting the
`displayed images.
`Similarly, when toggle circuit 56 indicates that an even
`line is being scanned, signal R2B will be generated for
`Now that the invention has generally been explained
`the first half of the line while signal R2A will be gener
`with the aid of FIG. 1 and the timing diagram of FIG.
`2, the following discussion will proceed to a more de
`ated for the second half of the line. The specific utiliza
`tion of these signals in the memory will be explained
`tailed breakdown of the major components of the cir
`55
`cuitry. However, it must be noted that even the more
`with reference to FIG. 5.
`NAND gates 70, 72, and 74 in cooperation with mul
`detailed circuitry to be discussed below does not in
`tiplexer logic circuit 76 generate the clock signals for
`clude various standard components such as those re
`controlling the storage of samples into and retrieval
`quired for voltage supply, stabilization of logic circuits,
`from memories 7 and 23. More specifically, NAND
`and driver stages. Reference to these components has
`60
`gate 70 is responsive to signals SOL, COL, and a 16.5
`been deleted due to the standard nature of such compo
`MHz frequency to generate OUTCLOCK A. NAND
`nents and, therefore, the relative ease with which one
`gate 72 is responsive to the 16.5 MHz signal as well as to
`skilled in the art can perceive the need for these compo
`COL and EOL to generate OUTCLOCK B. NAND
`nents, and how they are connected in the circuits. More
`importantly, to simplify to the reasonable extent possi
`gate 74 is responsive to SOL, EOL, and an 8.25 MHz
`65
`frequency signal to generate INCLOCK. The OUT
`ble what would otherwise be a very complex schematic.
`FIG. 3 depicts a block diagram breakdown of master
`CLOCK A, OUTCLOCK B, and INCLOCK signals
`are input to multiflexer 76. The latter is a quad, two
`control 5. Oscillator 50 provides a stable 33 MHz signal
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`input logic circuit. This means that it has four two input
`its position. This is a simplified version of what in actu
`circuits each of which generates an output signal. Thus,
`ality is an electronic switch and is utilized here to facili
`the inputs at pins 1 and 2 generate an output at pin 9, the
`tate the explanation of the invention. Signal SC is con
`inputs at pins 3 and 4 generate an output at pin 10, the
`nected to each of the shift registers. It activates appro
`inputs at pins 5 and 6 generate an output at pin 11, and
`priate circuitry in the Fairchild CCD321 device which
`the inputs at pins 7 and 8 generate an output at pin 12.
`is believed to require no further explanation beyond
`The input at pin 13 controls whether the output sees the
`what was mentioned regarding the signal above.
`top or bottom signal at the input. Thus, if this input is
`Signals S2A, S1A, S2B, and S1B, are connected to
`high then the output at pin 9 will be the same as the
`the clock inputs of shift registers 9, 11, 25, and 27. Keep
`input at pin 1, the output at pin 10 will be the same as the
`ing in mind what was mentioned earlier as to the rela
`input at pin 3 and so on for outputs 11 and 12. Similarly,
`tive timing of these signals, it will be readily apparent
`if the input at pin 13 is low, the output at pin 9 will be
`that, for an even line, signal S2A will clock samples into
`the same as the input at pin 2, the output at pin 10 will
`shift register 9 at 8.25 MHz. At the same time, switch 80
`be the same as the input at pin 4 and so on for outputs 11
`is held open by signal R2A to inhibit the output of the
`and 12. The input at pin 13 is the EVEN signal which
`register from being displayed. While shift register 9 is
`15
`means that when toggle circuit 56 generates an EVEN
`storing samples of the radar signal, shift register 25 is
`signal at a logic high the inputs at input pins 1, 3, 5, and
`storing cockpit camera video samples under control of
`7 will be reflected at outputs 9, 10, 11 and 12, respec
`clock S2B which is operating at a frequency of 8.25
`tively. Conversely, when toggle circuit 56 generates an
`MHz. Also, switch 84 will be held open under control
`ODD signal, which means that the EVEN signal is at a
`of signal R2B. While shift registers 9 and 25 are storing
`20
`logic low, the inputs at pins 2, 4, 6, and 8 will be re
`information, shift registers 11 and 27 should be output
`flected at output pins 9, 10, 11, and 12, respectively.
`ting information. Under control of signal S1A, shift
`As far as the outputs of multiplexer 76 are concerned,
`register 11 will be clocking out information for the first
`it will be readily apparent that for an EVEN scan line,
`half of the scan line at a rate of 16.5 MHz. Switch 82 at
`outputs S2A and S2B will be an 8.25 MHz signal for the
`its output will be closed under the influence of signal
`entire scan line. These signals, then, store samples into
`R1A. For the second half of the scan line shift register
`the shift registers to which they are connected, respec
`11 will be inactive since clock S1A is terminated. Shift
`tively. For an ODD scan line signals S1A and S1B will
`register 27 will be outputting its stored samples for the
`receive the 8.25 MHz signal to store information in the
`second half of the scan line due to the presence of clock
`shift register to which they are connected, respectively.
`S1B at its input operating at a frequency of 16.5 MHz.
`The OUTCLOCK A signal provides a 16.5 MHz signal
`Switch 86 at its output will be closed under the influ
`for the first half of the scan line whereas the OUT
`ence of signal R1B. For the first half of the scan line,
`CLOCK B signal provides the same frequency signal
`shift register 27 was inactive since no clock signal S1B
`but only for the second half of the scan line. Thus, for an
`was present.
`,
`even line, output S1A will control retrieval of samples
`For an odd line, registers 9 and 25 will be outputting
`35
`during the first half of the scan line whereas output S1B
`information whereas shift registers 11 and 27 will be
`inputting samples. More specifically, signal S2A will
`will control retrieval for the second half of the scan line.
`clock samples out of shift register 9 at a frequency of
`Similarly, for an odd scan line, output S2A will control
`retrieval for the first half of the scan line whereas output
`16.5 MHz for the first half of the scan line. Shift register
`25 will be inactive since no OUTCLOCK B signal is
`S2B will control retrieval for the second half of the scan
`40
`line. Further details with regard to the use of these
`present. For the second half of the scan line, the OUT
`signals will be provided below with reference to FIG. 5.
`CLOCK A signal is terminated and OUTCLOCK B
`The final clock produced by clock generator 5 as
`signal S2B will clock samples out of shift register 25 at
`shown in FIG. 4 is called SC. This signal controls the
`16.5 MHz. As to shift register 11, signal S1A clocks
`sampling of the analog signal obtained from AGC cir
`samples into storage at a frequency of 8.25 MHz. Signal
`45
`cuit 1 at the input of all the shift registers. It is respon
`S1B clocks samples into shift register 27 also at 8.25
`sive to the 8.25 MHz INCLOCK signal from NAND
`MHz. Switches 84 and 80 will be closed, respectively,
`74, a 16.5 MHz signal and the EQUAL signal from
`for the first and second halves of the scan line. Switches
`vertical blanking time generator 58. It is readily seen
`82 and 86 will remain open for the entire duration of the
`that the SC signal is a 8.25 MHz square but with each
`scan line.
`50
`halfwave having only half its normal width due to the
`It should be clear from all of the above that the inven
`presence of the 16.5 MHz signal at the input. This nar
`tion provides a compact, relatively low cost and light,
`row pulse provides the 455 analog samples for storage
`yet effective, apparatus for producing a compressed
`by the shift registers. The connection of the signal to the
`picture. This is achieved primarily by resort to analog
`memory for storing the analog video signals in place of
`memories is also described further below.
`55
`the complex circuitry used in the art previously which
`FIG. 5 shows how the various clock signals are em
`ployed to control the storage and retrieval of samples
`relied on A/D circuitry and digital memory Moreover,
`two compressed pictures derived from two independent
`from memories 7 and 23. More specifically, the radar
`video signal is input at terminal A for storage by shift
`video sources are elegantly combined by a timing cir
`cuit which generates eight clock signals having a rela
`registers 9 and 11. The cockpit camera video signal is
`60
`tively complex timing relationship with digital circuitry
`input at terminal B for storage by shift registers 25 and
`employing minimal components to reduce size, weight
`27. At the output of shift registers 9, 11, 25, and 27 are
`and cost. These factors are important generally but all
`connected switches 80, 82, 84 and 86, respectively.
`Switches 80 and 82 correspond to switch 15 in FIG. 1
`the more so in the aircraft environment, discussed
`above, contemplated for the preferred embodiment of
`while switches 84 and 86 correspond to switch 29 in
`FIG. 1. Switches 80, 82, 84, and 86, are shown as
`the invention.
`contact type single pole, single throw switches to the
`Although the above discussion describes the pre
`pole of which is connected an amplifier which controls
`ferred embodiment of the invention, it will be readily
`
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`65
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`IPR2018-01045
`Sony EX1022 Page 8
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`4,399,462
`10
`5. The apparatus of claim 4, wherein said first timing
`apparent that various modifications of the described
`means further includes a clock generator means coupled
`circuits are possible. For example, one of the sources of
`to the master control means for combining given fre
`video signals can incorporate some of the components
`quency signal, the higher frequency signal, and the
`of the disclosed circuit. More specifically, should the
`SOL, COL, EOL, EVEN and ODD signals to generate
`cockpit camera be a CCD type camera, the camera
`said four clock outpout signals coupled, respectively, to
`itself can act as memory 23. Thus a separate memory
`the four shift registers,
`would not be required. Picture compression of the
`6. The apparatus of claim 5, wherein the given fre
`image detected by the CCD camera would thus be
`quency is 8.25 MHz and the higher frequency is 16.5
`achievable by clocking out the information stored in the
`CCD camera at twice the normal rate. Furthermore,
`MHz.
`7. The apparatus of claim 6, further comprising four
`the digital gating circuitry used to derive the various
`switch means coupled, respectively, to the output of
`clock signals should be looked upon as exemplary since
`each shift register and wherein the clock generator
`many other ways of deriving such signals will readily
`means generates four switching signals in response to
`occur to one familiar with this art. These an