A PARTICIPANT’S
`PERSPECTIVE
`
`R. Gary Daniels
`
`Motorola
`
`The ‘Jhather” of the
`
`6805 MCU relates his
`
`role in the histo y of
`the microprocessor.
`
`M y agreement
`
`this article on
`to write
`(in a moment
`the microprocessor
`of weakness) came out of respect
`for Federico Faggin and his contributions
`to
`our society and profession.
`Here is the story, as told by an active par-
`ticipant.
`Briefly,
`in
`the space allowed.
`Accurately,
`as best my memory
`permits.
`Interestingly, as my writing
`talent allows. But
`admittedly,
`from my viewpoint.
`
`the beginning
`Before
`(1946-1970)
`The willing marriage of two revolutionary
`industries set the stage for the microproces-
`sor.
`In
`industry.
`first was the computer
`The
`J.
`1946 at the University
`of Pennsylvania,
`Presper Eckert and John Mauchly demon-
`strated the world’s first electronic computer.
`It was the size of a boxcar, weighed 30 tons,
`and used 150,000 watts of power.
`Its 18,000
`vacuum
`tubes could compute gunnery coor-
`dinates
`100
`times
`faster
`than a human.
`ENIAC started the computer
`revolution.
`The second
`industry began
`in 1948 with
`the invention of the transistor at Bell Labs by
`William Shockley, John Bardeen, and Walter
`Brattain. The
`first
`transistor was also, by
`today’s standards, big (about the size of a BB
`pellet) and crude (two sharpened points that
`probed
`a piece of germanium).
`But
`this
`point-contact
`structure promised
`future elec-
`tronic devices
`that would
`be smaller and
`lighter and have much longer life. It launched
`the semiconductor
`revolution.
`These revolutions
`started slowly, gained
`momentum
`in
`the 195Os, and began
`to
`exhibit
`real utility
`in the 196Os-mostly
`for
`military and space applications.
`in the late
`The integrated circuit invention
`1950s (jointly credited
`to Jack Kilby of Texas
`Instruments
`and Robert Noyce of Fairchild
`
`for the
`
`Semiconductor) was a key milestone
`fledgling semiconductor
`industry.
`had
`By 1970, both of
`these
`industries
`matured and prospered. Both were accept-
`ed as viable
`technologies
`(and businesses),
`and both were relatively well understood-
`certainly
`by
`the engineering
`community.
`Computer architectures were no longer mys-
`teries, and most engineering
`schools’ cur-
`ricula
`offered
`the concepts
`of software
`programming.
`The IBM System&bO, one of the first IC-
`based computers, was
`the most popular
`mainframe
`in 1970. It featured software com-
`patibility over several models. Minicomput-
`ers had appeared
`that offered
`lower cost and
`smaller size while maintaining
`substantial
`performance.
`had
`technology
`Similarly, semiconductor
`cir-
`to integrated
`progressed
`from discrete
`in
`in computers
`cuits (used predominantly
`1970) to the leading edge of the VLSI era.
`MOS technology
`in 1970 offered
`the capa-
`bility of integrating
`several hundred
`transis-
`tors-perhaps
`a few thousand-on
`a single
`piece of silicon. For the first time, we could
`monolithically
`integrate
`a complete
`elec-
`tronic system!
`The most popular choices for system inte-
`gration
`in 1970 were
`the calculator and the
`electronic
`timepiece.
`My project
`in 1970? The design of an elec-
`tronic wristwatch chip (in lo-micron
`silicon-
`gate CMOS at 1.5 volts). My career with
`Motorola Semiconductor had started in 1966
`as an engineer
`in
`the Applied
`Science
`Department
`in Phoenix, Arizona.
`The 1970s were a time of high engineer-
`ing achievement
`and excitement. We had
`put a man on the moon
`in 1969! It was also
`a period of high economic growth-in
`the
`country, and especially,
`in the computer and
`semiconductor
`industries.
`
`0272-1732/96/$5.000
`
`1996lEEE
`
`December 1996 21
`
`PAGE 1 of 11
`
`HMC EXHIBIT 1025
`
`

`

`(@th MST componer&),tha~
`1 tie constmcted breadboar@
`‘1 qe‘alsd ;ised to develop and deb&d@gnostic
`s,o@~~.
`,:~we,,used.log& atid~:circ&c&bu~er
`~@<la$o$“‘>$grar$
`~,&ensiy&l~, and these w&ii: season+ly
`*@ W/
`$Ccuxiat&if
`1 could obtiiri
`ptocess p”&ameters., we
`laid out PCs by
`‘hand &ncJ used computer
`digitiaing~ to .get a cobptiter
`database for mask preparation
`and for checking
`iman-
`ually). ‘Comljuter pkograms could +&y
`rC layourr~&+--
`‘but ‘they were
`sldw
`an@ iudirne,fit&y
`by
`today’s‘
`,‘standards. High-l&#
`simulation was still in the future;
`‘as was lo~i~-to-layou~~~~rifi~~~~~.
`,*
`1
`*/
`,\,I
`,>,*
`
`.‘” ,,‘T
`
`;I
`
`\,
`
`j
`
`indus-
`the marriage of the computer
`In this exciting period,
`try and the semiconductor
`industry happened-thereafter
`forever altering
`the paths of these two
`industries.
`calculator
`The
`idea of a general-purpose
`programmable
`was Ted Hoff’s at one-year-old
`Intel. The implementation
`by
`a young engineer, Federico Faggin, is certainly
`the most piv-
`otal story of this time.
`in this series tells the whole story.
`The preceding
`article
`Suffice
`it to say here that Intel
`introduced
`the world’s
`first
`microprocessor,
`the 4004, in 1971. The 4-bit machine
`con-
`tained 2,300 transistors
`in P-channel silicon-gate
`(S-micron)
`technology.
`It was fabricated on two-inch wafers and assem-
`bled
`in a 16-pin package. The 4004 operated with a -15-v
`power supply at 750-kHz clock speed and could address up
`to 8 Kbytes of ROM and 640 bytes of P&M. Its performance
`was roughly comparable
`to the ENIAC.
`Intel
`followed
`the 4004 with
`the &bit 8008 in 1972. The
`8008 (a Faggin-Feeney
`design) contained
`3,500 transistors
`and could address 16 Kbytes of memory. However,
`it was
`still an invention
`in search of a market, as the technical world
`was just beginning
`to view
`the microprocessor
`seriously,
`Fortunately,
`interest was sparked at several semiconduc-
`tor firms.
`in 1972
`project
`initiated a custom microprocessor
`Motorola
`that never made
`it to silicon. The design
`team
`led by Tom
`Bennett went on to design our first microprocessor,
`the 6800.
`Texas Instruments
`laid the groundwork
`for future micro-
`controllers
`in 1973 with
`the metal-gate PMOS TMS-1000. This
`monolithic
`IC contained a LKbyte ROM, 32-byte RAM, i-bit
`CPU, 300-kHz
`clock oscillator,
`and on-chip
`input/output
`pins. TI designed
`the TMS-1000
`to span a range of handheld
`calculator products.
`race included
`in the microprocessor
`Other early entrants
`Rockwell’s PPS4 in 1972 and PPS-8 in 1974; National’s &bit,
`PMOS IMP 8 (perhaps
`the first to address 64 Kbytes of mem-
`ory) in 1973; and RCA’s COSMAC (the first 8-bit, CMOS entry)
`in 1974.
`
`22
`
`IEEE Micro
`
`Texas InstrumentsTMS-1000
`
`(1973)
`
`The semiconductor
`
`in late 1974. Bob Galvin
`turn
`took an abrupt
`My career
`decided
`to close down our Timepiece
`Electronics Unit
`(a
`wise business decision
`in retrospect, but it left me looking
`for a job). An opportunity
`occurred
`in
`the new Micro-
`processor Design Department working
`for Tom Bennett
`in
`Gary Tooker’s MOS Operation. However,
`this assignment
`meant a move
`to Austin, Texas.
`The 6800 had just been
`introduced.
`industry was entering a recession.
`team to redesign
`My first assignment was to lead a small
`the 6800 MPU to make
`it more manufacturable
`and so that
`higher
`speed versions
`could be selected. This product,
`known
`internally as the 68OOA, contained about 5,000 tran-
`sistors in 6-micron silicon-gate NMOS
`technology.
`supply
`The 6800 operated
`from a single 5-V power
`(unique at the time) at up to ~-MHZ clock and bus speeds
`and addressed 64 Kbytes of memory.
`It was fabricated
`on
`three-inch wafers and assembled
`in a 40-pin ceramic dual-
`in-line package
`(DIP).
`the 6800
`included
`A typical 6800 system configuration
`MPU, a 6810 128-byte RAM, a 6830 1-Kbyte ROM, a 6820
`peripheral
`interface adapter (PIA), and possibly a 6850 asyn-
`chronous communications
`interface adapter
`(ACIA).
`The company billed
`the 6800 as a “modern architecture”:
`two 8-bit accumulators,
`two 16-bit registers (index and stack
`pointer), a 16-bit program counter, and a condition
`code reg-
`ister. It had a 16-bit address bus and an 8-bit bidirectional
`data bus (therefore,
`to us, it was an 8-bit machine). Memory-
`mapped
`I/O allowed a sophisticated
`interrupt
`structure.
`As were other microprocessors
`of its day, the 6800 was
`seen as a replacement
`for random
`logic on several printed
`circuit boards. Use in an automobile
`or for desktop
`com-
`
`PAGE 2 of 11
`
`HMC EXHIBIT 1025
`
`

`

`puting was beyond our wildest dreams. The first volume cus-
`tomer
`for the 6800 made video games.
`for early micro-
`Programmers
`used assembly
`language
`to the 1s and OS
`processors
`An assembler
`converted
`this
`(object code)
`that the MPU could understand.
`Motorola’s major competitor was clearly
`Intel. The 8080,
`introduced
`a few months before
`the 6800, had similar
`fea-
`tures and performance.
`In
`the
`first of many “religious
`debates,” we would argue the 6800 architecture was “clean-
`er and simpler.” The 8080 became
`the brain of what many
`consider
`the first personal computer,
`the Altair.
`from Faggin
`The 280, an upgraded but compatible product
`(then at Zilog)
`introduced
`in 1975, made it essentially a three-
`horse race. However, by the end of 1975 there were many
`microprocessors
`on the market
`(see Table 1, next page).
`In 1976, we had a very
`important
`customer
`visit: Delco
`Electronics. Delco had accepted
`the task of designing
`an
`
`regu-
`to meet the new government
`engine control module
`lations
`for emissions
`for all General Motors vehicles.
`It need-
`ed a semiconductor
`supplier and partner, and we won
`the
`program against stiff competition. Here was the high-volume
`application
`and industry-leading
`partner we had been look-
`ing for!
`(General Motors
`as GMCM
`The system became known
`it built much of Motorola
`Custom Microprocessor),
`and
`Austin. Delco engineers J.D. Richardson, Phil Motz, and oth-
`ers, working with
`the Motorola
`design
`team
`led by Stan
`Groves and Gene Schriber, defined a system based on an
`enhanced 6800 plus a half-dozen
`companion
`chips.
`The upward-compatible
`enhancements
`to the 6800 includ-
`ed new 16-bit instructions,
`additional
`index register
`instruc-
`tions, an 8x8 multiply,
`and faster execution
`cycles on key
`store and branch
`instructions. And, of course, we had to meet
`the hostile automotive
`temperature
`and voltage
`require-
`
`December 9996 23
`
`PAGE 3 of 11
`
`HMC EXHIBIT 1025
`
`

`

`later
`
`expectations
`
`the quality
`learn
`to
`ments. We were
`(painfully
`but very beneficially).
`industry was still recovering
`In 1977, the semiconductor
`from
`the recession, and although we were hiring again, the
`GMCM program was understaffed. As my experience on the
`6800 redesign was fresh, Motorola decided
`that I should
`lead
`the CPU design; Gene Schriber
`took charge of the compan-
`ion chips.
`for microprocessors.
`By then, my title was design manager
`Since management duties required much of my at-work
`time,
`a large part of the GMCM CPU design work
`took place at
`home (on my pool
`table).
`the same as the
`The GMCM
`technology was pretty much
`6800, except
`that we moved up to 4-inch wafers and into
`high-pin-count
`plastic DIPS to satisfy
`the automotive
`envi-
`ronment
`(and cost) requirements. Delco’s quality demands
`led us to test grade (fault validate) all the test programs.
`GMCM was a very successful program-for
`both Motorola
`and Delco Electronics.
`It cemented a partnership
`that remains
`a model
`for our industry. Production
`volumes
`for this pro-
`gram dwarfed most other microprocessor
`applications
`at the
`time. And,
`it was just the beginning. The number of micro-
`processors/microcontrollers
`in an automobile would steadi-
`ly increase
`for another 15 years!
`Meanwhile,
`Intel announced
`the 8-bit 8048 microcontroller
`
`lntelX080(1974)
`
`I
`
`1 Chip
`
`Table 1. Major microprocessor
`(Sources: Dataquest;
`
`and microcontroller
`ICE, Phoenix, Ariz.;
`
`rank ordered by sales.
`merchant suppliers,
`In-Stat, Scottsdale, Ariz.; Motorola)
`
`Microprocessors
`
`Intel
`Motorola
`AMD
`Signetics
`National
`NEC
`Gould
`Texas Instruments
`
`Motorola
`Zilog
`Intel
`Synertek
`NEC
`National
`Rockwell
`RCA
`Mostek
`AMD
`Commodore
`Fairchild
`Signetics
`Gould
`
`Intel
`Motorola
`AMD
`AT&T Technologies
`DEC
`Fairchild
`Hitachi
`lnmos
`National
`NCR
`NEC
`Zilog
`Data General
`
`Intel
`Motorola
`AMD
`NEC
`lnmos
`Siemens
`Hitachi
`Zilog
`LSI Logic
`National
`Performance
`Toshiba
`Cypress/Ross
`
`Intel
`AMD
`Motorola
`IBM
`Texas Instruments
`Cynx
`Hitachi
`NEC
`IDT
`National
`Toshiba
`SGS-Thomson
`Fujitsu
`
`24
`
`IEEE Micro
`
`PAGE 4 of 11
`
`HMC EXHIBIT 1025
`
`

`

`the 8748. The 8048 contained
`unit and an EPROM version,
`a l-Kbyte ROM, a 64-byte RAM, an &bit
`timer, 27 I/O pins,
`and an on-chip
`clock oscillator. The 40-pin MCU operated
`from a 5-V supply. Other S-bit MCU competitive
`products
`included
`the F8 from Fairchild,
`the 3870 from Mostek, and
`the 1650
`from General
`Instruments.
`It was decreed
`that
`Motorola must have a single-chip microcontroller.
`a
`The product became known
`as the 6801. It contained
`128-byte RAM, 2-Kbyte ROM, sophisticated
`16-bit timer (a la
`automotive),
`~-MHZ on-chip clock oscillator, programmable
`digital
`I/O, serial port and, of course, the CPU.
`We originally
`intended
`to use the 6800 for the CPU, but the
`GMCM CPU fit the IC layout better and offered enhanced
`fea-
`tures. We explained
`to Delco engineers
`that since they would
`likely use the 6801, it would be in Delco’s best interest
`to
`grant our request
`to use the GMCM CPU. Delco agreed.
`We introduced
`the 6801, our first microcontroller,
`in 1978.
`The design
`team
`included Pern Shaw, Fuad Musa, Wayne
`Busfield, and Mike Wiles. This was our first system on a chip.
`The 5-micron NMOS 6801 contained 35,000 transistors
`in a
`40-pin DIP. We were all very proud of it--except
`for our mar-
`keting manager, Gary Summers, who complained at an oper-
`ations review
`that it was too expensive.
`That was tantamount
`to calling my baby ugly! At home
`that night my anger turned
`(after a few glasses of wine)
`to a
`challenge.
`I had a logic diagram of the 6800 at home, and I
`began
`to study
`it. What
`if we eliminated
`one accumulator?
`I
`red-marked
`that logic. How about the decimal-adjust
`instruc-
`tion that was seldom used but took a lot of silicon area? More
`red marks. How about an 8-bit index register and stack point-
`er? More red.
`By the wee hours of the morning my logic diagram was
`bloody
`red. The next morning
`I handed
`the marked-up doc-
`ument
`to a young engineer, Jim Thomas,
`to pursue
`further.
`Jim worked with Joel Boney and others removing even more
`features
`for a few days. Then
`they began
`to carefully add a
`few back-including
`powerful
`(I/O) bit manipulation
`and
`conditional
`branches.
`the 6805. The 6805
`We named
`this new &bit architecture
`line,
`introduced
`in 1979, is, we believe at this writing,
`the
`largest selling microprocessor
`architecture
`in the world
`(over
`two billion units shipped of the 6805, 146805, and 68HCO5
`lines).
`from a sister division about
`inquiries
`In 1979, we received
`a microcontroller
`for pagers. This was the brainchild of tech-
`nical wizard Walt Davis-and
`he brought designers
`to help
`do it! The architecture
`selected was the 6805, but
`to meet
`the low-power
`requirements
`of a pager, the technology
`had
`to be CMOS. ’
`and Raghu
`Phil Smith
`included
`team
`This
`design
`Raghunathan. The product was the 146805. We were sud-
`denly
`in the CMOS MCU business! We also had started our
`first long-lasting
`partnership with a sister division.
`In 1977, our operations manager, Colin Crook, envisioned
`the need for a step-function
`increase
`in microprocessor
`per-
`formance. He established a “skunk-works”
`activity with Tom
`Gunter as the leader.
`that memory
`the assumption
`Tom and his team made
`would be readily available and cheap (little did they know!)
`
`Motorola68000(1979)
`
`lan-
`in high-level
`and that future software would be written
`guages. To increase bandwidth,
`they called
`for a 16-bit data
`bus and a 32-bit address bus (package
`limitations
`reduced
`this to 24 bits on the first product). They made the registers
`general purpose and 32 bits wide-and
`there were plenty
`of them (16). The implementation
`used microcode
`(for the
`first time-at
`Motorola anyway).
`The product was the 68000.
`on 5-inch
`Introduced
`in 1979, the 68000 was fabricated
`wafers
`in 4-micron HMOS
`technology. Coincidentally,
`the
`transistor count was about 68,000. The 68000 used a special
`package: a 64.pin DIP (ceramic
`first, plastic
`later).
`It
`The 68000 operated at 5 V and at ~-MHZ clock speed.
`performed at about 1 MIPS (million
`instructions per second).
`Apple Computer selected
`the 68000 for its Macintosh per-
`sonal computer
`line, and we
`formed another
`long-lasting
`partnership.
`The 68000 in 1979 was in a class by itself, and we were
`proud of it. If any competitor was of serious concern,
`it was
`Zilog with
`its 28000, also introduced
`in 1979. The 28000 was
`assembled
`in a 48-pin DIP and contained
`close
`to 18,000
`transistors. Other early
`I6-bit microprocessors
`were
`the
`National PACE and the General
`Instruments ~~1600.
`But in our industry,
`the competition,
`it seems, never sleeps.
`Intel had introduced
`a I6-bit microprocessor,
`the 8086, in
`1978 and an 8-bit pin-out version
`in a 40-pin package,
`the
`8088, in 1979. With 29,000 transistors, an address range of
`only 1 Mbyte, and an ~-MHZ clock speed (in 3-micron HMOS
`technology), we felt it was no match
`for our 68000.
`design
`Nonetheless,
`the 8088 won
`the most
`important
`socket of the decade-for
`the IBM personal computer.
`Intel’s 8061 won
`the Ford engine control
`socket, while
`
`December 1996 25
`
`PAGE 5 of 11
`
`HMC EXHIBIT 1025
`
`

`

`fea-
`the 68HCl1,
`the 6801 in HCMOS. The resulting product,
`tured a higher performance,
`upward-compatible,
`8-bit CPU;
`more capable 16-bit
`timer; on-chip
`analog-to-digital
`con-
`verter; 8-Kbyte ROM; 256-byte RAM; and 512-byte on-chip
`EEPROM (an industry
`first). This, plus all the basic 6801 fea-
`tures,
`truly made
`it a system on silicon. The 68HCll
`con-
`tained
`130,000
`transistors
`in a 52-pin PLCC package.
`It
`operated with an on-chip ~-MHZ oscillator clock.
`Introduced
`in 1984, the 68HCll
`line was an instant suc-
`cess. We had shipped half a billion units by its eleventh birth-
`day. Fabricated
`in 2-micron HCMOS,
`the EEPROM proved
`to be a manufacturing
`challenge. We finally
`resorted
`to 100%
`burn-in
`to screen for EEPROM
`infant mortality defects.
`And the competition
`never slept.
`the 16-bit 80286:
`Intel responded
`to our 68000 in 1982 with
`8- to 12-MHz
`130,000
`transistors,
`1.5-micron
`technology,
`clock speeds, 68-pin PGA package. The Intel 386 followed
`16-
`in 1985 with 275,000 transistors,
`l.O-micron
`technology,
`to 33-MHz clock speeds, and a 132-pin PGA package.
`Intel competed with Motorola
`in the microcontroller
`field as
`well, with
`the 8051 (which
`fell somewhere between our 6805
`and 6801 in performance).
`National Semiconductor
`caught
`our attention with
`the introduction
`of its COPS MCU line.
`In the mid-1980s other competitors
`began
`to emerge-
`NEC, Hitachi, Toshiba, Mitsubishi, Matsushita,
`and Fujitsu
`(see Table 1).
`to have high-vol-
`all seemed
`These Japanese competitors
`ume
`internal
`customers
`in consumer
`electronics
`(TV sets,
`VCRs, camcorders). All were members of a powerful
`con-
`sortium. All paid careful attention
`to detail with highly dis-
`ciplined manufacturing.
`And, all held a license
`to either an
`Intel or a Motorola architecture,
`or were able to leverage a
`i-bit MCU used by their
`internal customers.
`Here was competition
`like we had never seen before!
`Then,
`in 1985, another
`recession hit
`the semiconductor
`industry. About
`then, you could get an even-money
`bet on
`the chances of
`the American
`semiconductor
`industry’s
`survival.
`Cries for help went to the US government. Sematech, MCC,
`and the American-Japan
`trade agreement all came about as
`a result. Too much or too little
`remains
`to be seen, but the
`American
`semiconductor
`industry has survived!
`Shortly after the introduction
`of the 68HC05, 68HCl1, and
`68020, my career path
`led me from design
`into operations.
`My boss, Murray Goldman,
`then general manager of the
`Microprocessor
`Division,
`split
`the business
`into
`two opera-
`tions:
`the High-End Microprocessor
`Operation
`under Tom
`Gunter, and the Microcontroller
`Operation under me. In the
`first month, September 1984, my new MCU operation
`report-
`ed negative bookings! Welcome
`to operations.
`
`for the micro-
`the architectural directions
`By the mid-1980s
`Intel with
`the
`processor
`leaders had been cast in concrete:
`x86, and Motorola with
`the 68000, both with
`full 32-bit
`(address and data) implementations.
`Software compatibility
`was an absolute
`requirement.
`The competition was for ever
`higher performance.
`
`Intel Pentium
`
`(1993)
`
`the RCA 1802. (Motorola was to become a
`Chrysler selected
`second-source
`supplier
`for the former and displace
`the lat-
`ter with
`the 6801.)
`included TI’s TMS-9000
`introductions
`Other competitive
`and National’s Scamp. (Table 1 lists the many microproces-
`sor suppliers
`in 1980.)
`No telling of this story would be complete without at least
`mentioning
`the competitive alliances of this period.
`It seemed
`that we had some sort of alliance with nearly everyone: Hitachi,
`TI, Philips, Mostek, Thomson, Signetics, and RCA/GE/Harris.
`Intel lined up with AMD and NEC, among others.
`
`several derivatives of,
`In the next few years we developed
`and coprocessors
`for, the 68000 microprocessor-notably
`the 68008, 68010, 68020, and the 68881 math coprocessor.
`The 68020, introduced
`in 1984, was the first 68000 deriv-
`ative, and the first high-performance
`microprocessor
`any-
`where,
`implemented
`in
`high-performance
`CMOS.
`It
`contained 200,000 transistors
`in 2-micron HCMOS
`in a 114-
`pin ceramic pin-grid-array
`package. This was the first true
`32-bit microprocessor
`(32-bit data and address buses, 32-bit
`internal
`registers, ALU, and barrel shifter). The 68020 includ-
`ed a 256-byte, on-chip
`instruction cache memory and a three-
`stage instruction
`pipeline.
`It supported both virtual memory
`and virtual machine.
`It operated at a 16-MHz clock
`frequen-
`cy, so we pegged
`the 68020 performance
`at about 5 MIPS.
`Apple Computer used the 68020 in its line of Macintosh
`color computers.
`Our microcontroller
`activity
`for us as well.
`A team led by Jim Sibigtroth enhanced and implemented
`
`to a major business
`
`line had grown
`
`26
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`HMC EXHIBIT 1025
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`

`

`the
`increasing
`that the basic architecture was fixed,
`Given
`clock
`frequency
`(via ever decreasing geometries on silicon)
`was the most obvious path to improve performance. Cache
`memory
`(instruction and then data), either on chip, close by,
`or both for very rapid access, was another
`fruitful approach.
`We also used complex pipelines and branch prediction algo-
`rithms. Math coprocessors
`(sometimes on chip) significant-
`ly increased computational
`performance.
`requirement,
`Memory management
`became an urgent
`both
`to handle very large secondary storage (disk memory
`devices) and to manage
`large, paged main memories with
`minimum
`performance
`degradation.
`Along
`these lines, Intel, Motorola, and their camp follow-
`ers fought
`the “micron wars.” Motorola announced
`the 68030
`with 270,000 transistors
`in 1987. It operated at up to 20 MHz
`in 1.3-micron
`technology
`in a 128-pin PGA package.
`
`the 486 in 1989. It contained 1.2 million
`Intel announced
`transistors and operated at up to 25 MHz at l-micron
`geome-
`tries (up to 50 MHz at 0.8 micron). The 486 included an on-
`chip math coprocessor, 8-Kbyte cache memory, and virtual
`memory support packaged
`in a 16%pin PGA.
`Intel’s success in the personal computer market attracted
`competitors with x86-compatible
`solutions. The list includ-
`ed AMD, Cyrix, TI, and SGS-Thomson. However,
`Intel main-
`tained dominant market share.
`sim-
`We introduced
`the 68040 in 1989, with performance
`ilar to the 486; 1.2 million
`transistors
`in 0.8-micron
`technol-
`ogy. The 68040
`included
`both data and instruction
`cache
`memories
`(4 Kbytes each), a six-stage
`instruction
`pipeline,
`and a math coprocessor. We set the 68040 performance
`at 20
`MIPS with an initial clock
`frequency of 25 MHz. The prima-
`ry package
`for the 68040 was a 179pin PGA.
`
`December 7996 27
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`HMC EXHIBIT 1025
`
`

`

`in perfor-
`to move up
`needed
`legislation,
`fuel economy
`mance. The resulting
`product,
`sampled
`in 1989, became
`known as GMPX or HC32 or 68332. It featured a 32-bit 68020
`CPU (less the barrel shifter and
`instruction
`cache) and an
`intelligent
`timer we called a TPU (time-processing
`unit). This
`design featured an on-chip
`intermodule bus (IMB) and a very
`modular architecture.
`It comprised 400,000 transistors
`in 0%
`micron HCMOS technology. We produced
`it on 8-inch wafers
`in our new MOS 11 wafer
`fab and assembled
`it in a 132-pin
`PQFP package. The design team included John Kastura (from
`Delco),
`John Vaglica, Vernon Goler,
`and Tony Riccio.
`Operating with a 32-KHz crystal and an on-chip PLL to gen-
`erate a 16-MHz system clock,
`the 68332 as a system (not just
`a CPU) delivered over 5-MIPS performance.
`Table 1 lists the major microprocessor
`and microcontroller
`participants
`as we entered
`the 1990s. Primarily,
`it was Intel
`versus Motorola
`in microprocessors,
`and Motorola
`versus
`NEC, Mitsubishi, Hitachi, Toshiba, Matsushita-and
`Intel-
`in microcontrollers.
`In this time frame, Murray Goldman proposed a Motorola
`alliance with Toshiba
`that involved a jointly owned
`factory.
`The negotiations
`took longer than building
`the factory (named
`TSC for Tohoku Semiconductor
`Corporation),
`but
`it finally
`happened. Here was a strong commitment
`by both parent
`companies
`to cooperate, and it worked. We view TSC as a
`success-in
`manufacturing,
`in technology
`cooperation,
`and
`in international
`understanding.
`It was not without
`its rough
`spots, of course, but overall
`it was a win-win
`alliance.
`
`(1992-96)
`to the 486 in 1993, the
`the successor
`Intel
`introduced
`transistors and reaches
`Pentium.
`It contains over 3 million
`technology.
`Further
`75MHz
`clock speeds
`in 0.8-micron
`process shrinks down
`to 0.35 micron pushed
`the clock speed
`over 100 MHz.
`It comes
`in a 296-pin PGA package.
`dynamic
`Pentium
`features a dual
`five-stage
`pipeline,
`branch
`prediction,
`16-Kbyte
`cache, and built-in
`dual-
`processing support. Despite an embarrassing problem with
`its floating-point
`unit, Pentium quickly became
`the bench-
`mark microprocessor
`of its day.
`in
`The latest Intel product
`is the Pentium Pro. Introduced
`1995 with 5.5 million
`transistors
`in 0.35-micron
`technology,
`it reaches clock speeds up to 200 MHz. The Pentium Pro
`includes a companion
`level-two
`cache memory chip
`in the
`same package.
`the 601,
`its first product,
`introduced
`The PowerPC alliance
`transistors
`in 0.6-micron
`in 1993. The 601 contains 2.8 million
`technology.
`It operates at 3.3 V with clock speeds up
`to
`120 MHz.
`the PowerPC
`In 1995 both IBM and Motorola manufactured
`604e at speeds up to 200 MHz.
`It contains over 5 million
`tran-
`sistors in 0.35-micron
`technology. The 604e is a 32-bit super-
`scalar design capable of issuing
`four
`instructions
`per clock
`cycle. Instructions
`can execute out of order. Dynamic branch
`prediction
`improves
`the accuracy of instruction prefetching.
`The 604e integrates separate 32-Kbyte
`instruction and data
`caches. Memory management units for instructions and data
`reside on chip;
`these support up to 4 petabytes of virtual
`
`Motorola
`
`PowerPC 604e (1995)
`
`The good news for Intel and Motorola was the large base
`of installed software;
`the bad news was that backward
`com-
`patibility
`forced along excess baggage. If one could start with
`a clean sheet of paper, knowing what we knew by then,
`what would we do differently? One answer
`to that question
`was a new architectural
`approach
`called RISC (reduced
`instruction
`set computing).
`The idea was to increase perfor-
`mance by simplifying
`the architecture.
`the Mips RZOOO
`Early entrants
`in the RISC field
`included
`(first to reach the market
`in 19861, Sun Microsystem’s Spare,
`AMD’s 29000, Acorn’s ARM, Digital’s Alpha, and HP’s PA-RISC.
`In 1991, Apple,
`IBM, and Motorola
`announced
`a major
`technology alliance to jointly develop high-performance
`RISC
`processors based on IBM’s RISC/System 6000 architecture,
`called
`the PowerPC. The alliance established a joint design
`center named Somerset
`in Austin, Texas.
`Meanwhile,
`as my team used to say, “While microproces-
`sors got all the headlines, microcontrollers
`shipped all the
`volume. ”
`the 68HC05
`for both
`to increase
`continued
`As shipments
`and 68HCll
`lines, we continued
`to pursue opportunities
`with a focus on our sister wireless communications
`divisions,
`in the automotive
`segment, and in Japan. My MCU opera-
`tion grew
`to a division.
`in the Canon
`for us was the 68HCll
`A major design win
`EOS camera. Canon became our first partnership
`customer
`in Japan.
`for our
`a rapid modular design capability
`We developed
`68HC05 line, which we named CSIC (customer-specified
`inte-
`grated circuits,
`to distinguish
`it from ASIC). Soon,
`this line
`grew
`to over 100 different products.
`Delco Electronics,
`faced with ever tighter emission and
`
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`

`

`memory and 4 gigabytes of physical
`memory. Other on-chip
`resources
`include multiple
`integer execution
`units
`and
`a
`floating-point
`unit.
`Operating at 2.5 V and 200 MHz,
`the
`604e delivers well over 200-MIPS per-
`formance with a power consumption
`of 12 watts.
`It is packaged
`in a 256.
`pin ball grid array.
`the
`Ford Motor Company selected
`PowerPC architecture
`for engine con-
`trol
`into
`the next century. Motorola
`completed
`the design of
`this very
`high performance
`microcontroller
`and delivered
`prototypes. We’ve
`announced
`commercial
`versions of
`this line (MPC500 and MPC800).
`We directed
`the 68000 line toward
`high-performance
`embedded control
`applications
`(printers,
`disk drives).
`Our ColdFire
`line, introduced
`in 1995
`as the bridge
`to RISC processing per-
`formance,
`fills
`the “sweet
`spot”
`between
`the 68000 and PowerPC.
`Table
`1 lists other
`contenders,
`bringing microprocessors
`up to the
`present. As of this writing,
`the worlds most powerful micro-
`processor appears to be the Digital Alpha 21164. It is a four-
`issue machine comprised of nearly 10 million
`transistors
`in
`0.35~micron technology and features a two-level on-chip cache
`architecture.
`It is assembled
`in a 499-pin PGA package.
`
`first
`that
`products
`features and the commercial
`Figure 1. Key microprocessor
`Report, Aug. 5, 1996, with Motorola
`incorporated
`them.
`(Source: Microprocessor
`data points added.)
`
`and relentlessly
`increased dramatically
`Transistor counts
`over the past 25 years (Figure 1). The trend line shows near-
`ly linear
`(in log
`terms)
`increases
`in transistor count over a
`25year period.
`
`design
`Microprocessor
`in the mid-1990s
`Phil Smith, Motorola
`
`Product complexity has increased over a hundredfold
`since the late 1970s so no single silicon guru can mas-
`termind a design. Large groups of engineers and layout
`designers, many with software backgrounds, work on
`each new microprocessor architecture. But to assist them,
`each is equipped with a workstation
`10 times more pow-
`erful
`than the lone mainframe
`that supported an entire
`development
`group of the past. Hundreds of highly spe-
`cialized software
`tools, from logic synthesis to &analy-
`to
`sis to full-chip
`layout verification,
`allow each designer
`complete multiple
`computer
`simulations
`per day.
`Modeling
`the behavior of the integrated
`circuit before
`first silicon has become
`the key to product quality.
`One aspect remains
`the same; the specification
`is still
`a large computer
`file, developed after lengthy discussions
`with customers. Making
`trade-offs may never go away.
`
`Bob Smith, Motorola
`
`the
`launched,
`has been
`Once a new architecture
`demand
`for custom derivatives must be satisfied at the
`earliest time possible. Modem derivative designs rely on
`disciplined, modular
`reuse strategies. The specifications,
`based on existing
`functional blocks,
`timers, serial inter-
`faces, and memories, are assembled using a graphical user
`interface. Software checks the consistency of the specifi-
`cation and allows designers to explore what-if scenar