`
`IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`___________________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`___________________________
`
`
`DIODES INCORPORATED,
`
`Petitioner,
`
`v.
`
`NORTH PLATE SEMICONDUCTOR, LLC,
`
`Patent Owner.
`
`
`U.S. Patent No. 7,564,097
`Issue Date: July 21, 2009
`Title: TRENCH-GATED MOSFET INCLUDING
`SCHOTTKY DIODE THEREIN
`
`___________________________
`
`Inter Partes Review No. IPR2018-01196
`___________________________
`
`PETITION FOR INTER PARTES REVIEW
`OF U.S. PATENT NO. 7,564,097
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` Petition for Inter Partes Review of U.S. Patent No. 7,564,097
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`PETITIONER’S EXHIBIT LIST (37 C.F.R. § 42.63(e))
`
`
`EXHIBIT
`1001
`
`DESCRIPTION
`U.S. Patent No. 7,564,097 to Ono et al. (“the ‘097 patent”)
`
`1002
`
`1003
`
`1004
`
`1005
`
`1006
`
`1007
`
`1008
`
`1009
`
`File History of U.S. Patent No. 7,564,097 to Ono et al.
`
`U.S. Pub. No. 2003/0040144 to Blanchard et al. (“Blanchard”)
`
`U.S. Pub. No. 2003/0020134 to Werner et al. (“Werner”)
`
`U.S. Patent No. 6,724,039 to Blanchard (“Blanchard '039”)
`
`U.S. Pub. No. 2004/0164304 to Magri et al. (“Magri”)
`
`Declaration of Sanjay Banerjee, Ph.D.
`
`Curriculum Vitae of Sanjay Banerjee, Ph.D.
`
`Selected pages from STEVEN M. KAPLAN, WILEY ELECTRICAL AND
`ELECTRONICS ENGINEERING DICTIONARY (John Wiley & Sons,
`Inc. 2004).
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` Petition for Inter Partes Review of U.S. Patent No. 7,564,097
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`TABLE OF CONTENTS
`
`C.
`
`
`INTRODUCTION ...................................................................................... - 1 -
`I.
`II. MANDATORY NOTICES (37 C.F.R. § 42.8(a)(1)) ................................. - 3 -
`A.
`Real Party-in-Interest (37 C.F.R. § 42.8(b)(1)) ................................ - 3 -
`B.
`Related Matters (37 C.F.R. § 42.8(b)(2)) ......................................... - 3 -
`C.
`Designation of Lead and Back-Up Counsel (37 C.F.R.
`§ 42.8(b)(3)) ..................................................................................... - 3 -
`Service Information (37 C.F.R. § 42.8(b)(4)) .................................. - 3 -
`D.
`III. PAYMENT OF FEES (37 C.F.R. § 42.103) .............................................. - 3 -
`IV. REQUIREMENTS FOR IPR PETITION UNDER 37 C.F.R. § 42.104 .... - 4 -
`A. Grounds for Standing (37 C.F.R. § 42.104(a)) ................................ - 4 -
`B.
`Claims for Which Review Is Requested (37 C.F.R. §
`42.104(b)(1)) .................................................................................... - 4 -
`Statutory Grounds of Challenge and Prior Art Relied Upon for
`Each Ground (37 C.F.R. § 42.104(b)(2)) ......................................... - 4 -
`Relevant Dates for the Prior Art Relied Upon ................................. - 6 -
`D.
`Person of Ordinary Skill in the Art .................................................. - 6 -
`E.
`Claim Construction (37 C.F.R. § 42.104(b)(3)) ............................... - 6 -
`F.
`G. Unpatentability of the Construed Claims (37 C.F.R. §
`42.104(b)(4)) .................................................................................. - 11 -
`Supporting Evidence (37 C.F.R. § 42.104(b)(5)) .......................... - 11 -
`H.
`THE '097 PATENT .................................................................................. - 11 -
`A. Overview of the '097 Patent ........................................................... - 11 -
`B.
`Priority Date of the Claims of the '097 Patent ............................... - 14 -
`VI. SUMMARY OF PRIOR ART APPLIED IN THIS PETITION .............. - 14 -
`A. U.S. Publication 2003/0040144 to Blanchard et al. (Exh. 1003) ... - 14 -
`B.
`U.S. Publication 2003/0020134 to Werner et al. (Exh. 1004) ....... - 17 -
`C.
`U.S. Patent No. 6,724,039 to Blanchard (Exh. 1005) .................... - 21 -
`D. U.S. Publication 2004/0164304 to Magri et al. (Exh. 1006) ......... - 22 -
`
`V.
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` Petition for Inter Partes Review of U.S. Patent No. 7,564,097
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`B.
`
`C.
`
`VII. DETAILED EXPLANATION OF GROUNDS ....................................... - 24 -
`A. Ground 1: Claims 1-5 Are Unpatentable Under Pre-AIA
`35 U.S.C. § 102 over Blanchard (Exh. 1003) ................................ - 24 -
`Ground 2: Claims 1-5 Are Unpatentable Under Pre-AIA
`35 U.S.C. § 103(a) over Blanchard (Exh. 1003) in view of
`Magri (Exh. 1006) .......................................................................... - 48 -
`Ground 3: Claims 1-5 Are Unpatentable Under Pre-AIA
`35 U.S.C. § 102 over Werner (Exh. 1004) ..................................... - 57 -
`D. Ground 4: Claim 3 Is Unpatentable Under Pre-AIA 35 U.S.C.
`§ 103(a) over Werner (Exh. 1004) in view of Blanchard '039
`(Exh. 1005) ..................................................................................... - 77 -
`Ground 5: Claims 1-5 Are Unpatentable Under Pre-AIA
`35 U.S.C. § 103(a) over Werner (Exh. 1004) in view of Magri
`(Exh. 1006) ..................................................................................... - 82 -
`VIII. CONCLUSION ......................................................................................... - 87 -
`
`
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`E.
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` Petition for Inter Partes Review of U.S. Patent No. 7,564,097
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`
`TABLE OF AUTHORITIES
`
`Page(s)
`
`
`Cases
`Phillips v. AWH Corp.
`415 F.3d 1303 (Fed. Cir. 2005) ............................................................................ 7
`In re Translogic Tech., Inc.
`504 F.3d 1249 (Fed. Cir. 2007) ............................................................................ 7
`Statutes
`35 U.S.C. § 102 ...................................................................................... 2, 5, 6, 24, 57
`Other Authorities
`37 C.F.R. § 42.6 ....................................................................................................... 89
`37 C.F.R. § 42.8 ......................................................................................................... 3
`37 C.F.R. § 42.15 ....................................................................................................... 3
`37 C.F.R. § 42.24 ..................................................................................................... 88
`37 C.F.R. § 42.24 ..................................................................................................... 88
`37 C.F.R. § 42.100 ..................................................................................................... 6
`37 C.F.R. § 42.103 ..................................................................................................... 3
`37 C.F.R. § 42.104 ........................................................................................... 4, 6, 11
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`I. INTRODUCTION
`Diodes Incorporated (“Diodes” or “Petitioner”) hereby petitions for inter
`
`partes review, seeking cancellation of claims 1-5 of U.S. Patent No. 7,564,097 (“the
`
`'097 patent”), Exh. 1001, which is owned by North Plate Semiconductor, LLC.
`
`The '097 patent states that it “relates to a trench MOSFET including a gate
`
`electrode having a trench gate structure and, particularly to the trench MOSFET in
`
`which parallel [S]chottky diodes are formed and housed between a source and a
`
`drain thereof.” Exh. 1001, 1:17-21. The '097 patent purports to claim the
`
`advantage of reducing device cost “to house the [S]chottky diode having the small
`
`area occupation on a semiconductor substrate” and “to secure an avalanche
`
`tolerance in a state that a backward voltage is applied to the [S]chottky diode.”
`
`Exh. 1001, 3:60-4:3.
`
`The specification of the '097 patent nonetheless makes clear that integrating
`
`a Schottky diode with a MOSFET predates the alleged invention of the ‘097 patent
`
`and was conventional in the art. Exh. 1001, 1:62-2:4.
`
`Not only were Schottky diodes well known in prior-art MOSFETs, but the
`
`claims of the '097 patent do not actually include a Schottky diode as a claim
`
`limitation. Instead, claim 1 of the ‘097 patent recites a conventional trench
`
`MOSFET having a “metal layer,” which is described as reaching a certain depth.
`
`As recited in claim 1 (the only independent claim in the patent), the trench
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` Petition for Inter Partes Review of U.S. Patent No. 7,564,097
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`MOSFET comprises a gate electrode having a typical trench-gate structure and five
`
`layers: (1) “an n-type diffusion layer,” (2) “a p-type base layer,” (3) “an n-type
`
`epitaxial layer,” (4) “a metal layer,” and (5) “a p-type layer with higher impurity
`
`concentration.”
`
`Before the priority date of the '097 patent, it was well known to people of
`
`ordinary skill in the art to have a trench MOSFET comprising such a gate electrode
`
`and the five layers, in the configuration recited in claims 1-5 of the '097 patent.
`
`For example, U.S. Patent Application Publication No. 2003/0040144 to Blanchard
`
`et al. (“Blanchard” or Exh. 1003) teaches a trench MOSFET comprising a gate
`
`electrode having a trench-gate structure and the five layers recited in the '097
`
`patent. So does U.S. Patent Application Publication No. 2003/0020134 to Werner
`
`et al. (“Werner” or Exh. 1004). These references also teach the Schottky diode.
`
`This petition demonstrates that claims 1-5 (the “Challenged Claims”) of the
`
`'097 patent are unpatentable under pre-AIA 35 U.S.C. § 102 and/or 103(a), and that
`
`there is a reasonable likelihood that Petitioner will prevail based upon prior art that
`
`the U.S. Patent and Trademark Office (“PTO”) did not consider during
`
`prosecution. Accordingly, and for the reasons set forth below, Petitioner
`
`respectfully requests inter partes review of the Challenged Claims.
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` Petition for Inter Partes Review of U.S. Patent No. 7,564,097
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`II. MANDATORY NOTICES (37 C.F.R. § 42.8(a)(1))
`A. Real Party-in-Interest (37 C.F.R. § 42.8(b)(1))
`The real party-in-interest is Diodes Incorporated, a Delaware corporation
`
`having a principal place of business in Plano, Texas.
`
`B. Related Matters (37 C.F.R. § 42.8(b)(2))
`Petitioner is aware of the following district court proceeding involving the
`
`'097 patent: North Plate Semiconductor, LLC v. Diodes Incorporated, No. 4:17-
`
`cv-00816-ALM (U.S. District Court, Eastern District of Texas).
`
`C. Designation of Lead and Back-Up Counsel (37 C.F.R. § 42.8(b)(3))
`
`Lead Counsel
`Darren M. Franklin (Reg. No. 51,701)
`Sheppard, Mullin, Richter & Hampton LLP
`333 South Hope Street, 43rd Floor
`Los Angeles, California 90071-1422
`Telephone: (213) 620-1780
`Fax: (213) 620-1398
`E-mail: dfranklin@sheppardmullin.com
`
`Service Information (37 C.F.R. § 42.8(b)(4))
`Please address all correspondence to the lead counsel at the address above.
`
`Back-Up Counsel
`Scott R. Miller (Reg. No. 32,276)
`Sheppard, Mullin, Richter & Hampton LLP
`333 South Hope Street, 43rd Floor
`Los Angeles, California 90071-1422
`Telephone: (213) 620-1780
`Fax: (213) 620-1398
`E-mail: smiller@sheppardmullin.com
`
`D.
`
`Petitioner consents to electronic service at the above e-mail addresses.
`
`III. PAYMENT OF FEES (37 C.F.R. § 42.103)
`The undersigned attorney for Petitioner authorizes the PTO to charge
`
`$30,500 ($15,500 request fee and $15,000 post-institution fee) to Deposit Account
`
`No. 19-1853 (Customer ID No. 113671) for the fee required by 37 C.F.R.
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` Petition for Inter Partes Review of U.S. Patent No. 7,564,097
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`§ 42.15(a) for this petition, and further authorizes payment of any additional fees to
`
`be charged to this Deposit Account. The PTO is also authorized to charge all fees
`
`due at any time during this proceeding to Deposit Account No. 19-1853.
`
`IV. REQUIREMENTS FOR IPR PETITION UNDER 37 C.F.R. § 42.104
`A. Grounds for Standing (37 C.F.R. § 42.104(a))
`Petitioner certifies that (1) the '097 patent is available for inter partes
`
`review; (2) Petitioner is not barred or estopped from requesting inter partes review
`
`challenging the claims of the '097 patent on the grounds identified in this petition;
`
`(3) this petition is filed within one year of the service of the original complaint
`
`against Petitioner in the litigation identified above; and (4) Petitioner has not filed
`
`a civil action challenging the validity of a claim of the '097 patent.
`
`B. Claims for Which Review Is Requested (37 C.F.R. § 42.104(b)(1))
`Petitioner requests inter partes review and cancellation of claims 1-5 of the
`
`'097 patent (the “Challenged Claims”).
`
`C.
`
`Statutory Grounds of Challenge and Prior Art Relied Upon for Each
`Ground (37 C.F.R. § 42.104(b)(2))
`Petitioner seeks inter partes review and cancellation of the Challenged
`
`Claims on the grounds listed below. Copies of the references listed below are filed
`
`with this petition.
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` Petition for Inter Partes Review of U.S. Patent No. 7,564,097
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`Ground 1: Claims 1-5 are unpatentable under pre-AIA 35 U.S.C. § 102 over
`
`U.S. Patent Application Publication No. 2003/0040144 to Blanchard et al. (Exh.
`
`1003).
`
`Ground 2: Claims 1-5 are unpatentable under pre-AIA 35 U.S.C. § 103(a)
`
`over U.S. Patent Application Publication No. 2003/0040144 to Blanchard et al.
`
`(Exh. 1003) in view of U.S. Patent Application Publication No. 2004/0164304 to
`
`Magri et al. (Exh. 1006).
`
`Ground 3: Claims 1-5 are unpatentable under pre-AIA 35 U.S.C. § 102 over
`
`U.S. Patent Application Publication No. 2003/0020134 to Werner et al. (Exh.
`
`1004).
`
`Ground 4: Claim 3 is unpatentable under pre-AIA 35 U.S.C. § 103(a) over
`
`U.S. Patent Application Publication No. 2003/0020134 to Werner et al. (Exh.
`
`1004) in view of U.S. Patent No. 6,724,039 to Blanchard (Exh. 1005).
`
`Ground 5: Claims 1-5 are unpatentable under pre-AIA 35 U.S.C. § 103(a)
`
`over U.S. Patent Application Publication No. 2003/0020134 to Werner et al. (Exh.
`
`1004) in view of U.S. Patent Application Publication No. 2004/0164304 to Magri
`
`et al. (Exh. 1006).
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` Petition for Inter Partes Review of U.S. Patent No. 7,564,097
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`D. Relevant Dates for the Prior Art Relied Upon
`Blanchard (Exh. 1003) was published on February 27, 2003 and issued on
`
`September 16, 2003 from an application filed on August 23, 2001 and thus is prior
`
`art under at least pre-AIA 35 U.S.C. §§ 102(a), (b), (e).
`
`Werner (Exh. 1004) was published on January 30, 2003 and issued on
`
`February 14, 2006 from an application filed on May 16, 2002 and thus is prior art
`
`under at least pre-AIA 35 U.S.C. §§ 102(a), (b), (e).
`
`Blanchard '039 (Exh. 1005) was issued on April 20, 2004 from an
`
`application filed on August 31, 1998 and thus is prior art under at least pre-AIA 35
`
`U.S.C. §§ 102(a), (e).
`
`Magri (Exh. 1006) was filed on November 14, 2003 and thus is prior art
`
`under at least pre-AIA 35 U.S.C. § 102(e).
`
`E.
`
`Person of Ordinary Skill in the Art
`A person of ordinary skill in the art of the '097 patent at the time of the
`
`alleged invention had a bachelor’s degree in electrical engineering or an equivalent
`
`field, plus about three years of experience working in the field of semiconductor
`
`device design or fabrication. Exh. 1007 ¶¶ 37-39.
`
`F. Claim Construction (37 C.F.R. § 42.104(b)(3))
`In an inter partes review, the Patent Trial and Appeal Board (the “Board”)
`
`construes claim terms in an unexpired patent according to their broadest reasonable
`
`construction in light of the specification. 37 C.F.R. § 42.100(b). Under this
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`standard, claim terms are given their ordinary and accustomed meaning as would
`
`be understood by a person of ordinary skill in the art in the context of the entire
`
`disclosure. See In re Translogic Tech., Inc., 504 F.3d 1249, 1257 (Fed. Cir. 2007).
`
`For this proceeding, Petitioner believes that the Board should interpret the
`
`Challenged Claims consistent with their ordinary and customary meaning within
`
`the context of the '097 patent. Further context regarding the meanings of certain
`
`terms is set forth below.1
`
`The claims of the '097 patent describe a trench MOSFET. Claim 1 is the
`
`only independent claim, and it has seven basic elements: (1) a gate electrode; (2) a
`
`gate insulating film; (3) an n-type diffusion layer; (4) a p-type base layer; (5) an n-
`
`type epitaxial layer; (6) a metal layer; and (7) a second p-type layer.
`
`All elements in the claims of the '097 patent are in terms commonly
`
`understood and have ordinary and widely accepted meanings as of the earliest
`
`possible effective filing date of the patent. Exh. 1007 ¶ 44. Under the broadest
`
`reasonable construction, a person of ordinary skill would have understood the
`
`terms used in claim 1 as follows:
`
`
`1 Petitioner reserves the right to propose different constructions in other
`proceedings and in particular district court litigation, for which the narrower claim
`construction standard of Phillips v. AWH Corp., 415 F.3d 1303 (Fed. Cir. 2005),
`applies.
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` Petition for Inter Partes Review of U.S. Patent No. 7,564,097
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`1.
`
`Under the broadest reasonable construction, a “trench MOSFET” is a
`
`metal-oxide semiconductor field-effect transistor of which portions are formed in a
`
`trench of the semiconductor chip. The portions that are in the trench include the
`
`gate electrode and the gate insulating film. Exh. 1001, 1:36-37, FIG. 6; Exh. 1007
`
`¶ 46; Exh. 1009 at 483.
`
`2.
`
`Under the broadest reasonable construction, a “gate electrode” is a
`
`terminal of a MOSFET that controls the formation of a channel in the
`
`semiconductor body region. Exh. 1001, 7:35-37, 7:47-58, FIG. 6 (item 27); Exh.
`
`1007 ¶ 47; Exh. 1009 at 312.
`
`3.
`
`Under the broadest reasonable construction, a “trench gate
`
`structure” is a semiconductor device structure in which at least a portion of the
`
`gate electrode and the corresponding portion of the gate insulating film are formed
`
`in a trench. Exh. 1001, 7:47-60, FIG. 6 (item 27); Exh. 1007 ¶ 48.
`
`4.
`
`Under the broadest reasonable construction, a “gate insulating film”
`
`is a film of insulating material between the body region and the gate electrode.
`
`Exh. 1001, 7:35-37, FIG. 6 (item 28); Exh. 1007 ¶ 49.
`
`5.
`
`Under the broadest reasonable construction, an “n-type” layer is a
`
`layer of semiconductor material which has more n-type dopant ions than p-type
`
`dopant ions. Exh. 1001, 10:31-35; Exh. 1007 ¶ 50; Exh. 1009 at 494.
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` Petition for Inter Partes Review of U.S. Patent No. 7,564,097
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`6.
`
`Under the broadest reasonable construction, a “diffusion layer” is a
`
`layer of semiconductor material within which dopant ions have been dispersed by
`
`thermal diffusion. Exh. 1001, 7:37-40, FIG. 6 (item 25); Exh. 1007 ¶ 51; Exh.
`
`1009 at 187.
`
`7.
`
`Under the broadest reasonable construction, a “layer formed to face
`
`the gate electrode via the gate insulating film” is a layer having a portion near
`
`the gate electrode with the gate insulating film between the layer and the gate
`
`electrode. Exh. 1001, FIG. 6; Exh. 1007 ¶ 52.
`
`8.
`
`Under the broadest reasonable construction, a “p-type” layer is a layer
`
`of semiconductor material which has more p-type dopant ions than n-type dopant
`
`ions. Exh. 1001, 10:31-35; Exh. 1007 ¶ 53; Exh. 1009 at 547.
`
`9.
`
`Under the broadest reasonable construction, a “base layer,” for an n-
`
`type MOSFET, is a region of p-type semiconductor between the source region and
`
`the drain region. Exh. 1001, 7:33-35, FIG. 6 (item 34c); Exh. 1007 ¶ 54.
`
`10. Under the broadest reasonable construction, an “epitaxial layer” is a
`
`layer of semiconductor material formed on a substrate of a proper crystalline
`
`structure, typically the same as that of the underlying substrate. Exh. 1001, 7:25-
`
`31, FIG. 6 (item 23); Exh. 1007 ¶ 55; Exh. 1009 at 260-61.
`
`11. Under the broadest reasonable construction, a “metal layer departing
`
`from the trench in parallel with a depth direction of the trench” is a conductive
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`layer comprising metal and having a portion extending into the semiconductor
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`body in substantially the same direction as the trench. Exh. 1001, 7:61-63, FIG. 6
`
`(item 39); Exh. 1007 ¶ 56.
`
`12. Under the broadest reasonable construction, an “impurity
`
`concentration” is a measurement of the density of a dopant within a host
`
`semiconductor material. Exh. 1007 ¶ 57; Exh. 1009 at 364.
`
`Claim 2 describes a depth of the metal layer. All elements in claim 2 have
`
`their common, ordinary and widely understood and accepted meanings. Exh. 1007
`
`¶ 58.
`
`Claim 3 describes a depth of the metal layer. All elements in claim 3 have
`
`their common, ordinary and widely understood and accepted meanings. To the
`
`extent that a construction is needed for this proceeding under the broadest
`
`reasonable construction, “a deepest portion of the p-type base layer” is the
`
`portion of the p-type base layer that is the farthest from the n-type diffusion layer.
`
`Exh. 1001, FIG. 6 (deepest portion of item 34c); Exh. 1007 ¶ 59.
`
`Claim 4 describes a depth of a deepest portion of the base layer. All
`
`elements in claim 4 have their common, ordinary and widely understood and
`
`accepted meanings. The phrase “a deepest portion of the p-type base layer” is
`
`defined above.
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` Petition for Inter Partes Review of U.S. Patent No. 7,564,097
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`Claim 5 describes side surfaces of the metal layer. All elements in claim 5
`
`have their common, ordinary and widely understood and accepted meanings. To
`
`the extent that a construction is needed for this proceeding under the broadest
`
`reasonable construction, “side surfaces of the metal layer” means the surfaces of
`
`the metal layer that extend downwardly into the semiconductor body. Exh. 1001,
`
`FIG. 6 (side surfaces of item 39); Exh. 1007 ¶ 61.
`
`G. Unpatentability of the Construed Claims (37 C.F.R. § 42.104(b)(4))
`Claims 1-5 of the '097 patent are unpatentable under the statutory grounds
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`identified above, as explained in Section VII below.
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`H.
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`Supporting Evidence (37 C.F.R. § 42.104(b)(5))
`The exhibit numbers of the supporting evidence relied upon to support the
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`challenge and the relevance of the evidence to the challenge raised, including the
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`specific portions of the evidence that support the challenge, are provided in the
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`exhibit list above and Section VII below.
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`V. THE '097 PATENT
`A. Overview of the '097 Patent
`The ‘097 patent discloses a trench MOSFET structure that comprises
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`ordinary trench MOSFET components, such a trench gate, a gate electrode, an n-
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`type source layer, a p-type base layer arranged over an n-type epitaxial layer, and a
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`metal layer formed in a separate trench in parallel to the gate trench. The metal
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`layer penetrates the source layer and the p-type base layer to reach the n-type
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`epitaxial layer and comes in contact with a p-type region having a higher impurity
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`concentration than the p-type base layer. The entire structure, including the trench
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`gate, the base layer, the more heavily doped p-type region, and the metal layer,
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`along with the depths of the gate trench, the metal layer, and the base layer with
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`respect to each other, were well known in the art of semiconductor devices before
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`the priority date of the '097 patent. Exh. 1007 ¶¶ 32-34.
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`Figure 6 of the '097 patent (reproduced below) was chosen for the face page
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`of the patent and shows an embodiment of the alleged invention:
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`Figure 6 of the '097 patent shows the gate electrode 27, the gate insulating film 28,
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`the n-type diffusion layer 25, the p-type base layer 34c, the n-type epitaxial layer
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`23, the metal layer 39, and the high-concentration p-type layer 34b. Exh. 1007
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`¶¶ 35-36.
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`B.
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`Priority Date of the Claims of the '097 Patent
`The '097 patent claims priority to U.S. Application No. 11/127,224 filed on
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`May 12, 2005, which claims priority to JP 2005-112645 filed on April 8, 2005 and
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`JP 2004-145265 filed on May 14, 2004.
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`VI. SUMMARY OF PRIOR ART APPLIED IN THIS PETITION
`A. U.S. Publication 2003/0040144 to Blanchard et al. (Exh. 1003)
`Blanchard discloses a multiple-cells MOSFET structure merged with a
`plurality of Schottky rectifier cells, and a method of designing and making such a
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`MOSFET structure. Exh. 1003, Abstract; Exh. 1007 ¶ 62. As explained in the
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`claim analysis below, Blanchard’s MOSFET structure meets all of the limitations
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`of claims 1-5 of the '097 patent.
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`More particularly, Blanchard discloses embodiments that include all
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`components of the MOSFET in the ‘097 patent, including an n-source region at the
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`top, a p-body (base) region in the middle, an n-region (n-epitaxial layer) at a lower
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`portion, and a gate region adjacent to the source region, the body region, and the
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`epitaxial region. The Schottky diode cells are disposed within a trench network
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`and comprise a conductor portion in Schottky rectifying contact penetrating the
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`source and the body regions and contacting the n-epitaxial region. In the various
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`embodiments, a MOSFET cell gate region is positioned along a sidewall of the
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`trench network and adjacent to at least one Schottky diode cell. Exh. 1003,
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`Abstract. In addition, Blanchard discloses the possible relative depths of the gate
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`trench, the Schottky rectifying contact, and the p-body region. Furthermore,
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`Blanchard discloses that the body region and the conductor portion contact a more
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`heavily doped p-type region. Exh. 1003 ¶ 0055; Exh. 1007 ¶ 63.
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`Figure 7 of Blanchard (reproduced below) shows an embodiment of the
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`merged trench MOSFET and Schottky-diode structure:
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`Among other things, Figure 7 of Blanchard shows:
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`•
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`•
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`conductive regions 211 that function as gate electrodes and are formed
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`in trenches 219a and 219c;
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`an insulating film 210 that surrounds each gate electrode 211;
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`an n-type layer formed through diffusion at an upper portion of the
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`gate trenches 219a and 219c, the n-type layer facing the gate
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`electrodes 211 via the gate insulating film 210;
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`•
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`a p-type body (base) layer that faces the gate electrodes 211 via the
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`gate insulating film 210 below the n-type diffusion layer;
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`an n-type epitaxial layer 201 having an n-type region 202 that faces
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`the gate electrodes 211 via the gate insulating film 210 below the p-
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`type body (base) layer;
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`•
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`a conductor 218 that comprises metal and has a portion formed in the
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`trench 219b, the portion departing from the gate trenches 219a and
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`219c in parallel with a depth direction of the trenches, the portion
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`penetrating the n-type diffusion layer and the p-type body (base) layer
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`to reach the n-type region 202 of the n-type epitaxial layer 201; and
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`•
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`a p+ layer that has a higher impurity concentration than the p-type
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`body (base) layer and is located to be in contact with the p-type body
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`(base) layer and the metal conductor 218. Exh. 1007 ¶¶ 64-65.
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`Additionally, Figure 7 of Blanchard shows that the depth of the metal
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`conductor 218 is shallower than a depth of a deepest portion of the p-type body
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`(base) layer, shown as a p+ region at the bottom of the layer. The depth of the
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`deepest portion of the p-type base layer is deeper than the depths of the gate
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`trenches 219a and 219c, as well as the metal conductor 218. Finally, side surfaces
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`of the metal conductor 218 are not in contact with the n-type epitaxial layer 201 or
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`its n-type region 202. Exh. 1007 ¶ 66.
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`B. U.S. Publication 2003/0020134 to Werner et al. (Exh. 1004)
`Werner discloses a semiconductor MOS transistor which has a gate
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`electrode arranged in a trench running in the vertical direction of a semiconductor
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`body, and a Schottky diode which is connected in parallel with a drain-source path
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`(D-S) and is formed by a Schottky contact between a source electrode and the
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`semiconductor body. Exh. 1004, Abstract; Exh. 1007 ¶ 67. As explained in the
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`claim analysis below, Werner’s MOS transistor meets all of the limitations of
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`claims 1-5 of the '097 patent.
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`More particularly, Werner discloses a trench MOSFET having a metal
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`trench that forms a Schottky diode where the metal trench passes through the
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`source region and the body (base) layer and reaches the n-type epitaxial layer.
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`Exh. 1004, Fig. 10b; Exh. 1007 ¶ 68. Figure 10b is reproduced below:
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`Werner further discloses a trench MOSFET having a metal trench and a base
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`region that is extended by a more heavily doped region at the bottom, a portion of
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`the more heavily doped region being deeper than the gate trench and the metal
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`trench. Exh. 1004, Fig. 10a. Regions having the Schottky diode of Figure 10b and
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`regions having the more heavily doped region of Figure 10a alternate with one
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`another within the same embodiment. Exh. 1004 ¶ 0086; Exh. 1007 ¶ 69. Figure
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`10a is reproduced below:
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`Among other things, Figures 10a and 10b of Werner show:
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`•
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`•
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`gate electrodes 40 formed in trenches 17;
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`an insulating film 52 that surrounds each gate electrode 40;
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`an n-doped layer 30 formed through diffusion at an upper portion of
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`the gate trenches 17, the n-doped layer facing the gate electrodes 40
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`via the gate insulating film 52;
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`a p-doped base layer 20 that faces the gate electrodes 40 via the gate
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`insulating film 52 below the n-doped diffusion layer 30;
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`an n-doped epitaxial layer 12 that faces the gate electrodes 40 via the
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`gate insulating film 52 below the p-doped base layer 20;
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`a source electrode 60 that comprises metal and has a portion formed in
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`the trench 62, the portion departing from the gate trenches 17 in
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`parallel with a depth direction of the trenches, the portion penetrating
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`the n-doped diffusion layer 30 and the p-doped base layer 20 to reach
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`the n-doped epitaxial layer 12 (see, e.g., Exh. 1004 ¶ 0089 (“The
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`trench 62 is then produced, which reaches through the source zone 30
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`and the body zone 20 right into the drift zone 12.”); and
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`•
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`a p+ conducting layer 15 that has a higher impurity concentration than
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`the p-doped base layer 20 and is located to be in contact with the p-
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`doped base layer 20 and the metal source electrode 60. Exh. 1007
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`¶ 70.
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`Additionally, Figure 10a of Werner shows that the depth of the metal source
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`electrode 60 is shallower than a depth of the gate trenches 17, as well as a depth of
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`a deepest portion of the p-doped base layer 20 as extended by the p+ layer 15. The
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`depth of the deepest portion of the p-doped base layer 20 as extended by the p+
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`layer 15 is deeper than depths of the gate trenches 17, as well as the metal source
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`electrode 60. Finally, side surfaces of the metal source electrode 60 are not in
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`contact with the n-doped epitaxial layer 12. Exh. 1007 ¶ 71.
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`C. U.S. Patent No. 6,724,039 to Blanchard (Exh. 1005)
`Blanchard '039 teaches “a vertical DMOS transistor 60 having a built-in
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`Schottky diode.” Exh. 1005, 4:11-12. Figure 3A of Blanchard '039 (reproduced
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`below) shows an embodiment of the DMOS transistor:
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`
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`Among other things, Figure 3A of Blanchard '039 shows:
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`•
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`•
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`•
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`gate structures 68 having gate electrodes 72;
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`a gate insulating film 70 and side-wall insulators 74 that surround the
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`gate electrodes 72;
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`n-doped source regions 82 that face the gate electrodes 72 via the gate
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`insulating film 70;
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