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`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`
`
`DIODES INCORPORATED
`Petitioner
`v.
`
`NORTH PLATE SEMICONDUCTOR, LLC
`Patent Owner.
`
`
`
`Case IPR2018-01196
`U.S. Patent 7,564,097
`
`
`
`
`
`PATENT OWNER PRELIMINARY RESPONSE
`
`
`
`
`
`

`

`
`
`
`
`TABLE OF CONTENTS
`
`I. Introduction ......................................................................................................... 1
`II. Technology Background .................................................................................... 2
`A. Planar MOSFETs and Trench MOSFETs ..................................... 3
`B. Breakdown Voltage and On-Resistance ........................................ 6
`C.
`Integrated MOSFET and Schottky Diode ................................... 10
`III. The ‘097 Patent and Prosecution History ........................................................ 11
`A. The ‘097 Patent ........................................................................... 11
`B. Prosecution History of the ‘097 Patent ....................................... 13
`IV. Petitioner’s expert opinion testimony should be given no weight. ................. 17
`V. Claim Construction .......................................................................................... 19
`A. Petitioner’s Proposed Constructions ........................................... 19
`B. “metal layer departing from the trench in parallel with a depth
`direction of the trench” ....................................................................... 19
`VI. Ground 1: Claims 1-5 are not anticipated by Blanchard. ............................... 28
`A. Claim 1 is not anticipated by Blanchard. .................................... 28
`B. Claims 2-5 are not anticipated by Blanchard. ............................. 33
`VII. Ground 2: Claims 1-5 are not obvious over Blanchard in view of Magri. ... 33
`A. Claim 1 is not obvious over Blanchard in view of Magri. .......... 33
`B. Claims 2-5 are not obvious over Blanchard in view of Magri. ... 45
`VIII. Ground 3: Claims 1-5 are not anticipated by Werner. ................................. 45
`A. Overview of Werner .................................................................... 45
`B. Werner does not anticipate elements [1f] or [1g]. ....................... 49
`1. Element [1f] ............................................................................................... 50
`2. Element [1g] ............................................................................................... 53
`C. Petitioner cannot argue that it would have been obvious to
`combine FIGS. 10a and 10b. .............................................................. 54
`D. Claims 2-5 are not anticipated by Werner. ................................. 54
`IX. Ground 4: Claim 3 is not obvious over Werner in view of Blanchard ‘039. . 55
`X. Ground 5: Claims 1-5 are not obvious over Werner in view of Magri. .......... 55
`A. Claim 1 is not obvious over Werner in view of Magri. .............. 55
`B. Claims 2-5 are not obvious over Werner in view of Magri. ....... 61
`XI. Conclusion ...................................................................................................... 62
`
`
`
`
`
`ii
`
`

`

`
`
`
`
`TABLE OF AUTHORITIES
`
`
`Curtiss-Wright Flow Control Corp. v. Velan, Inc.,
`438 F.3d 1374 (Fed. Cir. 2006) ......................................................................... 22
`
`DePuy Spine, Inc. v. Medtronic Sofamor Danek, Inc.,
`567 F.3d 1314 (Fed. Cir. 2009). ........................................................................ 44, 61
`
`In re: Smith Int’l, Inc.,
`871 F.3d 1375 (2017) ........................................................................................ 24
`
`Intelligent Bio-Systems, Inc. v. Illumina-Cambridge Ltd.,
`821 F.3d 1359 (Fed. Cir. 2016) ......................................................................... 42
`
`KSR Int’l v. Teleflex Inc.,
`550 U.S. 398 (2007) .......................................................................................... 44, 60
`
`Sensus USA, Inc. v. Certified Measurement, LLC,
`IPR2015-01439, Paper 13 ................................................................................. 18
`
`Medichem, S.A. v. Rolabo, S.L.,
`437 F.3d 1157 (Fed. Cir. 2006) ......................................................................... 44, 61
`
`Microsoft Corp. v. Proxyconn, Inc.,
`789 F.3d 1292 (Fed. Cir. 2015) ......................................................................... 24
`
`Monsanto Co. v. Pioneer Hi-Bred Int’l, Inc.,
`IPR2013-00022, Paper 43 ................................................................................. 18
`
`Pfizer, Inc. v. Apotex, Inc.,
`480 F.3d 1348 (Fed. Cir. 2007) ......................................................................... 44, 61
`
`
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`
`iii
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`

`

`EXHIBIT LIST
`
`
`
`
`
`2004
`
`2005
`
`
`Exhibit Description
`2001
`U.S. Patent No. 6,433,396 (“Kinzer”)
`2002
`Reserved
`2003
`“Graphic Symbols for Electrical and Electronics Diagrams (Including
`Reference Designation Letters,” IEEE Standard, American Nat’l
`Standard, Canadian Standard, IEEE Std 315-1975 (Reaffirmed 1993)
`(selected pages)
`B. Jayant Baliga, “Fundamentals of Power Semiconductor Devices”
`(2008, Springer) (selected section)
`R.K. Williams et al., “A 30V P-Channel Trench Gated DMOSFET with
`900 mW cm2 Specific On-Resistance at 2.7 V”, IEEE International
`Symposium on Power Semiconductor Devices and ICs, pp. 53-56, 1996
`B. Jayant Baliga, “Advanced Power MOSFET Concepts” (2010, Springer)
`(selected section)
`
`2006
`
`
`
`
`
`
`
`
`
`iv
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`

`

`
`
`
`
`North Plate Semiconductor, LLC (“North Plate” or “Patent Owner”)
`
`respectfully submits this Patent Owner Preliminary Response (“POPR”) to the
`
`Petition (“Pet.”) filed by Diodes Incorporated. (“Diodes” or “Petitioner”) on June
`
`5, 2018 seeking inter partes review of U.S. Patent No. 7,564,097 (“the ‘097
`
`patent”) (Ex. 1001). The Petition was filed on June 5, 2018, and thus this POPR is
`
`timely filed under 35 U.S.C. § 313 and 37 C.F.R. § 42.107.
`
`I.
`
`Introduction
`
`The ‘097 patent is directed to an integrated trench MOSFET with Schottky
`
`diode. Because Schottky diodes have low forward voltage drop, they suffer from
`
`high reverse leakage current, which reduces their efficiency. To overcome this
`
`problem, the ‘097 patent discloses an integrated trench MOSFET with Schottky
`
`diode having unique features distinguishable over the prior art. The device
`
`contains a vertical metal layer embedded within a second trench. In some
`
`embodiments, the p-body layer extends farther down along the sidewalls of the
`
`trench. In other embodiments, a higher-impurity p-doped region is in contact with
`
`the p-base layer and Schottky metal layer to increase the device’s avalanche
`
`tolerance.
`
`
`
`The Petition fails on many grounds. In Ground 1, Petitioner relies upon a
`
`claim construction of “metal layer” that is blatantly at odds with the patent’s
`
`intrinsic evidence. Indeed, Petitioner’s construction is undermined by the patent’s
`
`
`
`1
`
`

`

`
`
`
`
`prosecution history—and yet, Petitioner does not discuss the patent’s prosecution
`
`history whatsoever in its Petition.
`
`
`
`In Ground 2 and Ground 5, Petitioner proposes combinations of a planar
`
`MOSFET with a trench MOSFET. Yet, power semiconductors are highly and
`
`finely tuned devices. (See generally Ex. 2004 and 2006). Modifying one feature
`
`can gravely impact the performance of the device. (Id.). Petitioner does not even
`
`attempt to account for the myriad of technical distinctions between planar and
`
`trench MOSFETs, and the Petition contains no argument and no expert
`
`testimony—that is supported by actual evidence—showing that Petitioner’s
`
`proposed combination device would have a reasonable expectation of actually
`
`working.
`
`
`
`Finally, in Ground 3 and Ground 4, Petitioner grossly misreads the prior art
`
`reference (Werner). Werner teaches two different structural devices, in FIGS. 10a
`
`and 10b, respectively. Petitioner admits that neither figure individually anticipates
`
`all elements in the claims. Yet, Petitioner selectively cherry-picks different
`
`elements from each figure, even though the Werner reference expressly teaches
`
`that the figures are different and cannot be combined.
`
`II. Technology Background
`
`
`
`2
`
`

`

`
`
`
`
`A.
`
`Planar MOSFETs and Trench MOSFETs
`
`As of the priority date for the ‘097 patent, POSAs were aware of the
`
`MOSFET (metal-oxide-semiconductor field-effect transistor) power transistor.
`
`(Ex. 2004 at 9). Two prevalent commercially-available MOSFET structures are
`
`depicted below. The D-MOSFET, or “planar” MOSFET, was introduced in the
`
`1970’s, and the U-MOSFET, or “trench” MOSFET, was introduced in the 1990’s.
`
`(Id. at 9-10, 279-80).1
`
`
`1 The patent challenged in this Petition, the ‘097 patent, is directed to a “trench”
`
`MOSFET. (See independent claim 1). Yet, a brief discussion of the “planar”
`
`MOSFET is warranted for two reasons. First, the “trench” MOSFET structure
`
`evolved from the “planar” structure, as a way to reduce total on-resistance, as
`
`discussed infra. Second, Petitioner’s Grounds 2 and 5 argue that it would have
`
`been obvious to combine certain features from a “planar” device, disclosed in
`
`Magri (Ex. 1006), with “trench” devices, disclosed in Blanchard (Ex. 1003) and
`
`Werner (Ex. 1004).
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`
`3
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`

`

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`In the D-MOSFET (“planar” device), when a positive bias is applied to the
`
`drain, a high voltage can be supported. (Ex. 2004 at 285). The junction between
`
`the P-layer and the N-Drift Region is a P-N junction. (Ex. 2004 at 281). That
`
`junction is reverse-biased when the drain is positive biased. (Ex. 2004 at 285).
`
`Thus, no current flows between the Drain and the Source, and the device is in the
`
`OFF state. (Id. at 321). Yet, when a positive bias is applied to the Gate, the device
`
`is in the ON State. (Id. at 285). An inversion layer forms within the P-layer
`
`immediately underneath the Gate, and that inversion layer creates a channel, as
`
`shown in the figure below. (Id.). When a positive Drain voltage is applied, current
`
`flows through the channel, and electrons flow from the Source to the Drain. (Id.).
`
`
`
`4
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`

`

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`
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`Importantly, when the electrons flow out of the channel (the inverted P-layer under
`
`the Gate,) they enter the JFET Region, as shown in the figure above. (Ex. 2004 at
`
`285). The JFET Region increases the internal resistance of the “planar” device.
`
`(Id.). Eradicating the JFET Region, and the resistance contributed by the JFET
`
`Region, was one motivation for the “trench” MOSFET. (Ex. 2004 at 10).
`
`The U-MOSFET (“trench” device”) operates similarly to the “planar”
`
`device, except that the channel is vertical rather than horizontal. (Ex. 2004 at 286).
`
`This is shown in the figure below. When a positive bias is applied to the Gate, an
`
`inversion layer forms within the P-Base layer along the side of the Gate, and that
`
`inversion layer creates a channel. (Id.). When a positive Drain voltage is applied,
`
`current flows through the channel, and electrons flow from the Source to the Drain.
`
`(Id.).
`
`
`
`5
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`

`

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`
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`One advantage of “trench” MOSFETs over “planar” MOSFETs is that
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`“trench” MOSFETs can achieve substantially lower on-resistance. (Ex. 2006 at
`
`62; see Sec. II(B) for discussion of on-resistance). First, there is no JFET region in
`
`the “trench” MOSFET. (Ex. 2004 at 286). As discussed below, this significantly
`
`reduces the internal resistance of the device compared to the “planar” MOSFET.
`
`(Id.). Second, the channel density in a “trench” MOSFET can be increased
`
`because the “trench” structure affords much smaller cell pitch (horizontal distance
`
`between cells). (Id. at 63-64).
`
`B.
`
`Breakdown Voltage and On-Resistance
`
`
`
`Two dual goals of power MOSFETs are to increase breakdown voltage and
`
`lower on-resistance. The principle advantage of power semiconductors is their
`
`ability to withstand high voltages. (Ex. 2004 at 91). A high breakdown voltage is
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`desireable for certain power MOSFETs because they can sustain higher voltages.
`
`
`
`6
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`

`

`
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`
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`(Id. at 91 (“The most unique feature of power semiconductor devices is their
`
`ability to withstand high voltages”)). A semiconductor’s threshold for
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`withstanding high voltages is limited by the avalanche breakdown phenomena.
`
`(Id. (“the ability to support high voltages without the onset of significant current
`
`flow is limited by the avalanche breakdown phenomenon . . . . .”)).
`
`Yet, increasing breakdown voltage typically comes with a tradeoff—namely,
`
`simultaneously increasing the on-resistance. (See e.g., Ex. 2004 at 289 (describing
`
`how adjusting the resistance of the drift region, via doping concentration and
`
`thickness, correspondingly adjusts breakdown voltage); id. at 280 (for original
`
`power MOSFETs, “their power-handling capability was constrained by internal
`
`resistance within the structure between the drain and source electrodes”). A lower
`
`on-resistance is desireable for certain power MOSFETs because it results in
`
`increasing switching frequency. (Ex. 2004 at 279-280) (“The trench-gate . . .
`
`structure offered the opportunity to reduce the internal resistance of the power
`
`MOSFET . . . increasing the operating frequency . . . .”)).
`
`Breakdown voltage is the maximum voltage a device can sustain before
`
`failure. As discussed above, when a positive bias is applied to the Drain electrode,
`
`the P-N junction between the P-layer and the N-Drift Region is reversed biased.
`
`(Id. at 285). That creates a depletion region at that junction, and that depletion
`
`region supports the high voltage of a power semiconductor device. (Id. at 91).
`
`
`
`7
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`

`

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`
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`The depletion region is perpetuated by the electric field caused by the applied
`
`voltage in the depletion region, which sweeps out mobile carriers (either electrons
`
`or holes.) (Id.). As the voltage increases, so does the electric field, and so does the
`
`velocity of the mobile carriers. (Id.). Increasing the voltage further leads to a
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`multiplicative phenomenon that produces a cascade of mobile carriers with high
`
`velocity through the depletion region, which itself produces a high current. (Id. at
`
`91-92). After this point, since the device can no longer sustain higher voltages, it
`
`experiences avalanche breakdown. (Id. at 92). Thus, avalanche breakdown limits
`
`the operating voltage of power semiconductor devices; breakdown voltage is the
`
`maximum voltage that can be applied to the device before significant current.
`
`(Id.).
`
`On-resistance is the cumulative resistance that must be overcome to turn a
`
`device to its ON state. On-resistance measures the total resistance to current flow
`
`between the Source and Drain when the device in turned on. (Ex. 2004 at 327).
`
`On-resistance is customarily analyzed, in part, by analyzing the resistance for
`
`individual components within the device. (Id. at 328). The internal resistance
`
`components of both the “planar” and “trench” MOSFETs are illustrated in the
`
`figures below.
`
`
`
`8
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`

`

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`(Ex. 2004 at 328, 358).
`
`
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`As shown in the figures, the resistance components between the “planar”
`
`and “trench” MOSFETs are the same, with the exception of the JFET resistance
`
`(RJFET). (Ex. 2004 at 358). The JFET resistance is eliminated from the “trench”
`
`MOSFET. The reason the JFET resistance is eliminated is because “the trench
`
`extends beyond the bottom of the P-base region to form a channel connecting the
`
`N+ source region and the N-drift region.” (Id.). Elimination of the JFET
`
`resistance significantly reduces the overall on-resistance for two reasons—the
`
`elimination of a significant resistance component, but also because cell pitch
`
`(horizontal width of cell) can be reduced. (Id.). Reducing cell pitch reduces the
`
`resistance contributions from a number of different regions within the device.
`
`(Id.). Reducing the overall on-resistance of the power MOSFET with the “trench”
`
`design resulted in a desireable increase in switching frequency. (Id. at 280).
`
`
`
`9
`
`

`

`
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`
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`The total on-resistance can be measured by adding the individual component
`
`resistances. (Ex. 2004 at 365). The channel and drift region resistances are
`
`typically the largest components for “trench” MOSFETs, and can together
`
`contribute to more than 70% of the overall on-resistance. (Id. at 366). By contrast,
`
`other resistance components, such as the accumulation resistance, can be much
`
`smaller. (Id.).
`
`
`
`The on-resistance increases with an increasing channel length. (Ex. 2004 at
`
`362-63). The channel length is measured by the difference in depth of the P-base
`
`junction and the N+-source junctions. (Id.). Thus, increasing the channel length
`
`will increase the on-resistance. (Id.).
`
`C.
`
`Integrated MOSFET and Schottky Diode
`
`
`
`As discussed above in Sec. II(A), when the MOSFET is in the ON state, a
`
`positive bias is applied to the Drain. The diode at the junction between P-Base and
`
`the N-Drift Regions is thus reverse biased. When the MOSFET turns to the OFF
`
`state, a negative voltage may be applied to the Drain, and the diode at the junction
`
`between P-Base and the N-Drift Region may become forward biased. (Ex. 1003
`
`¶0003; Ex. 1004 ¶0003). When that happens, a large concentration of holes from
`
`the P-Base region is injected into the N-Drift Region. (Ex. 2006 at 400; Ex. 1004
`
`¶0004). That stored charge must be removed from the junction between the P-
`
`Base and N-Drift Regions before the MOSFET return to the ON State. (Ex. 2006
`
`
`
`10
`
`

`

`
`
`
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`at 400; Ex. 1003 ¶0005; Ex. 1004 ¶0004). Removing the stored charge creates a
`
`large reverse recovery current that leads to increased power loss, inefficiency and
`
`reduced switching speed. (Ex. 2006 at 399-400; Ex. 1003 ¶0005; Ex. 1004 ¶0004).
`
`
`
`To avoid forward-biasing the junction between the P-Base and N-Drift
`
`Regions during OFF state, MOSFETs have been integrated with a Schottky diode.
`
`(See e.g., Ex. 1003 ¶0004; Ex. 1004 ¶0004). By doing so, when the Drain is
`
`negative biased, current flows through the Schottky diode rather than the forward-
`
`biased junction between the P-Base and N-Drift Regions during OFF state. (Ex.
`
`1003 ¶¶0004, 0006; Ex. 1004 ¶0005). This is because the voltage drop across the
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`metal-semiconductor junction of the Schottky diode is less than that over the PN
`
`junction between the P-Base and N-Drift Regions. (Ex. 1003 ¶0004; Ex. 1004
`
`¶0004).
`
`III. The ‘097 Patent and Prosecution History
`
`A.
`
`The ‘097 Patent
`
`The ‘097 patent is directed to a trench-gated MOSFET including Schottky
`
`diode therein. (Ex. 1001, Title). The ‘097 patent explains that the claimed unique
`
`MOSFET disclosed has numerous advantages over the prior art.
`
`Because Schottky diodes have low forward voltage drop, they suffer from
`
`high reverse leakage current, which reduces their efficiency. (Ex. 1001 col. 8:39-
`
`41; col. 8:45-48). To illustrate this, the ‘097 patent discloses a comparative
`
`
`
`11
`
`

`

`
`
`
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`example in FIG. 12. (Ex. 1001 col. 7:1-2). The device in FIG. 12 exhibits a
`
`relatively high leakage current. (Id. col. 8:39-40; col. 8:45-48). This is because
`
`the surface contact between the metal layer 29 and n-type epitaxial layer 23 is
`
`relatively large. (Id. col. 8:37-39). Likewise, the corresponding contact between
`
`the metal layer 29 and p-type base layer 24 is comparatively smaller. (Id.). This
`
`means that the depletion regions formed at the junction between the n-type
`
`epitaxial 23 layer and p-type base layer 24 do not cover a substantial portion of the
`
`metal layer 29. (Id. col. 8:34-39).
`
`To overcome this problem, as shown in FIG. 2, in some embodiments, the
`
`‘097 patent discloses an integrated MOSFET with Schottky diode where the p-type
`
`base layer 34 extends farther down along the sidewalls of the trench containing
`
`metal layer 39. (Ex. 1001 col. 8:61-65). Accordingly, the depletion regions at the
`
`junction of the p-type base layer 34 and the n-type epitaxial layer 23 cover a
`
`greater portion of the surface contact between the metal layer 39 and n-type
`
`epitaxial layer 23. (Id. col. 8:65-9:1). Thus, when a reverse voltage is applied to
`
`the Schottky contact, the leakage current is reduced. (Id. col. 9:1-3; col. 8:63-65).
`
`In addition, the ‘097 patent discloses a higher-impurity p-doped region that
`
`is located in contact with the p-type base layer 34 and the Schottky metal layer 39.
`
`(Ex. 1001 col. 9:9-11). This improves the ohmic contact between the p-type layer
`
`34 and the metal layer 39, and correspondingly, increases the device’s avalanche
`
`
`
`12
`
`

`

`
`
`
`
`tolerance in the event a backward voltage is applied to the Schottky diode. (Id. col.
`
`3:62-4:4; col. 9:14-23). (Avalanche breakdown voltage is discussed in more detail
`
`above, supra Sec. II(B).)
`
`Finally, in combination with the foregoing advantages, the Schottky diode is
`
`formed vertically, within a trench. Likewise, the space required for the integrated
`
`Schottky diode is reduced. (Ex. 1001 col. 3:55-60 (“this metal layer locates
`
`departing from the trench in parallel with a depth direction of the trench, and
`
`therefore, a planer area occupation thereof can be eliminated as same degree as the
`
`trench.”)). Because of this, packing density can be increased. (Id. col. 3:60-62
`
`(“Consequently, in consideration with a cost, it is possible to house the schottky
`
`diode having the small area occupation on a semiconductor substrate.”); see also
`
`col. 4:46-49 (“this metal layer is provided to be adjacent to the second trench, and
`
`therefore, a planar area occupation can be made smaller.”); col. 8:21-26 (“the metal
`
`layers 29 are formed by using the regions between the trenches of the gate
`
`electrodes 27 to make this as a metal electrode side of the schottky diode, and
`
`therefore, total area as a device is seldom increased.”)).
`
`B.
`
`Prosecution History of the ‘097 Patent
`
`The Petition omits any discussion of the prosecution history for the ‘097
`
`patent even though the prosecution history directly undermines Petitioner’s
`
`proposed constructions and arguments. For instance, the prosecution history
`
`
`
`13
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`

`

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`
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`shows that Patent Owner disclaimed the proposed construction of “metal layer”
`
`that Petitioner relies upon in Ground 1. (See infra Sec. III(B)).
`
`The ‘097 patent issued from U.S. Patent Application No. 11/740,045 (“the
`
`‘045 Application”). The original ‘045 Application recited 12 claims. (Ex. 1002,
`
`pp. 128-30). On July 31, 2008, the Examiner issued an office action asserting that
`
`the pending claims were allegedly subject to restriction. (Id. pp. 61-67). The
`
`Examiner asserted that the claims were purportedly directed to two patentably
`
`distinct species, a first embodiment (FIGS. 5 and 6) and a second embodiment
`
`(FIGS. 7 and 8). (Id. p. 61).
`
`The Examiner asserted that the two embodiments are purportedly distinct
`
`because, in the first embodiment (FIGS. 5 and 6), the higher impurity
`
`concentration layer is in contact with the base layer and metal layer, which was not
`
`the case in the second embodiment (FIGS. 7 and 8). In other words, FIG. 5: higher
`
`impurity n-type layer (55c) is in contact with n-type (diffusion) base layer (55a2)
`
`and metal layer (59), and FIG. 6: higher impurity p-type layer (34b) is in contact
`
`
`2 The Examiner mistakenly identified the n-type “diffusion layer (source)” in FIG.
`
`5 as “35” rather than “55a” (see Ex. 1001 col. 10:55-56 (describing “n-type
`
`diffusion layers 55a”)).
`
`
`
`14
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`

`

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`
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`with p-type (body) base layer (34c3) and metal layer (39). (Ex. 1002 p. 63). By
`
`contrast, in the second embodiment, the conductor layer (70c) cannot be in contact
`
`with the higher impurity p-type layer (74a) because the conductor layer 70c is
`
`embedded in a trench where there is an insulating film (FIG. 7: 70a; FIG. 8: 70aa)
`
`along the sidewall, and that insulating film (70a/70aa) prevents contact between
`
`conductor layer (70c) and higher impurity p-type layer (74a). (Id.).
`
`On August 29, 2008, in response to the restriction requirement, Applicants
`
`elected embodiment 1 (FIGS. 5 and 6), which corresponded to pending claims 1-6.
`
`(Ex. 1002 p. 57).
`
`On October 20, 2008, the Examiner issued a non-final office action rejecting
`
`claims 1-3 and 5 as allegedly anticipated by U.S. Patent No. 6,433,396 to Kinzer
`
`(“Kinzer”). The Examiner also objected to claims 4 and 6 as being dependent
`
`upon a rejected base claim but otherwise allowable. (Ex. 1002 pp. 42-47).
`
`On January 8, 2009, Applicants responded to the non-final office action.
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`Applicants amended independent claim 1 to add the phrase metal layer as follows:
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`a metal layer formed departing from the trench in parallel with a depth
`direction of the trench, the metal layer penetrating the n-type diffusion
`layer and the p-type base layer to reach the n-type epitaxial layer;
`
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`3 The Examiner mistakenly identified the p-type base layer as “34” rather than
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`“34c” (see Ex. 1001 col. 11:34-35).
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`15
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`(Ex. 1002, p. 32).
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`Applicants argued that this element was not anticipated by FIG. 6 of Kinzer,
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`which is the figure from Kinzer relied upon by the Examiner. As shown in FIG. 6
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`from Kinzer (depicted below) (see Ex. 2001), Applicants explained that the
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`purported metal layer (51) identified by the Examiner (51) “does not penetrate the
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`noted n-type diffusion layer 34 and the noted p-type base layer 33 to reach the n-
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`type expitaxial layer 30.” (Ex. 1002, p. 36, emphasis in original). Applicants also
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`explained that the noted metal layer 51 in Kinzer, FIG. 6, is a layer that is
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`“deposited atop a chip or wafer and onto the region 30 . . . .” (Id., citing Ex. 2001
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`col. 2:51-53). Thus, the noted metal layer 51 “is formed above the p-type base
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`layer 33, and does not penetrate the noted n-type diffusion layer 34, to reach the
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`noted n-type epitaxial layer 30.” (Id., emphasis in original).
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`16
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`Following that response, on April 20, 2009, the Examiner issued a Notice of
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`Allowance. (Ex. 1002, p. 18). (On June 2, 2009, a Supplemental Notice of
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`Allowance issued, but only to correct an error in the original Notice of Allowance
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`that miscorrectly identified the withdrawn claims in response to the restriction
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`requirement. (Id. pp. 15-16)).
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`IV. Petitioner’s expert opinion testimony should be given no weight.
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`The Petition repeatedly relies upon the conclusory testimony of its expert
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`(Dr. Banerjee, Ex. 1002). This testimony is not substantiated whatsoever with any
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`external evidence. For instance, Petitioner’s analysis of claim 2 relies upon Dr.
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`Banerjee’s explanation of “reactive ion etching,” the “micro-loading effect,” and
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`other phenomena not purportedly discussed in the ‘097 Patent or Blanchard. (See
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`
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`17
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`Ex. 1002 ¶120). Yet, Dr. Banerjee cites to no external evidence to support his
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`opinions. (Id.). Similarly, the Petition cites to Dr. Banjaree’s explanation of the
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`‘097 patent, and Dr. Banjaree’s view that the entire structure was well-known
`
`before the priority date. (See Pet. at 12, citing Ex. 1002 ¶34). Yet, again, Dr.
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`Banerjee cites to no external evidence to support this opinion. (Id.).
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`The Trial Practice and Procedure dictates that such opinion evidence from
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`Dr. Banerjee is given no weight: “Expert testimony that does not disclose the
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`underlying facts or data on which the opinion is based is entitled to little or no
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`weight.” 37 C.F.R. § 42.65(a).
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`Thus, absent that evidence, Petitioner necessarily fails to show “a reasonable
`
`likelihood that at least one of the claims challenged in the petition is unpatentable.”
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`37 C.F.R. § 42.108(c); see also Sensus USA, Inc. v. Certified Measurement, LLC,
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`IPR2015-01439, Paper 13 at 10-11 (denying institution because expert’s
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`“testimony includes the same statements as the Petition without providing
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`additional explanation or evidentiary support for [Board] to conclude” what the
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`expert purports the prior art reference to teach); Monsanto Co. v. Pioneer Hi-Bred
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`Int’l, Inc., IPR2013-00022, Paper 43 at 6-7 (denying institution where “absent Dr.
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`Burris’ Declaration,” petitioner failed to provide evidence to support the expert’s
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`opinion that there was a reason to defoliate maize plants within the claimed 650 to
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`800 GDD timeframe).
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`18
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`V. Claim Construction
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`A.
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`Petitioner’s Proposed Constructions
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`
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`Petitioner first argues that the challenged claims should be interpreted
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`according to the plain and ordinary meaning. (Pet. at 7). Yet, Petitioner then
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`proposes what appear to be specific constructions for several terms. (See Pet. at 8-
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`11). Patent Owner challenges herein those proposed constructions by Petitioner
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`that bear directly on Patent Owner’s arguments in this Preliminary Response. For
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`those constructions proposed by Petitioner not specifically challenged herein,
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`Patent Owner does not adopt or accede to any of Petitioner’s constructions, for the
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`purpose of this proceeding or any other proceedings, either before the Patent Office
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`or a District Court, and reserves all rights with respect to challenging Petitioner’s
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`proposed constructions, or any other proposed constructions, in the future.
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`B.
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`“metal layer departing from the trench in parallel with a depth
`direction of the trench”
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`
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`Petitioner proposes that this term should be construed to mean, “a
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`conductive layer comprising metal and having a portion extending into the
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`semiconductor body in substantially the same direction as the trench.” (Pet. at 10).
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`Petitioner’s construction is a very broad construction of the claimed “metal layer.”
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`Petitioner’s broad construction is necessary for its arguments to work in Ground 1,
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`based on Blanchard. Specifically, Petitioner attempts to include the horizontal
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`19
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`“source electrode” as part of the vertical “metal layer.” Yet, this construction is
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`inconsistent with the intrinsic evidence.
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`Rather, the “metal layer” is limited to the “trench” portion that is vertical
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`and parallel to the gate electrode trench 27. The “metal layer” does not include the
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`horizontal conducting layers above the semiconductor layers, which is otherwise
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`identified in the ‘097 patent as the “source electrode” or “source electrode layer.”
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`This is supported by: (i) the claim language; (ii) the specification; and (iii) the
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`prosecution history.
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`
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`First, the claim language supports Patent Owner’s construction.
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`Independent claim 1 recites that the “metal layer” is formed in the region
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`“departing from the trench in parallel with the depth direction of the trench.”
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`Thus, the claim explicitly describes the metal layer as including vertical portions,
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`i.e., “in parallel with the depth directions of the trench.” The claim specifically
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`says that “metal layer” is “formed” from these vertical portions, i.e., not including
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`otherwise horizontal portions that would not be “in parallel with the depth
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`direction of the trench.” Further, the patent expressly defines the “trench” as
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`extending in the vertical direction—“[t]he trench has a shape extending in the
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`vertical direction to the paper in the drawing.” (Ex. 1001 col. 7:50-51).
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`
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`In addition, the claim defines the “metal layer” to satisfy the following
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`requirement: “the metal layer penetrating the n-type diffusion layer and the p-type
`
`
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`20
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`base layer to reach the n-type epitaxial layer”. Any purported horizontal portion of
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`the “metal layer” would not penetrate the respective semiconductor layers and
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`“reach” the n-type epitaxial layer, and would not thus not satisfy the explicit
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`definition of the “metal layer” recited in the claim. (This conclusion is supported
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`by the prosecution history, discussed infra.)
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`
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`The claim language of the dependent claims also undermines Petitioner’s
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`construction. Claim 2 recites that the “metal layer is shallower than a depth of the
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`trench.” By referring to the “depth” of the “metal layer,” this bolsters the
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`construction that the “metal layer” is only vertical