Paper 27
`Trials@uspto.gov
`571-272-7822 Entered: January 6, 2020
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`APPLE INC.,
`Petitioner,
`v.
`QUALCOMM INCORPORATED,
`Patent Owner.
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`IPR2018-01249
`Patent 7,693,002 B2
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`Before TREVOR M. JEFFERSON, DANIEL J. GALLIGAN, and
`SCOTT B. HOWARD, Administrative Patent Judges.
`GALLIGAN, Administrative Patent Judge.
`
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`
`JUDGMENT
`Final Written Decision
`Determining All Challenged Claims Unpatentable
`Granting Petitioner’s Motion to Exclude
`35 U.S.C. § 318(a)
`
`
`
`
`Trials@uspto.gov
`571-272-7822 Entered: January 6, 2020
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`APPLE INC.,
`Petitioner,
`v.
`QUALCOMM INCORPORATED,
`Patent Owner.
`
`IPR2018-01249
`Patent 7,693,002 B2
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`
`
`Before TREVOR M. JEFFERSON, DANIEL J. GALLIGAN, and
`SCOTT B. HOWARD, Administrative Patent Judges.
`GALLIGAN, Administrative Patent Judge.
`
`
`
`
`
`JUDGMENT
`Final Written Decision
`Determining All Challenged Claims Unpatentable
`Granting Petitioner’s Motion to Exclude
`35 U.S.C. § 318(a)
`
`
`
`
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`Patent 7,693,002 B2
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`I. INTRODUCTION
`In this inter partes review, Apple Inc. (“Petitioner”) challenges the
`patentability of claims 1–28 and 31–37 of U.S. Patent No. 7,693,002 B2
`(“the ’002 patent,” Ex. 1001), which is assigned to Qualcomm Incorporated
`(“Patent Owner”).
`We have jurisdiction under 35 U.S.C. § 6. This Final Written
`Decision, issued pursuant to 35 U.S.C. § 318(a), addresses issues and
`arguments raised during the trial in this inter partes review. For the reasons
`discussed below, we determine that Petitioner has proven by a
`preponderance of the evidence that claims 1–28 and 31–37 of the ’002
`patent are unpatentable. See 35 U.S.C. § 316(e) (“In an inter partes review
`instituted under this chapter, the petitioner shall have the burden of proving a
`proposition of unpatentability by a preponderance of the evidence.”).
`A. Procedural History
`On June 18, 2018, Petitioner requested inter partes review of claims
`1–28 and 31–37 of the ’002 patent on the following grounds:
`35 U.S.C. §1
`Claims Challenged
`Reference(s)
`1–28, 31–37
`103(a)
`1–17, 20–28, 31–36
`103(a)
`
`Sato2
`Asano,3 Itoh4
`
`
`1 The Leahy-Smith America Invents Act (“AIA”) included revisions to
`35 U.S.C. §§ 103 and 112 that became effective after the filing of the
`application for the ’002 patent. Therefore, we apply the pre-AIA versions of
`these sections.
`2 US 4,951,259, issued Aug. 21, 1990 (Ex. 1005).
`3 US 2006/0098520 A1, published May 11, 2006 (Ex. 1006).
`4 Kiyoo Itoh, VLSI Memory Chip Design, (2001) (Ex. 1007).
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`Paper 2 (“Pet.”). Patent Owner did not file a Preliminary Response. We
`instituted trial on all grounds of unpatentability. Paper 6 (“Dec. on Inst.”),
`18.
`
`During the trial, Patent Owner filed a Response (Paper 11, “PO
`Resp.”), Petitioner filed a Reply (Paper 15, “Pet. Reply”), and Patent Owner
`filed a Sur-reply (Paper 17, “PO Sur-reply”).
`Petitioner filed a Motion to Exclude Exhibit 2004 (Paper 19), to which
`Patent Owner filed an Opposition (Paper 21), and in support of which
`Petitioner filed a Reply (Paper 23).
`An oral hearing was held on October 10, 2019, a transcript of which
`appears in the record. Paper 26 (“Tr.”).
`B. The ’002 Patent and Illustrative Claim
`The ’002 patent generally relates to wordline drivers and decoders for
`memory arrays. Ex. 1001, code (57), 1:7–9. Figure 1 of the ’002 patent is
`reproduced below.
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`Figure 1 is a block diagram of an embodiment of a wordline driver
`system 100. Ex. 1001, 2:31–34. Figure 1 shows groups of wordline drivers
`104 and 106 that control particular wordlines in memory array 102. Id. at
`2:53–3:8. Group of wordline drivers 104 drives wordlines WL<0> through
`WL<3>, and group of wordline drivers 106 drives wordlines WL<60>
`through WL<63>. Id. Additional wordline drivers that are not shown
`control the wordlines between WL<3> and WL<60>. Id. at 3:4–8.
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`In operation, two-to-four bit decoder 112 decodes the first portion
`(such as bits 0 and 1) of a six-bit memory address, and four-to-sixteen bit
`decoder decodes the remaining portion of the address (bits 2 through 5).
`Ex. 1001, 3:9–25. Based on the decoded first portion of the address received
`from decoder 112, conditional clock generator 110 “selectively applies the
`clock signal to a selected one of the clock outputs 124, 126, 128 and 130,”
`each of which is coupled to a particular wordline driver in each group of
`wordline drivers. Id. at 3:26–34. “The four-to-sixteen bit memory address
`decoder 108 decodes the remainder of the six-bit memory address (e.g. bits
`two to five) and applies a partial address input to the wordlines that are
`related to the decoded memory address.” Id. at 3:37–40. For example, if the
`partially-decoded address indicates that the first group of wordlines is
`addressed (WL<0> through WL<3>), decoder 108 applies a signal to
`address line 120, which, as shown in Figure 1, connects to group of wordline
`drivers 104. Ex. 1001, 3:41–67. The ’002 patent explains that “the decoded
`output of the two-to-four decoder 112 with clock generator 110 and the
`decoded output of the four-to-sixteen bit memory address decoder 108 may
`be utilized via a logical AND operation to selectively activate a wordline
`driver of the group of wordline drivers 104.” Id. at 4:3–8.
`Of the challenged claims, claims 1, 7, 11, 17, 21, and 23–27 are
`independent. Claim 1, reproduced below, is illustrative.
`1.
`A circuit device comprising:
`first logic to receive a clock signal and a first portion of a
`memory address of a memory array, the first logic to decode the
`first portion of the memory address and to apply the clock signal
`to a selected clock output of a plurality of clock outputs
`associated with a selected group of a plurality of wordline drivers
`that are associated with the memory array; and
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`second logic to decode a second portion of the memory
`address, the second logic to selectively activate a particular
`wordline driver of the selected group of wordline drivers
`according to the second portion of the memory address.
`
`II. ANALYSIS
`A. Level of Ordinary Skill in the Art
`Relying on the testimony of Dr. Robert Horst, Petitioner offers the
`following assessment as to the level of ordinary skill in the art:
`A person of ordinary skill in the art (“POSITA”) as of October
`10, 2006 would have had at least an undergraduate degree in
`electrical engineering, or a related field, and three years of
`experience in the design of memory systems and circuits.
`Alternatively, a person of ordinary skill with less than the amount
`of experience noted above would have had a correspondingly
`greater amount of educational training such a graduate degree in
`a related field.
`Pet. 2 (citing Ex. 1003 ¶¶ 27–29). In the Institution Decision, we stated that,
`“[t]o the extent necessary, and for purposes of this Decision, we accept the
`assessment offered by Petitioner, with the exception of the language ‘at
`least,’ because this assessment is consistent with the ’002 patent, the asserted
`prior art, and the evidence of record.” Dec. on Inst. 6 (citing Ex. 1003 ¶ 27).
`In its Response, Patent Owner states that it “accepts Petitioner’s proposed
`education and experience level of one of ordinary skill in the art, as modified
`by the Board’s institution decision.” PO Resp. 15 (citing Pet. 2; Dec. on
`Inst. 6).
`Based on the evidence of record, we determine, consistent with our
`assessment in the Institution Decision, that the skill level of a person of
`ordinary skill in the art would have been that of a person with an
`undergraduate degree in electrical engineering, or a related field, and three
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`years of experience in the design of memory systems and circuits.
`Alternatively, a person of ordinary skill with less than the amount of
`experience noted above would have had a correspondingly greater amount of
`educational training such as a graduate degree in a related field. See
`Ex. 1003 ¶ 27; see also Ex. 2001 (Patent Owner’s declarant Dr. Pedram
`testifying that he “do[es] not dispute Petitioner’s proposed level of ordinary
`skill in the art as modified by the Board”).
`B. Claim Interpretation
`In an inter partes review for a petition filed before November 13,
`2018, a claim in an unexpired patent shall be given its broadest reasonable
`construction in light of the Specification of the patent in which it appears.
`37 C.F.R. § 42.100(b) (2018); see Changes to the Claim Construction
`Standard for Interpreting Claims in Trial Proceedings Before the Patent Trial
`and Appeal Board, 83 Fed. Reg. 51,340 (Oct. 11, 2018) (amending
`37 C.F.R. § 42.100(b) effective November 13, 2018) (now codified at
`37 C.F.R. § 42.100(b) (2019)). The Petition was accorded a filing date of
`June 18, 2018, and, therefore, the broadest reasonable interpretation standard
`for claim interpretation applies. See Paper 5 (Notice of Filing Date
`Accorded to Petition).
`In applying a broadest reasonable interpretation, claim terms generally
`are given their ordinary and customary meaning, as would be understood by
`one of ordinary skill in the art in the context of the entire disclosure. See In
`re Translogic Tech., Inc., 504 F.3d 1249, 1257 (Fed. Cir. 2007). This
`presumption may be rebutted when a patentee, acting as a lexicographer, sets
`forth an alternate definition of a term in the specification with reasonable
`clarity, deliberateness, and precision. In re Paulsen, 30 F.3d 1475, 1480
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`(Fed. Cir. 1994). Furthermore, only terms that are in controversy need to be
`construed, and only to the extent necessary to resolve the controversy. See
`Nidec Motor Corp. v. Zhongshan Broad Ocean Motor Co., 868 F.3d 1013,
`1017 (Fed. Cir. 2017) (citing Vivid Techs., Inc. v. Am. Sci. & Eng’g, Inc.,
`200 F.3d 795, 803 (Fed. Cir. 1999)).
`1. Clock Signal
`Patent Owner argues that the term “clock signal” should be construed
`as “a periodic signal used for synchronization” and that, under this
`interpretation, Petitioner’s obviousness challenge based on Sato fails
`because Sato does not teach such a signal. PO Resp. 11–15, 30–45.
`Patent Owner relies on the absence of disclosure in the ’002 patent to
`show that its construction is proper rather than on intrinsic evidence that
`affirmatively supports its construction. For example, Patent Owner argues
`that “[t]he ’002 patent does not describe an asynchronous memory system
`that uses multiple, non-periodic timing signals.” PO Resp. 12 (citing
`Ex. 2001 ¶ 54). This is true insofar as the ’002 patent is completely silent on
`the issue. Notably absent from the Specification of the ’002 patent is any
`mention of the clock signal as “periodic” or used for “synchronization.” The
`words “period,” “frequency,” and “synchronous,” and derivatives therefrom,
`appear nowhere in the Specification of the ’002 patent. In its Response,
`Patent Owner does not cite a single passage of the ’002 patent to support its
`proposed construction. See PO Resp. 11–15. In its Sur-reply, Patent Owner
`argues the following:
`[T]he invention of the ’002 patent is specifically intended to
`address problems that arise from the use of a periodic clock
`signal. Such a clock signal periodically switches between logic-
`level high and low states, thus resulting in high power
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`consumption, and because the periodic clock signal is distributed
`to many different components of the memory system to
`synchronize them, a heavy load is placed on the clock signal. See
`Ex. 1001 at 1:11-25. The invention of the ’002 patent is intended
`to address the problems of power consumption and loading that
`result from the use of a periodic, synchronizing clock signal. See
`id.
`PO Sur-reply 3–4. The cited passage is from the “Description of Related
`Art” section in the “BACKGROUND” of the ’002 patent and does not
`mention periodicity or synchronization. Ex. 1001, 1:11–25.
`Patent Owner’s declarant Dr. Pedram similarly focuses on the absence
`of disclosure in the ’002 patent as supporting the limiting construction
`advocated by Patent Owner. See Ex. 2001 ¶¶ 53–70. Much of this
`testimony is a description of the operation of asynchronous memories and an
`explanation that the ’002 patent does not disclose various components
`allegedly necessary for an asynchronous memory. See Ex. 2001 ¶¶ 55–60,
`65–66. The few passages of the ’002 patent cited by Dr. Pedram mention a
`“clock” or “clock signal” but do not support the construction proposed by
`Patent Owner. Ex. 1001, 1:11–16, 1:64–66, 2:2–12. Thus, we are not
`persuaded that the intrinsic record’s lack of disclosure supports Patent
`Owner’s proposed interpretation.
`Because the ’002 patent is silent on the nature of its “clock signal,”
`Patent Owner relies on the IEEE Dictionary’s definition of “clock signal” as
`“[a] periodic signal used for synchronizing events.” PO Resp. 12 (citing
`Ex. 2002, 9). As Petitioner notes, however, the IEEE Dictionary states that
`“clock pulse” and “timing pulse” are synonyms for “clock signal.” Pet.
`Reply 6–7 (citing Ex. 2002, 9). This is significant because of the parties’
`dispute over whether Sato’s disclosure of a “timing signal” teaches a “clock
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`signal.” The IEEE Dictionary at least suggests an equivalence between the
`two terms.
`Whether or not the IEEE Dictionary supports Patent Owner’s
`proposed definition of “clock signal,” we determine that it is not necessary
`to construe the term “clock signal” in light of Sato’s disclosure. In
`particular, Sato discloses that “[t]he present invention can be applied widely
`to semiconductor memory devices having at least a clocked static type
`address decoder and semiconductor devices with built-in semiconductor
`memory devices of the type described above.” Ex. 1005, 12:4–8 (emphasis
`added). Sato also states that “[t]his invention relates to semiconductor
`memory devices and to a technique which will be effective when applied, for
`example, to CMOS (Complementary MOS) static RAMs (Random Access
`Memories)” and further that “CMOS static RAMs including clocked static
`decoders are known in the art.” Ex. 1005, 1:6–11 (emphasis added). Thus,
`as explained further below, Patent Owner’s attempt to narrow the recited
`“clock signal” to data having certain characteristics so as to avoid Sato’s
`disclosure of a “timing signal” that is allegedly asynchronous fails to
`differentiate over Sato in any event.
`Thus, we determine that it is not necessary to construe the term “clock
`signal.”
`
`2. Means-Plus-Function Limitations
`In accordance with 37 C.F.R. § 42.104(b)(3), Petitioner proposes
`constructions for the following limitations it contends are means-plus-
`function limitations subject to 35 U.S.C. § 112, ¶ 6: “means for decoding a
`first portion of a memory address of a memory array” in claim 11; “means
`for selectively providing a clock signal to a selected group of wordline
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`drivers based on the first portion of the memory address [of a memory
`array]”5 in claims 11, 27; “means for decoding a second portion of the
`memory address” in claims 11, 14; “means for activating a particular
`wordline driver of the selected group of wordline drivers according to the
`second portion of the memory address” in claims 11, 27; and “means for
`applying the second portion of the memory address to a shared address line”
`in claim 14. Pet. 5–7.
`Patent Owner does not offer its own constructions for any of these
`limitations, nor does it address Petitioner’s proposed constructions. See PO
`Resp. 11–15 (discussing claim construction).
`Each of the limitations reproduced above recites “means” and further
`recites a function, thus creating a presumption that 35 U.S.C. § 112, ¶ 6
`applies. See 35 U.S.C. § 112, ¶ 6 (“An element in a claim for a combination
`may be expressed as a means or step for performing a specified function
`without the recital of structure, material, or acts in support thereof, and such
`claim shall be construed to cover the corresponding structure, material, or
`acts described in the specification and equivalents thereof.”); Williamson v.
`Citrix Online, LLC, 792 F.3d 1339, 1349 (Fed. Cir. 2015) (en banc in
`relevant part) (holding that “use of the word ‘means’ creates a presumption
`that § 112, ¶ 6 applies” (quoting Personalized Media Commc’ns, LLC v.
`Int’l Trade Comm’n, 161 F.3d 696, 703 (Fed. Cir. 1998))).
`We agree with Petitioner that these limitations are means-plus-
`function limitations subject to 35 U.S.C. § 112, ¶ 6. We have reviewed the
`portions of the Specification of the ’002 patent cited by Petitioner, and we
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`5 Claim 27 includes “of a memory array.”
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`adopt Petitioner’s proposals for the structure corresponding to the recited
`functions. See Pet. 5–7.
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`C. Principles of Law
`A patent claim is unpatentable under 35 U.S.C. § 103(a) if the
`differences between the claimed subject matter and the prior art are such that
`the subject matter, as a whole, would have been obvious at the time the
`invention was made to a person having ordinary skill in the art to which said
`subject matter pertains. KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 406
`(2007). The question of obviousness is resolved on the basis of underlying
`factual determinations including (1) the scope and content of the prior art;
`(2) any differences between the claimed subject matter and the prior art;
`(3) the level of ordinary skill in the art; and (4) any secondary
`considerations, if in evidence. Graham v. John Deere Co., 383 U.S. 1, 17–
`18 (1966).
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`D. Obviousness over Sato
`(Claims 1–28, 31–37)
`Petitioner contends claims 1–28 and 31–37 of the ’002 patent are
`unpatentable under 35 U.S.C. § 103(a) as obvious over the teachings of Sato.
`Pet. 2, 9–32, 51–52, 54, 55, 58–60, 63–81.
`1. Sato
`Like the ’002 patent, Sato is directed to wordline drivers for memory.
`Ex. 1005, codes (54), (57). Figure 3 of Sato is reproduced below.
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`Figure 3 is a diagram of an address decoder in one embodiment. Ex. 1005,
`2:57–59. Sato explains that pre-decoder PDCR receives and decodes the
`lower 2-bit complementary address signals ax0 and ax1. Ex. 1005, 5:16–28.
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`Furthermore, “timing signal 𝜙𝜙ce described above is supplied to the pre-
`decoder PDCR and its output signal, that is, the selection signal 𝜙𝜙x0 ~ 𝜙𝜙x3,
`is generated in accordance with this timing signal 𝜙𝜙ce.” Ex. 1005, 10:36–
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`39. Decoding NAND gate circuits, of which only one, NAG0, is shown in
`Figure 3, are used to decode the remaining address bits to select the
`appropriate wordline drive circuit. Ex. 1005, 5:43–6:59.
`2. Alleged Deficiency of Sato Ground
`Patent Owner argues that Petitioner has not set forth a prima facie
`case of obviousness because it has not identified any differences between the
`claimed subject matter and the prior art and, thus, has not complied with
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`Graham. PO Resp. 28–30. We disagree. In Graham, the Supreme Court
`stated the following:
`Under § 103, the scope and content of the prior art are to be
`determined; differences between the prior art and the claims at
`issue are to be ascertained; and the level of ordinary skill in the
`pertinent art resolved. Against this background, the obviousness
`or nonobviousness of the subject matter is determined. Such
`secondary considerations as commercial success, long felt but
`unsolved needs, failure of others, etc., might be utilized to give
`light to the circumstances surrounding the origin of the subject
`matter sought to be patented. As indicia of obviousness or
`nonobviousness, these inquiries may have relevancy.
`383 U.S. at 17–18 (emphasis added).
`
`renders obvious a clock signal” and explains why a person of ordinary skill
`
`Petitioner asserts that Sato’s “[t]iming signal 𝜙𝜙ce represents or
`in the art would have “viewed the function of the timing signal 𝜙𝜙ce as
`how Sato’s disclosures relating to its timing signal 𝜙𝜙ce teach the recited
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`similar to or equivalent to that of a clock signal.” Pet. 14–17 (quoting
`Ex. 1003 ¶ 64). Petitioner presents over two pages of argument explaining
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`subject matter pertaining to the “clock signal.” See Pet. 14–17. The trial
`record shows that the wording difference between Sato (“timing signal”) and
`the ’002 patent (“clock signal”) is the pivotal issue raised by Patent Owner
`in its challenge to the Sato ground. See PO Resp. 30–45. Thus, Petitioner’s
`explanation addressing this difference in terminology between the prior art
`and the claims shows that its analysis follows Graham.
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`3. Claim 1
`a) First logic
`Petitioner’s contentions
`i.
`Independent claim 1 is reproduced above and is directed to “[a] circuit
`device” having
`first logic to receive a clock signal and a first portion of a memory
`address of a memory array, the first logic to decode the first
`portion of the memory address and to apply the clock signal to a
`selected clock output of a plurality of clock outputs associated
`with a selected group of a plurality of wordline drivers that are
`associated with the memory array.
`With its obviousness contentions, Petitioner provides the following
`annotated version of Sato’s Figure 3:
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`Pet. 10. In the annotated version of Sato’s Figure 3, Petitioner identifies
`with color annotations particular components that it contends teach various
`limitations recited in claim 1. Pet. 10.
`Petitioner contends Sato’s disclosure of pre-decoder PDCR receiving
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`timing signal 𝜙𝜙ce and address signals ax0 and ax1, along with their
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`complements, teaches “first logic to receive a clock signal and a first portion
`of a memory address of a memory array,” as recited in claim 1. Pet. 14
`(citing Ex. 1005, 3:9–15, 3:50–59, 4:6–11, 5:16–24, 9:44–54, Fig. 3).
`Petitioner contends (Pet. 18) Sato teaches “the first logic to decode the first
`portion of the memory address” because Sato discloses that “pre-decoder
`PDCR decodes the lower 2-bit complementary internal address signals ax0
`and ax1” (Ex. 1005, 5:25–26). Petitioner also contends Sato teaches the first
`logic “to apply the clock signal to a selected clock output of a plurality of
`clock outputs associated with a selected group of a plurality of wordline
`drivers that are associated with the memory array” through its disclosure of
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`PDCR generating selection signals 𝜙𝜙x0 through 𝜙𝜙x3 based on input timing
`signal 𝜙𝜙ce. Pet. 18–23 (citing, inter alia, Ex. 1005, 5:25–31, 6:40–55, 9:30–
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`51, 9:52–65, 10:36–39, claim 1, Fig. 3).
`Patent Owner’s arguments and our analysis
`ii.
`Patent Owner argues Sato does not teach the recited “clock signal”
`because Sato’s timing signal is not “a periodic signal used for
`synchronization,” as Patent Owner proposes to construe the term. PO
`Resp. 30–44. According to Patent Owner, Sato discloses an asynchronous
`system whereas the ’002 patent discloses a synchronous system. Patent
`Owner acknowledges that “Sato does not expressly refer to its memory
`system as being asynchronous” but argues that a person of ordinary skill in
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`the art “would understand it as such because it is an exact match of the
`asynchronous systems” Patent Owner describes in its Response. PO
`Resp. 34 (citing Ex. 2001 ¶ 102). Patent Owner argues that “Sato does not
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`suggest that any of the signals 𝜙𝜙ce, 𝜙𝜙we, 𝜙𝜙sa, and 𝜙𝜙oe are periodic, which
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`is consistent with asynchronous systems’ use of multiple, non-periodic
`internal timing signals.” PO Resp. 34 (citing Ex. 2001 ¶ 103).
`Although Sato may not say that its timing signal is periodic, the ’002
`patent does not say that the recited “clock signal” is periodic. Rather, Patent
`Owner attempts to take advantage of the lack of disclosure in its own
`Specification to support an alleged distinction over the prior art based on a
`difference in terminology – “timing signal” as opposed to “clock signal.”
`Regardless of the differences in terminology, Patent Owner’s
`attempted distinction over Sato fails because Sato discloses that its circuit
`operates with a clock signal as well. In particular, as Petitioner points out
`(Pet. 15), Sato discloses that “[t]he present invention can be applied widely
`to semiconductor memory devices having at least a clocked static type
`address decoder and semiconductor devices with built-in semiconductor
`memory devices of the type described above.” Ex. 1005, 12:4–8 (emphasis
`added); see also Pet. 15 (quoting Ex. 1005, 12:4–6). Sato also states that
`“[t]his invention relates to semiconductor memory devices and to a
`technique which will be effective when applied, for example, to CMOS
`(Complementary MOS) static RAMs (Random Access Memories)” and
`further that “CMOS static RAMs including clocked static decoders are
`known in the art.” Ex. 1005, 1:6–11 (emphasis added); see also Pet. 15
`(quoting Ex. 1005, 1:10–11).
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`Patent Owner responds to Sato’s disclosure of “clocked” circuits as
`follows:
`The portion of Sato cited by Petitioner merely provides Sato’s
`unexplained, unsupported opinion that his invention can be
`applied to devices having a clocked static type address decoder
`in the same way that Sato opines that his invention can also be
`applied to dynamic RAMs and other semiconductor memory
`devices.
`PO Resp. 43 (citing Ex. 2001 ¶ 118; Ex. 1005, 11:66–12:3). We disagree
`with Patent Owner. The cited portion of Sato not “unsupported opinion.” It
`is the express disclosure of the prior art, and it moots Patent Owner’s
`argument, which is based entirely on the difference in terminology between
`“clock signal” and “timing signal.” As discussed above, nowhere does the
`’002 patent describe the nature of its clock signal. Thus, Patent Owner’s
`argument depends solely on the use of the term “clock signal.” Sato’s
`disclosure of “a clocked static type address decoder” refutes Patent Owner’s
`attempted semantic distinction. Ex. 1005, 12:4–8.
`Patent Owner further argues that “Sato’s vague statement about
`potential uses for its invention does not transform the reference’s non-
`
`periodic timing signal 𝜙𝜙ce into a periodic clock signal.” PO Resp. 43–44.
`
`As noted above, however, the ’002 patent never says that its “clock signal”
`is periodic. Rather, Patent Owner bases its argument on extrinsic
`evidence—the IEEE Dictionary—to which Patent Owner resorts based on
`the word “clock signal” and the lack of disclosure in the ’002 patent of the
`nature of that signal. See PO Resp. 11–15. Sato’s disclosure of “a clocked
`static type address decoder” demonstrates that Sato teaches a circuit having
`logic “to receive a clock signal.” Whether or not the received clock signal is
`periodic does not negate Sato’s teaching of logic to receive a clock signal.
`
`
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`Patent Owner also argues that Sato does not teach the “clock output”
`of the claims. PO Resp. 45–47. In particular, Patent Owner argues that “the
`predecoder PDCR is a black box—Sato provides no disclosure on its internal
`
`circuitry” and that, “even if the input signal 𝜙𝜙ce to the predecoder PDCR is
`
`considered a clock signal, the outputs of the predecoder PDCR are not
`necessarily clock signals.” PO Resp. 47 (citing Ex. 2001 ¶ 76). The
`evidence, however, shows that Sato’s predecoder is not a black box.
`Referring to the predecoder of Figure 1, which does not receive timing
`
`lower 2-bit
`the
`The pre-decoder PDCR decodes
`complementary internal address signals ax0 and axl supplied
`thereto from the X address buffer XADB and generates selection
`
`signal 𝜙𝜙ce as an input, Sato discloses the following:
`signals 𝜙𝜙x0 ~ 𝜙𝜙x3. These selection signals 𝜙𝜙x0 ~ 𝜙𝜙x3 are
`selection signal 𝜙𝜙x0 is set to the high logic level when both the
`logic level. Similarly, the selection signals 𝜙𝜙x1, 𝜙𝜙x2 and 𝜙𝜙x3
`
`formed selectively in accordance with the complementary
`internal address signals ax0 and ax1. In other words, the
`
`inversed internal address signals ax0 and ax1 are at the high
`
`are set to the high logic level when both the non-inversed internal
`address signal ax0 and the inversed internal address signal ax1
`are at the high logic level, when both the inversed internal
`address signal ax0 and non-inversed internal address signal ax1
`are at the high logic level and when both the non-inversed
`internal address signals ax0 and ax1 are at the high logic level,
`respectively.
`Ex. 1005, 5:25–42. For the predecoder of Figure 3, upon which Petitioner
`relies in its contentions of obviousness, Sato discloses that “[t]he timing
`
`signal 𝜙𝜙ce described above is supplied to the pre-decoder PDCR and its
`output signal, that is, the selection signal 𝜙𝜙x0 ~ 𝜙𝜙x3, is generated in
`accordance with this timing signal 𝜙𝜙ce.” Ex. 1005, 10:36–39. Thus, Sato
`
`
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`explains how the predecoder works without timing signal 𝜙𝜙ce and
`additionally with timing signal 𝜙𝜙ce.
`
`Patent Owner does not dispute that Sato’s description of predecoder
`PDCR in column 5, lines 25–42 applies to the predecoder of Figure 3 as
`well. Indeed, Patent Owner’s declarant, Dr. Pedram, relies on this disclosure
`to explain the operation of predecoder PDCR of Figure 3. Ex. 2001
`¶¶ 75–76. Dr. Horst, Petitioner’s declarant, testifies that “Sato does not
`provide a diagram the internals of XDCR in Fig. 3, but the text description
`above [(Ex. 1005, 5:25–42, 9:44–59)] provides enough detail for a [person
`of ordinary skill in the art] to understand that it performs a function
`equivalent to four AND gates.” Ex. 1003 ¶ 62. Dr. Horst provides the
`following figure:
`
`
`
`Ex. 1003 ¶ 62. The figure reproduced above is captioned “Illustration of the
`internal structure of the PDCR decoder in Sato Fig. 3.” Ex. 1003 ¶ 62. In
`support of his testimony, Dr. Horst cites a textbook titled Fundamentals of
`Digital Logic with Verilog Design (Ex. 1009) that shows how a truth table
`for a decoder is implemented using AND gates and inverters. Ex. 1003 ¶ 63
`(citing Ex. 1009, 312 (Fig. 6.16), 315).
`
`
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`In its Sur-reply, Patent Owner again asserts that “Sato’s predecoder
`PDCR is a black box” and argues “that Petitioner’s arguments about what
`the [person of ordinary skill in the art] ‘would understand’ are based purely
`on speculation.” PO Sur-reply 20 (citing PO Resp. 45–47). We disagree.
`Dr. Horst’s testimony as to how a person of ordinary skill in the art would
`have understood Sato’s predecoder PDCR in Figure 3 is not based on
`speculation. Rather, it is based on a detailed explanation, and we credit this
`explanation. See Ex. 1003 ¶¶ 60–63. Sato’s disclosure at column 5,
`
`above is supplied to the pre-decoder PDCR and its output signal, that is, the
`
`lines 25–42 lists the address inputs that will result in each of 𝜙𝜙x0, 𝜙𝜙x1, 𝜙𝜙x2,
`and 𝜙𝜙x3 being at a high logic level, thus providing, in its written description,
`a truth table. Sato then discloses that “[t]he timing signal 𝜙𝜙ce described
`selection signal 𝜙𝜙x0 ~ 𝜙𝜙x3, is generated in accordance with this timing
`signal 𝜙𝜙ce.” Ex. 1005, 10:36–39. Dr. Horst explains that this means that
`“the value of timing signal 𝜙𝜙ce is passed through to the selected output.”
`
`Ex. 1003 ¶ 63. Based on Sato’s disclosure and Dr. Horst’s detailed
`explanation, we find that a person of ordinary skill in the art—a person with
`an undergraduate degree in electrical engineering, or a related field, and
`three years of experience in the design of memory systems and circuits—
`would have readily recognized how Sato’s predecoder operates based on
`Sato’s detailed description.
`iii. Our findings as to “first logic”
`We are persuaded by Petitioner’s contentions that Sato teaches the
`“first logic” recited in claim 1. See Pet. 14–23. In particular, we find Sato
`teaches “first logic to receive a clock signal and a first portion of a memory
`address of a memory array” because it discloses, with reference to Figure 3,
`
`
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`and ax1, along with their complements, as inputs. Ex. 1005, Fig. 3; see
`Ex. 1005, 5:16–24 (disclosing that PDCR “receives the lower 2-bit
`complementary internal address signals ax0 and ax1”), 10:36–39 (disclosing
`
`that predecoder PDCR re
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