(12) United States Patent
`Weeks et al.
`
`111111
`
`1111111111111111111111111111111111111111111111111111111111111
`US006611002B2
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 6,611,002 B2
`Aug. 26, 2003
`
`(54) GALLIUM NITRIDE MATERIAL DEVICES
`AND METHODS INCLUDING BACKSIDE
`VIAS
`
`(75)
`
`Inventors: T. Warren Weeks, Raleigh, NC (US);
`Edwin L. Piner, Cary, NC (US);
`Ricardo M. Borges, Morrisville, NC
`(US); Kevin J. Linthicum, Angier, NC
`(US)
`
`(73) Assignee: Nitronex Corporation, Raleigh, NC
`(US)
`
`( *) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`(21) Appl. No.: 09/792,414
`
`(22) Filed:
`
`Feb.23,2001
`
`( 65)
`
`Prior Publication Data
`
`US 2002/0117681 A1 Aug. 29, 2002
`
`Int. Cl? ................................................ HOlL 33/00
`(51)
`(52) U.S. Cl. ........................... 257/94; 257/96; 257/101;
`257/103; 257/190; 257/191; 257/462; 438/173;
`438/172; 438/778; 438/779
`(58) Field of Search ............................ 257/94, 96, 103,
`257/101, 190, 191, 192, 194, 462, 347;
`438/173, 172, 778, 779
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`4,985,742 A * 1!1991 Pankove ...................... 357/34
`3/1993 Khan et a!.
`5,192,987 A
`
`FOREIGN PATENT DOCUMENTS
`
`2/2000
`10/1996
`7/1998
`10/1999
`11/2001
`12/1997
`5/1998
`9/1998
`6/2000
`5/2001
`6/2001
`6/2001
`8/2001
`
`199 31 300 A1
`0 740 376 A1
`0 852 416 A1
`0 951 055 A2
`2 809 534 A
`09326534 A
`10135519 A *
`10242584 A
`W000/33365 A1
`WOOl/37327 A1
`WOOl/43174 A2
`WOOl/47002 A2
`WOOl/59819 A1
`
`DE
`EP
`EP
`EP
`FR
`JP
`JP
`JP
`wo
`wo
`wo
`wo
`wo
`Primary Examiner-Nathan 1. Flynn
`Assistant Examiner---Remmon R. Forde
`(74) Attorney, Agent, or Firm-Wolf, Greenfield & Sacks,
`P.C.
`
`(57)
`
`ABSTRACT
`
`The invention includes providing gallium nitride material
`devices having backside vias and methods to form the
`devices. The devices include a gallium nitride material
`formed over a substrate, such as silicon. The device also may
`include one or more non-conducting layers between the
`substrate and the gallium nitride material which can aid in
`the deposition of the gallium nitride material. A via is
`provided which extends from the backside of the device
`through the non-conducting layer(s) to enable electrical
`conduction between an electrical contact deposited within
`the via and, for example, an electrical contact on the topside
`of the device. Thus, devices of the invention may be
`vertically conducting. Exemplary devices include laser
`diodes (LDs), light emitting diodes (LEDs), power rectifier
`diodes, FETs (e.g., HFETs), Gunn-effect diodes, and varac(cid:173)
`tor diodes, among others.
`
`(List continued on next page.)
`
`51 Claims, 8 Drawing Sheets
`
`18~
`
`16
`
`22~
`
`EVERLIGHT ELECTRONICS CO., LTD.
`Exhibit 1007
`
`

`

`US 6,611,002 B2
`Page 2
`
`U.S. PATENT DOCUMENTS
`
`3/1994 Khan eta!.
`5,296,395 A
`2/1995 Takeuchi et a!.
`5,389,571 A
`2/1995 Edmond eta!.
`5,393,993 A
`8/1995 Okaniwa
`5,438,212 A
`6/1996 Edmond eta!.
`5,523,589 A
`4/1998 Edmond eta!.
`5,739,554 A
`6/1998 Marx eta!.
`5,760,426 A
`11/1998 Edmond eta!.
`5,838,706 A
`1!1999 Yamamoto eta!.
`5,864,171 A
`5,874,747 A * 2/1999 Redwing eta!. .............. 257/77
`5,905,275 A * 5/1999 Nunoue eta!. ............... 257!95
`5,928,421 A
`7/1999 Yuri eta!.
`6,045,626 A
`4/2000 Yano eta!.
`
`4/2000 Davis eta!.
`6,051,849 A
`6,060,730 A * 5!2000 Tsutsui ....................... 257/103
`6,064,082 A * 5!2000 Kawai eta!. ............... 257/192
`6,121,121 A
`9/2000 Koide
`6,121,634 A * 9/2000 Saito eta!. ................... 257/86
`6,153,010 A
`11/2000 Kiyoku eta!.
`6,177,688 B1
`1!2001 Linthicum et a!.
`6,201,262 B1
`3/2001 Edmond eta!.
`6,239,033 B1 * 5/2001 Kawai ........................ 438/693
`6,255,198 B1
`7/2001 Linthicum et a!.
`6,261,929 B1
`7/2001 Gehrke eta!.
`6,265,289 B1
`7/2001 Zheleva et a!.
`6,355,497 B1
`3/2002 Romano eta!.
`* cited by examiner
`
`EVERLIGHT ELECTRONICS CO., LTD.
`Exhibit 1007
`
`

`

`U.S. Patent
`
`Aug. 26, 2003
`
`Sheet 1 of 8
`
`US 6,611,002 B2
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`16
`
`20
`
`14
`
`L l
`
`Fig. 1
`
`12
`
`22__/
`
`EVERLIGHT ELECTRONICS CO., LTD.
`Exhibit 1007
`
`

`

`U.S. Patent
`
`Aug. 26, 2003
`
`Sheet 2 of 8
`
`US 6,611,002 B2
`
`0
`
`0 \.._
`
`.
`C) ·-u.
`
`EVERLIGHT ELECTRONICS CO., LTD.
`Exhibit 1007
`
`

`

`U.S. Patent
`
`Aug. 26, 2003
`
`Sheet 3 of 8
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`US 6,611,002 B2
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`18~
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`20a
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`22__/
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`20b
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`Fig. 3
`
`EVERLIGHT ELECTRONICS CO., LTD.
`Exhibit 1007
`
`

`

`U.S. Patent
`
`Aug. 26, 2003
`
`Sheet 4 of 8
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`US 6,611,002 B2
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`132
`
`18~
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`41
`
`38
`
`40
`
`36
`
`22__/
`
`Fig. 4
`
`16
`
`14
`
`20
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`EVERLIGHT ELECTRONICS CO., LTD.
`Exhibit 1007
`
`

`

`U.S. Patent
`
`Aug. 26, 2003
`
`Sheet 5 of 8
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`US 6,611,002 B2
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`r42
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`16
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`14
`
`20
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`18~
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`54
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`50
`48
`
`55
`
`52
`
`46
`
`22__}
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`Fig. 5
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`EVERLIGHT ELECTRONICS CO., LTD.
`Exhibit 1007
`
`

`

`U.S. Patent
`
`Aug. 26, 2003
`
`Sheet 6 of 8
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`US 6,611,002 B2
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`16
`
`14
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`20
`
`60
`
`58
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`22~
`
`Fig. 6
`
`EVERLIGHT ELECTRONICS CO., LTD.
`Exhibit 1007
`
`

`

`U.S. Patent
`
`Aug. 26, 2003
`
`Sheet 7 of 8
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`US 6,611,002 B2
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`EVERLIGHT ELECTRONICS CO., LTD.
`Exhibit 1007
`
`

`

`U.S. Patent
`
`Aug. 26, 2003
`
`Sheet 8 of 8
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`US 6,611,002 B2
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`18~
`
`80
`78
`76
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`
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`
`EVERLIGHT ELECTRONICS CO., LTD.
`Exhibit 1007
`
`

`

`US 6,611,002 B2
`
`1
`GALLIUM NITRIDE MATERIAL DEVICES
`AND METHODS INCLUDING BACKSIDE
`VIAS
`
`FIELD OF INVENTION
`
`The invention relates generally to semiconductor materi(cid:173)
`als and, more particularly, to gallium nitride materials and
`methods of producing gallium nitride materials.
`
`BACKGROUND OF INVENTION
`
`Gallium nitride materials include gallium nitride (GaN)
`and its alloys such as aluminum gallium nitride (AlGaN),
`indium gallium nitride (InGaN), and aluminum indium
`gallium nitride (AlinGaN). These materials are semiconduc(cid:173)
`tor compounds that have a relatively wide, direct bandgap
`which permits highly energetic electronic transitions to
`occur. Such electronic transitions can result in gallium
`nitride materials having a number of attractive properties
`including the ability to efficiently emit blue light, the ability
`to transmit signals at high frequency, and others.
`Accordingly, gallium nitride materials are being widely
`investigated in many semiconductor device applications
`such as transistors, field emitters, and optoelectronic
`devices.
`Gallium nitride materials have been formed on a number
`of different substrates including silicon carbide (SiC),
`sapphire, and silicon. Silicon substrates are readily available
`and relatively inexpensive, and silicon processing technol(cid:173)
`ogy has been well developed. However, forming gallium
`nitride materials on silicon substrates to produce semicon(cid:173)
`ductor devices presents challenges which arise from differ(cid:173)
`ences in the lattice constant, thermal expansion, and band
`gap between silicon and gallium nitride.
`Many semiconductor devices include at least two electri(cid:173)
`cal contacts which, for example, provide electrically con(cid:173)
`ducting contact to terminals of a power supply. In a typical
`device, current flows from a first contact (e.g., the anode) on
`the device to a second contact (e.g., the cathode) on the
`device. In certain devices, both the first and the second
`contacts are positioned on a topside (i.e., upper surface) of
`the device. Such devices are referred to as horizontally
`conducting devices because current flows horizontally
`through the device from the first contact to the second
`contact. In other devices, the first contact is positioned on the
`topside of the device and the second contact is positioned on
`a backside (i.e., bottom surface) of the device. Such devices
`are referred to as vertically conducting devices. In some
`cases, vertically conducting devices may be made smaller
`than an otherwise similar functioning horizontal device
`because horizontal devices include multiple topside contacts
`while vertical devices may require only one topside contact.
`Reducing device size may be advantageous because it
`increases the number of devices produced per unit area
`(wafer). Thus, vertically conducting devices may be pre(cid:173)
`ferred over horizontally conducting devices in certain appli-
`cations.
`
`SUMMARY OF INVENTION
`
`The invention includes providing gallium nitride material
`devices having backside vias and methods to form the
`devices. The devices include a gallium nitride material
`formed over a substrate, such as silicon. The device also may
`include one or more non-conducting layers between the
`substrate and the gallium nitride material which can aid in
`
`5
`
`45
`
`2
`the deposition of the gallium nitride material. A via is
`provided which extends from the backside of the device
`through the non-conducting layer(s) to enable electrical
`conduction between an electrical contact deposited within
`the via and, for example, an electrical contact on the topside
`of the device. Thus, devices of the invention may be
`vertically conducting. Exemplary devices include laser
`diodes (LDs), light emitting diodes (LEDs), power rectifier
`diodes, FETs (e.g., HFETs), Gunn-effect diodes, and varac-
`10 tor diodes, amongst others.
`In one aspect, the invention provides a semiconductor
`structure. The semiconductor structure includes a substrate
`having at least one via extending from a backside of the
`substrate and an electrical contact formed in the via. The
`15 semiconductor structure also includes a gallium nitride
`material region formed over the substrate.
`In another aspect, the invention provides a semiconductor
`structure. The semiconductor structure includes a silicon
`substrate having at least one via extending from a backside
`20 of the silicon substrate. The semiconductor structure also
`includes a gallium nitride material region formed over the
`silicon substrate.
`In another aspect, the invention provides a vertically
`conducting semiconductor device. The semiconductor
`25 device includes a silicon substrate and a gallium nitride
`material region formed over the silicon substrate. The semi(cid:173)
`conductor device is capable of vertical conduction.
`In another aspect, the invention provides a semiconductor
`structure. The semiconductor structure includes a silicon
`30 substrate and a gallium nitride material region formed over
`the silicon substrate. The semiconductor structure also
`includes a non-conducting layer formed between the gallium
`nitride material region and the silicon substrate, and an
`electrical contact formed within a via extending from a
`35 backside of the semiconductor structure through the non(cid:173)
`conducting layer.
`In another aspect, the invention provides a method of
`forming a semiconductor structure. The method includes
`40 forming a gallium nitride material region over a substrate,
`forming a via extending from a backside of the semicon(cid:173)
`ductor structure, and forming an electrical contact within the
`v1a.
`In another aspect, the invention provides a method of
`forming a semiconductor structure. The method includes
`forming a gallium nitride material region over a silicon
`substrate, and forming a via extending from a backside of
`the silicon substrate.
`Among other advantages, the invention enables the pro(cid:173)
`duction of vertically conducting gallium nitride material
`devices even when the device includes a non-conducting
`layer. In particular, it is possible to produce vertically
`conducting devices with silicon substrates that include such
`non-conducting layers. Silicon substrates are particularly
`desirable because they are readily available, relatively
`inexpensive, and may be processed using known techniques.
`Furthermore, the vertical conducting devices of the inven(cid:173)
`tion may be formed with smaller dimensions than similar
`functioning horizontal devices due to the presence of fewer
`60 topside contacts on vertically conducting devices. Utilizing
`smaller device dimensions may enable more devices to be
`formed on a given wafer.
`Also, the backside contact formed using the methods of
`the invention may have other advantageous functions. In
`65 some cases, the backside contact can function as a heat sink
`which removes thermal energy generated during the opera(cid:173)
`tion of the device. Also, the backside contact may function
`
`50
`
`55
`
`EVERLIGHT ELECTRONICS CO., LTD.
`Exhibit 1007
`
`

`

`US 6,611,002 B2
`
`3
`as a reflective layer which can enhance output efficiencies of
`optoelectronic devices.
`It should be understood that not every embodiment of the
`invention has all of the advantages described herein. Other
`advantages, aspects, and features of the invention will
`become apparent from the following detailed description of
`the invention when considered in conjunction with the
`accompanying drawings.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 illustrates a semiconductor device including a
`backside via according to one embodiment of the present
`invention.
`FIG. 2 illustrates a semiconductor device including mul- 15
`tiple backside vias according to another embodiment of the
`present invention.
`FIG. 3 illustrates a semiconductor device including mul(cid:173)
`tiple backside vias and no topside vias according to another
`embodiment of the present invention.
`FIG. 4 illustrates an LED according to another embodi(cid:173)
`ment of the present invention.
`FIG. 5 illustrates a laser diode according to another
`embodiment of the present invention.
`FIG. 6 illustrates a power rectifier diode according to
`another embodiment of the present invention.
`FIG. 7 illustrates a double-gate HFET according to
`another embodiment of the present invention.
`FIG. 8 illustrates an LED including multiple backside vias
`and no topside vias according to another embodiment of the
`present invention.
`
`4
`which have a band sufficiently offset from the layer adjacent
`the "non-conducting" layer. A "non-conducting" layer may
`be conductive in and of itself, but may still be non(cid:173)
`conducting (e.g, in a vertical direction) as a result of a band
`5 offset or discontinuity with an adjacent layer. As used herein,
`"vertical conduction" refers to electrical current flow in a
`vertical direction within a device. "Vertical conduction" may
`be between backside contact and topside contact or may be
`between different layers within the device that are separated
`1 o vertically.
`It should be understood that when a layer is referred to as
`being "on" or "over" another layer or substrate, it can be
`directly on the layer or substrate, or an intervening layer also
`may be present. A layer that is "directly on" another layer or
`substrate means that no intervening layer is present. It
`should also be understood that when a layer is referred to as
`being "on" or "over" another layer or substrate, it may cover
`the entire layer or substrate, or a portion of the layer or
`substrate. As shown in the figures, the term "topside" refers
`20 to the upper surface of the device and the term "backside"
`refers to the bottom surface of the device. Thus, the topside
`is opposite the backside of the device.
`In certain preferred embodiments, substrate 12 is a silicon
`substrate. A silicon substrate, as used herein, refers to any
`25 substrate that includes a silicon layer at its topside (i.e.,
`upper) surface. Examples of suitable silicon substrates
`include substrates that are composed of bulk silicon (e.g.,
`silicon wafers), silicon-on-insulator (SOl) substrates,
`silicon-on-sapphire substrates (SOS), and separation by
`30 implanted oxygen (SIMOX) substrates, amongst others.
`High-quality single-crystal silicon substrates are used in
`many embodiments. Silicon substrates 12 having different
`crystallographic orientations may be used. In some cases,
`silicon (111) substrates are preferred. In other cases, silicon
`35 (100) substrates are preferred.
`It should be understood that in other embodiments, sub(cid:173)
`strates other than silicon substrates may be used such as
`sapphire and silicon carbide substrates.
`Substrate 12 may have any dimensions and its particular
`dimensions are dictated by the application. Suitable diam(cid:173)
`eters include, but are not limited to, 2 inches (50 mm), 4
`inches (100 mm), 6 inches (150 mm), and 8 inches (200
`mm). In some embodiments, silicon substrate 12 is relatively
`thick, for example, greater than 250 microns. Thicker sub(cid:173)
`strates are generally able to resist bending which can occur,
`in some cases, in thinner substrates. In some embodiments,
`silicon substrate 12 is preferably thin, for example less than
`100 microns, to facilitate the formation of via 24 there(cid:173)
`through.
`Non-conducting layer 15 may be formed on substrate 12
`prior to the deposition of gallium nitride material device
`region 14, for example, to accomplish one or more of the
`following: reducing crack formation in gallium nitride mate(cid:173)
`rial device region 14 by lowering thermal stresses arising
`from differences between the thermal expansion rates of
`gallium nitride material device region 14 and substrate 12;
`reducing defect formation in gallium nitride material device
`region 14 by lowering lattice stresses arising from differ(cid:173)
`ences between the lattice constants of gallium nitride mate(cid:173)
`rial device region 14 and substrate 12; and, increasing
`conduction between substrate 12 and gallium nitride mate(cid:173)
`rial device region 14 by reducing differences between the
`band gaps of substrate 12 and gallium nitride material device
`65 region 14. It should be understood that non-conducting layer
`15 also may be formed between substrate 12 and gallium
`nitride material device region for a variety of other reasons.
`
`DETAILED DESCRIPTION OF THE
`INVENTION
`
`The invention provides gallium nitride material devices
`including backside vias and methods to form the devices.
`Referring to FIG. 1, a semiconductor device 10 according
`to one embodiment of the invention is shown. Semiconduc- 40
`tor device 10 includes a substrate 12 and a gallium nitride
`material device region 14 formed over the substrate. As
`described further below, device structures are typically
`formed, at least in part, within gallium nitride material
`region 14. Device 10 further includes a non-conducting 45
`layer 15 formed on substrate 12, for example, to facilitate the
`subsequent deposition of gallium nitride material device
`region 14. A topside electrical contact 16 (on a topside 18 of
`the device) and a backside electrical contact 20 (on a
`backside 22 of the device) are provided for connection to an 50
`external power supply that powers the device. Backside
`contact 20 is deposited within a via 24 that extends from
`backside 22 of the device. Via 24 extends through non(cid:173)
`conducting layer 15 and into a conducting region (e.g.,
`device region 14) within device 10. As a result of the 55
`deposition of backside contact 20 within via 24, current can
`flow between the backside contact and topside contact 16
`through device region 14 without being blocked by non(cid:173)
`conducting layer 15. Thus, vertical conduction through
`device 10 between backside contact 20 and topside contact 60
`16 may be achieved despite the presence of non-conducting
`layer 15.
`As used herein, "non-conducting" refers to a layer that
`prevents current flow or limits current flow to negligible
`amounts in one or more directions. "Non-conducting"
`layers, for example, may be formed of non-conductor
`materials, or may be formed of semiconductor materials
`
`EVERLIGHT ELECTRONICS CO., LTD.
`Exhibit 1007
`
`

`

`US 6,611,002 B2
`
`5
`The presence of non-conducting layer 15 may be particu(cid:173)
`larly preferred when utilizing silicon substrates.
`The composition of non-conducting layer 15 depends, at
`least in part, upon the type of substrate and the composition
`of gallium nitride material device region 14. In some
`embodiments which utilize a silicon substrate, non(cid:173)
`conducting layer 15 may preferably comprise a
`compositionally-graded transition layer having a composi(cid:173)
`tion that is varied across at least a portion of the layer.
`Suitable compositionally-graded transition layers, for 10
`example, have been described in co-pending, commonly(cid:173)
`owned, U.S. patent application Ser. No. 09/736,972, entitled
`"Gallium Nitride Materials and Methods," filed on Dec. 14,
`2000, which is incorporated herein by reference.
`Compositionally-graded transition layers are particularly 15
`effective in reducing crack formation in gallium nitride
`material device region 14 by lowering thermal stresses that
`result from differences in thermal expansion rates between
`the gallium nitride material and substrate 12 (e.g., silicon).
`In some embodiments, when non-conducting layer 15 is 20
`compositionally-graded, layer 15 is composed of an alloy of
`gallium nitride such as Al)nyGa(l-x-y)N, AlxGa(l-x)N, or
`InYGa(l-y)N. In these embodiments, the concentration of at
`least one of the elements (e.g., Ga, Al, In) of the alloy is
`typically varied across at least a portion of the cross- 25
`sectional thickness of the layer.
`In other embodiments, non-conducting layer 15 has a
`constant (i.e., non-varying) composition across its thickness.
`Such non-conducting layers include buffer layers and inter(cid:173)
`mediate layers. Suitable intermediate layers, for example,
`have been described in U.S. patent application Ser. No.
`09/736,972, referenced above. In some embodiments, non(cid:173)
`conducting layer 15 has a constant composition of a gallium
`nitride alloy such as Al)nyGa(l-x-y)N, AlxGa(l-x)N, or
`InYGa(l-y)N.
`In the illustrative embodiment, a single non-conducting
`layer 15 is shown between substrate 12 and gallium nitride
`material device region 14. Other embodiments may include
`more than one non-conducting layer. For example, device 10 40
`may include a non-conducting compositionally-graded tran(cid:173)
`sition layer and a non-conducting intermediate layer. It also
`should be understood that in some embodiments, one or
`more conducting layers also may be present between sub(cid:173)
`strate 12 and gallium nitride material device region 14 which 45
`may accomplish one or more of the above-described features
`of non-conducting layers. For example, the compositionally(cid:173)
`graded transition layer may be conducting in certain cases.
`In the embodiment of FIG. 1, via 24 extends through
`non-conducting layer 15 of substrate 12 so that vertical 50
`conduction can occur in device 10. Thus, at a minimum, via
`24 has a length (L) sufficient to create a conducting vertical
`path between topside contact 16 and backside contact 20.
`Via 24, for example, may extend to a position within gallium
`nitride material device region 14 to form such a conducting 55
`path. In some cases, it may be preferable to have via 24
`extend to an etch-stop layer (e.g., See 46, FIG. 5) within
`gallium nitride material device region 14, to facilitate pro(cid:173)
`cessing as described further below. In certain embodiments,
`via 24 may extend to a position below gallium nitride 60
`material device layer-for example, within an upper portion
`of a doped, conductive transition layer and, thus, a vertical
`conducting path is formed. In some cases, via 24 may extend
`to a source region or a drain region formed within device 10.
`The exact dimensions and shape of via 24 depend upon 65
`the application. A typical cross-sectional area of via is about
`100 microns by about 100 microns at backside 22. It may be
`
`6
`preferable for via 24 to be tapered inward, as shown, thus
`giving the via a cone shape. The inward taper can facilitate
`deposition of backside contact 20 on side walls 28 of via 24.
`In FIG. 1, device 10 includes a single via 24. Other
`5 embodiments, however, as described further below and
`shown in FIGS. 2-3 may include more than one via.
`As used herein, the phrase "electrical contact" or "con-
`tact" refers to any conducting structure on the semiconduc(cid:173)
`tor device that may be effectively contacted by a power
`source including electrodes, terminals, contact pads, contact
`areas, contact regions and the like. Backside contact 20 and
`topside contact 16 are formed of conducting materials
`including certain metals. Any suitable conducting material
`known in the art may be used. The composition of contacts
`16, 20 may depend upon the type of contact. For example,
`contacts 16, 20 may contact n-type material or p-type
`material. Suitable metals for n-type contacts include
`titanium, nickel, aluminum, gold, copper, and alloys thereof.
`Suitable metals for p-type contacts include nickel, gold, and
`titanium, and alloys thereof.
`Contacts 16, 20 have a thickness sufficient to ensure that
`the contact is electrically conductive across its entire physi(cid:173)
`cal area. Suitable thicknesses for contacts 16, 20, for
`example, are between about 0.05 microns and about 10
`microns. In some cases, the thickness of backside contact 20
`may vary over its area because of uneven deposition on side
`walls 28 of via 24. The surface areas of backside contact 20
`and topside contact 16 are generally sufficient so that the
`contacts can be contacted by terminals of an appropriate
`power source through wire bonding, air bridging and the
`like. In certain preferred embodiments, backside contact 20
`substantially extends only over backside and does not, for
`example, extend over sides 30 of device 10. Thus, in these
`preferred embodiments, sides 30 are substantially free of
`backside contact 20.
`In some embodiments, backside contact 20 also may
`function as an effective heat sink. In these embodiments,
`backside contact 20 removes thermal energy generated
`during the operation of the device. This may enable device
`10 to operate under conditions which generate amounts of
`heat that would otherwise damage the device. In particular,
`laser diodes that operate at high current densities may utilize
`backside contact 20 as a heat sink. Backside contact 20 may
`be specifically designed to enhance thermal energy removal.
`For example, backside contact 20 may be composed of
`materials such as copper and gold, which are particularly
`effective at removing heat. Also, backside contact 20 and via
`24 may be designed so that a large surface area is in contact
`with device region 14-for example, by including multiple
`vias and/or vias that extend significantly into device region
`14.
`In some embodiments, such as when device 10 is an
`opto-electronic device, backside contact 20 can function as
`a reflective layer. By efficiently reflecting internally emitted
`light away from substrate 12, backside contact 20 can direct
`the emitted light out of topside 18 and sides 30 of device 10.
`Thus, the output efficiency of the device may be enhanced.
`In particular, laser diodes and light emitting diodes can
`benefit from utilizing the reflective properties of backside
`contact 20. To enhance the ability of backside contact 20 to
`reflect light, via 24 is formed such that the backside contact
`extends proximate a light emitting active layer (e.g., 38,
`FIG. 4; 50, FIG. 5).
`Gallium nitride material device region 14 comprises at
`least one gallium nitride material layer. In some cases,
`gallium nitride material device region 14 includes only one
`
`30
`
`35
`
`EVERLIGHT ELECTRONICS CO., LTD.
`Exhibit 1007
`
`

`

`US 6,611,002 B2
`
`7
`gallium nitride material layer. In other cases, as described
`further below and shown in FIGS. 4--8, gallium nitride
`material device region 14 includes more than one gallium
`nitride material layer. The different layers can form different
`regions of the semiconductor structure. Gallium nitride
`material region also may include one or more layers that do
`not have a gallium nitride material composition such as
`oxide layers or metallic layers.
`As used herein, the phrase "gallium nitride material"
`refers to gallium nitride (GaN) and any of its alloys, such as
`aluminum gallium nitride (AlxGa(l-x)N), indium gallium
`nitride (InYGa(l-y)N), aluminum indium gallium nitride
`(Al)nyGa(l-x-y)N, gallium arsenide phosporide nitride
`(GaAsaPb N(l-a-b)), aluminum indium gallium arsenide
`phosporide nitride (Al)nyGa(l-x-y) ASaPb N(l-a-b)), amongst 15
`others. Typically, when present, arsenic and/or phosphorous
`are at low concentrations (i.e., less than 5 weight percent).
`In certain preferred embodiments, the gallium nitride mate(cid:173)
`rial has a high concentration of gallium and includes little or
`no amounts of aluminum and/or indium. In high gallium 20
`concentration embodiments, the sum of (x+y) may be less
`than 0.4, less than 0.2, less than 0.1, or even less. In some
`cases, it is preferable for the gallium nitride material layer to
`have a composition of GaN (i.e., x+y=O). Gallium nitride
`materials may be doped n-type or p-type, or may be intrinsic. 25
`Suitable gallium nitride materials have been described in
`U.S. patent application Ser. No. 09/736,972, incorporated
`herein.
`Gallium nitride material region 14 is of high enough
`quality so as to permit the formation of devices therein.
`Preferably, gallium nitride material region 14 has a low
`crack level and a low defect level. As described above,
`non-conducting layer 15 may reduce crack and/or defect
`formation. In some embodiments, gallium nitride material
`region 14 has about 109 defects/cm 2
`. Gallium nitride mate(cid:173)
`rials having low crack levels have been described in U.S.
`patent application Ser. No. 09/736,972, referenced above. In
`some cases, gallium nitride material region 14 has a crack
`level of less than 0.005 fAm/f.Im2. In some cases, gallium
`nitride material has a very low crack level of less than 0.001
`j.1m/j.1m2
`. In certain cases, it may be preferable for gallium
`nitride material region 14 to be substantially crack-free as
`defined by a crack level of less than 0.0001 j.1m/j.1m2
`.
`In certain cases, gallium nitride material region 14
`includes a layer or layers which have a monocrystalline
`structure. In some preferred cases, gallium nitride material
`region 14 includes one or more layers having a Wurtzite
`(hexagonal) structure.
`The thickness of gallium nitride material device region 14
`and the number of different layers are dictated, at least in
`part, by the requirements of the specific application. At a
`minimum, the thickness of gallium nitride material device
`region 14 is sufficient to permit formation of the desired
`device. Gallium nitride material device region 14 generally
`has a thickness of greater than 0.1 micron, though not
`always. In other cases, gallium nitride material region 14 has
`a thickness of greater than 0.5 micron, greater than 0.75
`micron, greater than 1.0 microns, greater than 2.0 microns,
`or even greater than 5.0 microns.
`Device 10 may be formed using known processing tech(cid:173)
`niques. Non-conducting layer 15 and gallium nitride mate(cid:173)
`rial device region 14 may be deposited on substrate 12, for
`example, using metalorganic chemical vapor deposition
`(MOCVD), molecular beam epitaxy (MBE), hydride vapor 65
`phase epitaxy (HYPE), amongst other techniques. In some
`cases, an MOCVD process may be preferred. A suitable
`
`8
`MOCVD process to form a compositionally-graded non(cid:173)
`conducting layer 15 and gallium nitride material device
`region 14 over a silicon substrate 12 has been described in
`U.S. patent application Ser. No. 09/736,972, referenced
`5 above. When gallium nitride material device region 14 has
`different layers, in some cases it is preferable to use a single
`deposition step (e.g., an MOCVD step) to form the entire
`device region 14. When using the single deposition step, the
`processing parameters are suitably changed at the appropri-
`10 ate time to form the different layers. In certain preferred
`cases, a single growth step may be used to form non(cid:173)
`conducting layer 15 and gallium nitride material device
`region 14.
`In some cases, it may be preferable to grow device region
`14 using a lateral epitaxial overgrowth (LEO) technique that
`involves growing an underlying gallium nitride layer
`through mask openings and then laterally over the mask to
`form the gallium nitride material device region, for example,
`as described in U.S. Pat. No. 6,051,849, which is incorpo-
`rated herein by reference. In some cases, it may be prefer(cid:173)
`able to grow device region 14 using a pendeoepitaxial
`technique that involves growing sidewalls of gallium nitride
`material posts into trenches until growth from adjacent
`sidewalls coalesces to form a gallium nitride material
`region, for example, as described in U.S. Pat. No. 6,177,688,
`which is incorporated herein by reference.
`Conventional etching techniques may be used t