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`PATENT NUMBER
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`6054336
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`sees|anlgle IAAT
`aeS. UTILITY PATENTAPPLICATION
`
`
`soxinesmee OF2G,|APR 25 2000
`
`
`690
`4
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`O.1.P.E.
`
`PATENT DATE
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`
`ART UNIT
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`[_] FICHE
`FITED WITH: [_] DISK (CRF)
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`PREPARED AND APPROVEDFORISSUE
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`UING CLASSIFICATION
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`%|S
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`
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`
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`CROSS REFERENCE(S)
`eeee
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`[Dose 1poursInele||1
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`
`
`
`
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`
` TERMINAL
`DISCLAIMER
`
` 0 a) The term of this patent
` C b) The term ofthis patent shall
`
`(date)
`subsequentto
`
`has been disclaimed.
`
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`not extend beyond the expiration date
`of U.S Patent. No.
`
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`O c) The terminal
`monthsof
`this patent have.been disclaimed.
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`WARNING:
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`
`Possession outside the U.S. Patent & Trademark Office is restricted to authorized employees and contractors only.
`Form PTO-436A
`(Rev. 10/97)
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`issue Fee In File
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`>
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`“PATENT APPLICATION
`SONU mal 4 9839
`
`09085085
`
`CONTENTS
`Date received
`(Incl. C. of M.)
`or
`Date Mailed
`
`42.
`
`Date received’
`(Incl. C. of M.)
`or
`Date Mailed
`
`.
`
`\ |
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`SS
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`Page 2 of 90
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`

`
`
`
`
`INITIALS POSITION
`‘exomrenmaron|Z.[1[0257|O.LP.E.CLASSIFIER|oY|BRSL|
`
`
`
`
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`[FORMALITYREVIEW|“/”%S\NUGIT|6IE
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`INDEX OF CLAIMS
`VA sccssssssssssssssnssesesessees Rejected
`No
`viessesessesssesssesssreseesnees Non-elected
`BE
`Lsssscsesscsasercessssereneeceres Allowed
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`A visssesssessscsescscstneeeseeeees Appeal
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`iceseceseseescesseeseeeeeens Restricted
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`If more than 150 claims or 10 actions
`staple additional sheet here
`
`(LEFT INSIDE)
`
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`
`
`
`
`
`RCHED
`
`~~SEARCH NOTES
`
`
`SEA
`
`(INCLUDING SEARCH STRATEGY)
`
`
`
`
`
`
`Poise[sub|ae[exe
`elles Asyit-
`U3¢ 160
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`U fac|L
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`PATENT APPLICATION SERIAL NO. O& pezSS
`
`U.S. DEPARTMENT OF COMMERCE
`PATENT AND TRADEMARK OFFICE
`FEE RECORD SHEET
`
`06/03/1998 BHINES
`
`00000010 141270
`
`09085085
`
`O1 FO:10i
`
`790.00 CH
`
`PTO-1556
`(5/87)
`
`Coteee
`
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`
`SERIAL NUMBER GROUP ART UNIT|ATTORNEY DOCKET NO,FILING DATE CLASS
`
`
`
`
`
`16.387
`APPLICANT
`EINDHOVEN, NETHERLANDS.
`/
`
`09/085,085
`
`05/26/98
`
`438
`
`2812
`
`HERMANUS L. PEEK, EINDHOVEN, NETHERLANDS; DANIEL W. E. VERBUGT,
`
`/
`
`DOMESTIC DATARHHKHRKAKKHKKHEKHAKEEK nae -
`
` 371 (NAT'L
`VERIFIED
`
`AGE ) DATTARRR III IOIII
`-
`
`
`
`
`
`_ **FOREIGN APPL
`VERIFIED
`
`
`TIONS ** KKK KKK AH KK
`EPO
`
`97201585.3
`
`05/29/97
`
`INDEPENDENT
`Foreign Priority
`Gy6s 0
`claimed
`STATE OR
`SHEETS
`TOTAL
`
`
`
`
`
`
`
`| 35 Use 119Sh immedone nmetf[Byres (no (Metafter Allowance|COUNTRY DRAWING CLAIMS CLAIMS
`
`
`
`
`
`
`
`
`
`1 Verified and Acknowledged
`10
`NLX
`3
`
`Lo] A
`Exeraner sInitials
`
`US PHILIPS CORP
`
`CORPORATE PATEN
`
`580 WHITE PLAINS RD
`TARRYTOWN Ny 10591
`
`
`
` METHOD OF MANUFACTURING AN ELECTRONIC DEVICE
`
`
`ADDRESS
`
`
`
`RECEIVED
`FEES: Authority has been given in Paper
`CI 1ros (Filing)
`
`No. _____ to charge/credit DEPOSIT ACCOUNT
`1.17 Fees (Processing Ext. of time)
`$920
`NO.
`for the following:
`1.18 Fees (Issue)
`LC] oe——_——
`
`[] Cred
`
`FILING FEE
`
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`28/6TORN i
`
`20231
`
`t p
`ao
`
`Case Docket wo. PHN 16,387
`5“THE COMMISSIONER OF PATENTS AND TRADEMARKS, Washington, D.C.
`ea
`SS sEnclosed for filing is the patent application of Inventor(s):
`ecHERMANUS L. PEEK AND DANIEL W.E. VERBUGT
`Yo "For: METHOD OF MANUFACTURING AN ELECTRONIC DEVICE
`_—=ENCLOSEDARE:
`te Information Disclosure Statement, Form PTO-1449 and copies of
`Appointment of Associates;
`documents listed therein;
`Prelimina
`Amendment;
`{X]
`({X] Specification (9 Pages of Specification, Claims, & Abstract);
`{X] Declaration and Power of Attorney:
`[X] unsigned Declaration) ;
`(1 Pages of a [ ]fully executed
`[X] formal sheets) ;
`[X] Drawing (3 sheets of
`[
`] informal
`{X] Certified copy of EUROPEAN application Serial No. 97201585.3;
`{X] Authorization Pursuant to 37 CFR §1.136 (a) (3)
`[
`] Other:
`;
`[
`] Assignment to
`
`te NUMBER FILED|NUMBER RATE BASIC FEE
`
`CLAIMS AS FILED
`
`
`
`te
`EXTRA
`$790.00
`der
`
`|TotalClaims|Claims CE:Ix$22.=|
`
`Independent
`X $82
`Claims
`
`mrWPgene eeit
`
`eenreteanngitCORNGEaNE
`
`wen
`
`seenedAS
`meat
`on
`ai
`
`Multiple Dependent Claims, if any
`
`2:00.00
`°
`°
`.
`TOTAL FILING FEE...
`Please charge Deposit Recount No. ia- 1270 in the amount of
`the total filing fee indicated above, plus any deficiencies. The
`Commissioner is also hereby authorized to charge any other fees
`which may be required, except the issue fee, or credit any
`overpayment to Account No. 14-1270.
`
`$270 =
`
`]Amend the specification by inserting before the first line
`{[
`as a centered heading --Cross Reference to Related Applications--;
`and insert below that as a new paragraph --This is a continuation-
`in--part of application Serial No.
`, filed
`.--, which is
`herein incorporated by reference--.
`
`CERTIFICATEOFEXPRESSMAILING
`Express Mail Mailing Label No. EmM+4or7162axsFqUus
`Date of Deposi
`paper and/or fee is being
`| hereby certify that this
`deposited with the United States Postal Service "Express
`"
`.
`Mail Post Office to Addressee” service under 37 C.F.R.
`1.10 on the date indicated above and is addressed to the
`Commissioner of Patents and Trademarks, Washington,
`
` £
`
`0 rey
`(914) 333-9633
`U.S. Philips Corporation
`580 White Plains Road
`saisBwini.ono 0691
`
`D.C. 20231.
`
`(
`
`T
`
`‘A G
`Name
`
`‘
`
`‘
`Sigpature
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`IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`Serial No.
`
`Group Art Unit
`
`|i
`
`i
`
`Filed: CONCURRENTLY
`
`EX.
`
`METHOD OF MANUFACTURING AN ELECTRONIC DEVICE
`
`Honorable Commissioner of Patents and Trademarks
`Washington, D.C. 20231
`
`AUTHORIZATIONPURSUANTTO37CFR81,136(a)(3)
`ANDTOCHARGEDEPOSITACCOUNT
`
`Sir:
`
`The Commissioner is hereby requested and authorized to
`treat any concurrent or future reply in this application requiring
`a petition for extension of time for its timely submission, as
`incorporating a petition for extension of time for the appropriate
`length of time.
`
`Please charge any additional fees which may now or in the
`future be required in this application,
`including extension of time
`fees, but excluding the issue fee unless explicitly requested to do
`so, and credit any overpayment,
`to Deposit Account No. 14-1270.
`
`
`
`C: \NEWAPPS\CHRGAUTH. WI
`
`Page 8 of 90
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`SAMSUNG EXHIBIT 1004
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`In re Application of
`
`HERMANUS L. PEEK ET AL
`
`Atty. Docket
`
`PHN 16,387
`
`Page 8 of 90
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`

`- PHN 16.387
`
`Method of manufacturing an electronic device
`
`1
`
`|
`
`30.10.1997
`
`TN3 Bl
`
`The invention relates to a method of manufacturing an electronic device
`whereby a conductive layer is provided on an electrically insulating substrate, from which
`layer a conductor pattern is formed by means of a mask comprising a dielectric layer in
`which said pattern is defined by openings which were formed in the dielectric layer by means
`of lithography, which dielectric layer at the areas of the windows to be formed is provided
`
`5
`
`with auxiliary windows having dimensions which are greater, at least in one direction, than
`
`the dimensions of the windows to be formed, whereupon an additional dielectric layeris
`
`provided which is etched back anisotropically without a mask such that of the additional layer
`
`spacers remain behind on side walls of the auxiliary windows. The invention is of particular
`
`
`
`3
`
`10
`
`importance for monolithically integrated circuits. In addition, however, the invention may
`
`also be of importance for other devices in which electrical conductors are provided at very
`
`small distances from one another, as will become clear from the description, such as, for
`
`
`
`15
`be
`
`example, PCBs, or control matrices for LCDs.
`
`Such a method is known, for example, from the article "A Single-Layer
`Metal-Electrode CCD Image Sensor" by Nakamuraet al., published in the Digest of
`technical papers of the 1995 IEEE International Solid-State Circuits Conference, pp. 222-
`223. In this known method, which is used for the manufacture of gates of a CCD, the
`
`conductor layer is formed by a WSi layer which is covered with a silicon oxide layer in
`
`20 which a mask is formed for patterning the WSi layer. Auxiliary windows are provided in the
`oxide layer at the areas of the gaps between the gates to be formed for this purpose, the
`
`25
`
`dimensions of the auxiliary windows being greater than those of the gaps to be eventually
`obtained. The oxide layer is etched throughoutits entire thickness, so that the WSi layer lies
`exposed in the auxiliary windows. The mask windows of reduced dimensions are obtained
`through the application of spacers on the side walls of the auxiliary windows.
`In the method described here, thesilicon oxide layer is etched downto the
`gates to be formed. This may give rise to problemsif the etching selectivity betweensilicon
`oxide and the conductor material is not sufficiently great, because in that case the gate
`material will also be attacked. It is of major importance that the material of the gates should
`
`aa teneeare,
`
`~
`
`
`—— =
`aeenntngn
`
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`PHN 16.387
`
`2
`
`|
`
`30.10.1997
`
`not or at least substantially not be made locally thinner owing to the etching of the silicon
`oxide layer, especially in cases where the conductor layer is very thin, for example
`comprises a layer of 60 nm thick polycrystalline silicon (poly) in view of the envisaged
`- photosensitivity of the CCD imager.
`The invention accordingly has for its object inter alia to modify a method
`of the kind mentioned in the opening paragraph in such a mannerthat the conductor material
`
`of the gates is not or substantially not attacked by the etchant for the silicon oxide layer.
`A further problem which often arises, at least with the use of
`polycrystalline silicon as the conductor material, while the gates are formed through etching
`of poly, is that short-circuits of more or less high-ohmic values occur between the gates after
`
`|
`
`etching of the poly, probably as a result of material remaining behind in the gaps after
`
`etching. The invention accordingly has for its further object to provide a method whereby
`
`5
`
`10
`
`such short-circuits can be prevented while very narrow gaps between the conductor tracks are
`
`opening paragraph is for this purpose characterized in that the auxiliary windows are
`
`retained. According to the invention, a method of the kind mentioned in the
`
`
`provided through only part of the thickness of the dielectric layer, and in that etching of the
`
`dielectric layer is continued, after the anisotropic etching-back of the additional layer, until
`
`the dielectric layer has been locally removed throughoutits entire thickness at the areas of
`
`the auxiliary windows, whereupon the conductor pattern is formed in the conductive layer
`
`through the windowsthus formed in the dielectric layer.
`
`The fact that the spacers are provided on the side walls of the auxiliary
`
`windowsin a stage in which the conductive layeris still entirely covered by the dielectric
`layer, in accordance with the invention, meansthat at most those portions of the conductive
`
`25
`
`layer which are situated at the areas of the gaps to be formed, i.e. which will be removed
`
`anyway, are exposed to the etching treatment the momentthe etching has progressed so far
`that the conductive layer is reached.
`i
`
`A layer of a suitable metal or of a conductive metal compound, for
`
`30
`
`example a metal silicide, may be used as the conductive layer. In an embodimentof a
`method according to the invention which is important on account of the use of polycrystalline
`or amorphoussilicon in the manufacture of integrated circuits, the conductive layer is
`
`provided in the form of a layer comprising silicon.
`
`A further major embodiment of a method according to the invention is
`
`}2
`
`terea ateeeseen
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`PHN 16.387
`
`3
`
`30.10.1997
`
`characterized in that the dielectric layer is provided as a dual layer comprising a sub-layer
`formed byasilicon nitride layer and a sub-layer of silicon oxide which is separated from the
`conductive layer by the nitride layer. The use of the nitride, which forms an oxidation mask,
`renders it possible to carry out an oxidation step in the gaps between the conductortracks,
`5 whereby undesirable short-circuits between the conductor tracks are prevented.
`After the windows have been formed in the dielectric layer, a ©
`corresponding pattern of openings may be advantageously provided in the conductive layer
`by etching, whereupon the exposed side walls of the conductor tracks can be oxidized by
`meansof said oxidation step. A preferred embodiment, in which a further reduction of the
`gaps between the conductor tracks can be obtained, is characterized in that the silicon oxide
`sub-layer is provided to a thickness which is greater than the thickness of the silicon oxide
`
`10
`
`|
`
`es
`
`'
`
`layer which forms said mask, whereupon said layer is provided with auxiliary windows
`which extend over only part of the silicon oxide layer at the areas of the windows to be
`
`formed, whereupon the additional layer also comprising silicon oxide is provided. Such a
`
`15 methodis particularly advantageous for conductive layers having a small or very small
`
`thickness, for example a thickness of at most 0.1 um. To reduce oxidation of the conductor
`tracks in lateral direction as much as possible, preferably, the oxidation is carried out in an
`
`BehPMaywetHRADRERE
`eyatSoeehAta
`oxidizing environmentcontaining water vapor. These and other aspects of the invention will be explained in more detail
`
`with reference to a few embodiments. In the drawing:
`
`Fig.
`
`1 is a cross-section of a semiconductor device manufactured by a
`
`method according to the invention in various stages of its manufacture; and
`
`Fig. 2 is a cross-section of a semiconductor device manufactured by a
`modification of the above method in two stages of its manufacture.
`
`
` invention is explained with reference to a charge coupled device, in particular an imaging
`
`It is noted that the drawing is diagrammatic and nottrue to scale. The
`
`device, in which it is of major importance that the electrodes should be at very small
`
`distances from one another. It is usual to provide the electrodes in a multilayer wiring in
`
`30 which adjoining electrodes overlap. Major advantages are obtained when the electrodes can
`
`be formed in a single poly layer, whereby process steps can be dispensed with and in
`addition a more planar structure can be obtained. It will become clear from the ensuing
`description that the invention has a much wider field of application than CCDsalone and, in
`general, may be applied whereverelectrodes are to be provided at very small distances from
`
`Lf
`
`tne nnn = eng
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`PHN 16.387
`
`4
`
`30.10.1997
`
`one another on an electrically insulating substrate. In the present example, the insulating
`substrate is formed by a gate dielectric layer 1 provided on the surface ofa silicon body 2
`(Fig. 1a). The conductivity type and the doping concentration in the semiconductor body are
`
`such that CCD operation is possible in the body 2. The dielectric layer 1 may comprise a
`single layer of, for example, silicon oxide, but in the present example comprises a dual layer
`with a layer 1a of silicon oxide and a layer 1b ofsilicon nitride. The presence of the nitride
`layer 1b renders it possible inter alia to carry out oxidation steps without appreciably
`changing the gate dielectric 1. A doped polycrystalline silicon layer 3 (poly) in which the
`
`10
`
`gates or electrodes of the charge coupled device are to be defined is provided on the
`dielectric layer 1. To limit absorption of light in the gates as much as possible, and thus to
`makethe sensitivity of the imaging device as high as possible, the layer 3 is made very thin,
`
`
`“:
`
`woKe oO
`
`nieeteURDeSee
`
`Qhwe
`
`i.e. thinner than approximately 0.1 ~m. The thickness of the poly layer 3 is approximately
`60 nm in the present example. A secondsilicon nitride layer, the layer 4, is provided on the
`poly layer 3 so as to form an oxidation mask for the poly layer 3. A comparatively thick (=
`$5-ym) oxide layer 5 is deposited on the nitride layer 4. A photoresist layer is provided
`thereon, and an etching mask 6 is formed in this photoresist in a usual manner, with
`
`openings 7 at the areas of the gaps to be formed between the gates. The width of the
`a hist
`openings 7 is, for example, 0.5 um. Fig. la showsthis stage in the process.
`The pattern of openings 7 in the photoresist layer 6 is transferred to the
`dielectric layer 4, 5 by meansof anisotropic etching. In an extreme case, the openings can be
`provided right across the thickness of the oxide layer 5 down to the nitride layer. In the
`present example, however, the layer 5 is not etched throughoutits entire thickness, but only
`through part of its thickness, for example through half or approximately half the layer 5 as
`shown in Fig. lb. This Figure shows the device after the photoresist layer 6 has been
`
`25
`
`removed subsequentto the etching of the oxide 5. The windows8 in the oxide layer 5 have
`
`30
`
`dimensions which correspond to those of the openings 7 in the mask 6 and are considerably
`
`greater, as will become apparent below, than those of the gaps to be formed in the
`conductive layer 3.
`*
`In a next stage shown in Fig. 1c, an additional oxide layer 9 is formed
`with a thickness of, for example, 0.25 um, the pattern of windows8 being presentalso in
`this additional layer. The layer 9 is subsequently removed again by meansof anisotropic
`etching-back, such that, at the moment when the horizontal portions of the layer 9 have been
`removed, only portions 10 of the additional layer, referred to asspacers for short, remain on
`the side walls of the auxiliary windows 8 (Fig. 1d), strongly reducing the dimensions ofthe
`
`—,
`A
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`5
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`30.10.1997
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`auxiliary windows 8. The etching treatment is continued (without mask) until the windows 11
`(Fig. le) are obtained, which windowsextend straight across the thickness of the remaining
`oxide layer 5 down to the nitride layer 4. As is shown in this Figure, the windows 11 have a
`
`tapering shape in downward direction, so that the width at the bottom of the windows11 is
`considerably smaller than that at the top and is no more than approximately 0.2 wm. The .
`etching treatment may be simply stopped the momentthe poly layer 3 is reached. Fig. 1f
`
`showsthe device in this stage of the process. The silicon oxide layer 5 can then be removed
`
`(Fig. 1g). The silicon nitride Jayer 4, provided with the very narrow windows11, is used as
`a mask in the subsequent oxidation step in which the silicon of the poly layer 3 lying exposed
`in the windows 11 is converted into silicon oxide 12 by meansof oxidation. The oxidized
`portions 12 extend through the entire thickness of the conductive layer 3 and define gates 13
`
`5
`
`10
`
`in this layer which are mutually separated by the oxidized portions 12 (Fig. 1h). The
`
`%
`Sil
`2215
`e
`
`oxidation step can be carried out such that short-circuits between adjoining gates 13 is
`prevented. To make the gaps between the gates 13 as small as possible, moreover, the
`oxidation is carried out in an oxidizing environment comprising water vapor. It has been
`found that under these circumstances the oxidation in lateral directions below thesilicon
`
`mS
`
`nitride at the edges of the windows11 is minimal, so that also the width of the oxide
`
`
`
`portions 12, and thus of the gaps between the electrodes 13, will be minimal. A possible
`
`explanation is that the presence of water vapor causes the formation of nitrogen-containing
`
`regions constituting a barrier against oxidation locally in the poly layer 3 at the boundary
`
`surfaces with the nitride layers 2 and 4. Since the poly Jayer is very thin, these nitrogen-
`
`containing regions can form a continuous oxidation barrier in the poly layer 3 close to the
`
`25
`
`30
`
`edges of the openings 11, preventing oxidation in lateral directions. In the present
`
`embodiment, where the thickness of the poly layer 3 is approximately 60 nm,the poly layer
`3 canbe oxidized throughits entire thickness in a comparatively short period at a
`temperature of 1000 °C. In an embodimentrealized in practice, the width of the inter-
`electrode gaps was 0.2-0.25 ym, whichis sufficiently small for achieving a satisfactory
`operation of the charge coupled device.
`-
`Fig. 2 shows a modification of the manufacturing process described
`
`above,starting with the situation of Fig. 1g, where the nitride layer 4 is provided with the
`narrow windows11. Instead of an oxidation step, the poly layer 3 is now first subjected to
`an etching treatment whereby the openings 11 are formed also in the poly layer 3 right
`
`through the thickness of the poly layer. Fig. 2a shows this stage in the process. The
`electrodes 13 have already been formed in the poly layer 3 through the openings 11 at this
`
`ie emerter=ener3nerre
`
`W
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`30.10.1997
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`stage. Then, see Fig. 2b, a light oxidation step is carried out. Any residues of conductor
`
`material between the gates 13 are converted into electrically insulating oxide by this
`
`oxidation step, so that short-circuits between gates are prevented. In addition,the lateral
`
`5
`
`sides of the gates are covered with a thin oxide layer 14 during this oxidation step. In this
`embodiment, the width of the inter-electrode gaps is determined by the width of the windows
`11 augmented by the widths of the oxidized edges of the electrodes. The total gap width may
`accordingly be slightly greater than in the preceding embodiment. On theother hand, this
`modification of the method is also suitable for use with greater thicknesses of the poly layer
`
`hs
`
`3.
`
`10
`
`It will be obvious that the invention is not limited to the embodiments
`
`described here but that many more variations are possible to those skilled in the art within
`
`the scope of the invention. Thus, for example, the nitride-poly-nitride layer structure as used
`
`in the examples may also be used for manufacturing so-called MNOS memory elements, the
`letters M, N, O, and S denoting metal for the gate electrode (poly in the present case),
`nitride, oxide, and semiconductor material, respectively. In such elements, as is known,
`information is stored in the form of electric charge at the boundary surface between the
`
`15
`
`nitride and the oxide. In a further modification of the embodiments described, the nitride
`layer 1b is not used. Furthermore, the invention may also be applied outside the field of
`integrated circuits, for example, if conductors are to be provided close together on a glass
`
`ry
`=
`“2
`
`*
`7
`
`20
`
`substrate or on a PCB.
`
`+ emer aanete> he
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`PHN 16.387
`
`Claims
`
`7
`
`30.10.1997
`
`[
`
`|
`
`1.
`A method\of manufacturing an electronic device whereby a conductive
`
`layer is provided on an electritally insulating substrate, from which layer a conductor pattern
`is formed by means of a mask\comprising a dielectric layer in which said pattern is defined
`by openings which were formed\in the dielectric layer by meansoflithography, which
`dielectric layerat the areas of thd windowsto be formed is provided with auxiliary windows
`having dimensions which are greater, at least in one direction, than the dimensions of the
`
`itional dielectric layer is provided which is etched
`windowsto be formed, whereupon
`that of the additional layer spacers remain behind
`back anisotropically without a mask such
`
`on side walls of the auxiliary windows, characterized in that the auxiliary windows are
`provided through only part of the thickness of the dielectric layer, and in that etching of the
`
`dielectric layer is continued, after the
`isotropic etching-back of the additional layer, until
`the dielectric layer has been locally removed throughoutits entire thickness at the areas of
`the auxiliary windows, whereupon the conductor pattern is formed in the conductive layer
`
`through the windowsthus formed in the dielectric layer.
`
`5
`
`te
`
`= 10
`te
`;
`
`
`
`is provided as a dual layer
`
`a layer comprising silicon.
`
`comprising a sub-layer formed bya silicon nitride layer and a
`
`A mdthod as claimed in claim 1, characterized in that the conductive layer
`
`A metliiod as claimed in claim 2, characterized in that the dielectric layer
`
`sub-layer of silicon oxide which is separated from the conductive layer by the nitride layer.
`
`sub-layer is provided to a thickness which is greater than the thickness of the silicon oxide
`
`layer which forms said mask, Whereuponsaid layer is provided with auxiliary windows
`the silicon oxide layer at the areas of the windowsto be
`which extend over only part of
`layer also comprising silicon oxide is provided.
`formed, whereupon the additiondl
`claim
`claimed inLenyone-ofthe-elaims-2-to-4; characterized in
`5.
`A method as
`that, after the windows have been formed in the dielectric layer, corresponding windowsare
`
`4,
`
`20
`
`A 25
`
`A method
`
`claimed in claim 3, characterized in that the silicon oxide
`
`
`
`formed in the layer masking against oxidation, so that portions of the conductive layer
`
`become exposed at the areas of the Windows, whereupon the conductor pattern is formed in
`the conductive layer in that the exposed
`portions of the conductive layer are oxidized
`
`
`
`aet
`
`nere
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`HN 16.387
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`Fogamgs pA YeaPNNN SPCROR
`
`
`
`ghout tn entire thickness.
`
`8
`
`30.10.1997
`
`A method as claimed in claim 5, characterized in that the oxidation is
`carried out in an oxidizing environment containing water vapor.
`
`claim
`A method as claimed inany-ene-ofthe-elnims-2-40-6; characterized in that
`ilicon layer is proved on a nitride layer, called second nitride layer hereinafter, which
`
`
`
`is formed on the substrate before the conductive layer and the nitride layer mentioned first
`
`are provided.
`claim 7
`
`8. A methodaXclaimed in,any-ene-er-severat-of-the-preeedingclaims,
`
`characterized in that the substrata
`is formed by an electrically insulating layer which is
`|
`
`rovided on a surface ofasilicon ody. fo
`
`iA
`A method as claimed in claim 2characterized in that the conductor
`
`pattern is provided in the form of a number of conductor tracks whicharesituated next to
`one another, which extend mutually parallel over the electrically insulating layer, and which
`in co-operation with the subjacent silicon body constitute gate electrodes of a charge coupled
`‘us
`device.
`c6 15
`claim HA)
`
`
`
`
`~y 5gny-one-of\\rs A method as claimed inthe-clamis2109, characterized in that
`u
`a polycrystalline silicon layer with a thickness of at most 0.1 ym is used as the conductive
`layer.
`
`
`
`sino seereeNE,
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`PHN 16.387
`
`oa°o
`
`oSsd
`
`9
`
`"30.10.1997
`
`O
`
`ABSTRACT OF THE prsclosuRe
`
`It may be necessary to provide conductors at very small distances from
`
`one another when electronic circuits, for example integrated circuits, are manufactured on an
`
`insulating substrate. A multilayer wiring system is often used in that case. The invention
`renders it possible to make very small inter-electrode gaps in a single conductor layer. To
`achieve this, the conductor layer is covered with a comparatively thick dielectric layer 4, 5 in
`
`5
`
`which windows 8 are formed which extend over only part of the dielectric layer. Then an
`
`auxiliary layer 9 is provided which has depressions at the areas of the windows 8. Windows
`11 are formed in the dielectric layer by anisotropic etching-back with dimensions which are
`substantially smaller than the dimensions of the original windows 8. The windows 11 may be
`used as etching windowsor oxidation windowsfor the subsequent formation of the definitive
`
`conductor pattern.
`
`oS
`=
`
`
`
`
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`DECLARAT ON and POWER OF ATTCRNEY
`
`ATTORNEY'S DOCKET NO.:
`PHN 16.387
`
`As a below named inventor, I hereby declare that:
`Myresidence,
`post office address and citizenship are as stated below next to my name.
`I believe I am the original, first and sole inventor (if only one name is listed below) or an original, first joint inventor(if
`plural names are listed below) of the subject matter which is claimed and for which a patent is sought on the invention entitled
`"Method of manufacturing an electronic device"
`the specification of which (check one)
`C2
`is attached hereto.
`ee
`( was filed on
`as Application Serial No.
`and was amended on
`(if applicable),
`hereby state that I have reviewed and understand the contents of the above-identified specification, including the claims,
`as amended by the amendment(s) referred to above.
`I acknowledge the duty to disclose information which is material to the examination ofthis application in accordance with
`Title 37, Code of Federal Regulations, §1.56(a).
`I hereby claim foreign priority benefits under Title 35, United States Code, § 119 of any foreign application(s) for patent
`or inventor’s certificate listed below and have also identified below any foreign application for patent or inventor’s certificate
`having a filing date before that of the application on which priority
`is claimed:
`RIOR FOREIGN APPLICATION(S
`
`COUNTRY
`
`APP.NUMBER
`
`DATEOF FILING
`
`PRIORITY
`
`(DATE,MONTH, YEAR) Ge UNDER 35
`
`97201585.3
`
`29 May 1997
`
`
`
`
`
`
`
`
`
`
`
`Code, §120 of any
`y claim the benefit under
`litle
`35, United
`States
`Unit
`tates application
`isted below and,
`insofar as the subject matter of each of the claims ofthis application is not disclosed in the prior United States application in the
`mamher provided by the first paragraph of Title 35 United States Code, §112, I acknowledge the duty to disclose material
`information as defined in Title 37,
`Code of Federal Regulations, §1,56(a) which occurred between the filing date of the prior
`application and the national or PCT international filing date of this
`application:
`a3
`pa
`PRIOR UNITED STA
`PPLICATION(S
`
`
`
`S.C. 1
`
`
`
`
`
`Jack E. Haken, Reg
`
`.
`
`No,
`
`(name and jclephone No.)
`(914) 332-022.
`
` 2 hereby declare that all statements made y g hat all statements made on
`
`
`
`
`
`
`
`
`information and belief are believed to be true; and further that these statements were made with the knowledge that willful false
`statéments and the like so made are punishable by fine or imprisonment, or both, under Section 1001 ofTitle 18 of the United
`States Code and that such willful fal