US 6,512,353 B2
`(10) Patent N0.:
`(12) United States Patent
`Sanzo et al.
`(45) Date of Patent:
`Jan. 28, 2003
`
`
`USOO6512353B2
`
`(54) SYNCHRONIZED, RIPPLE INDEPENDENT
`WINDOW COMPARATOR FOR SWITCH-
`MODE POWER CONVERTERS
`
`(75)
`
`Inventors: Christopher J. Sanzo, Providence, RI
`(US); Claudio Tuozzolo, Johnston, RI
`(US)
`
`(73) Assignee: Sipex Corporation, Billerica, MA (US)
`
`( * ) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(1)) by 0 days.
`
`(21) Appl. N0.: 09/879,427
`.
`(22)
`Filed:
`Jun. 12, 2001
`(65)
`Pr10r Publlcatlon Data
`US 2002/0039018 A1 A r. 4, 2002
`p
`Related US. Application Data
`Provisional application No. 60/217,949, filed on Jul. 13,
`2000,
`
`(60)
`
`7
`
`.................................................. G051? 1/40
`Int. Cl.
`(51)
`323/284’ 3‘3/287
`(52) U_'S' Cl'
`(58) Fleld of Search ................................. 323/284, 207,
`323/271 285, 222, 266, 281; 363/34’ 89:
`21-01) 37; 327/266) 278) 393
`
`(56)
`
`References Clted
`U.S. PATENT DOCUMENTS
`
`9/1987 Grunsch ~~~~~~~~~~~~~~~~~~~~~ 323/285
`47694240 A *
`4>779>037 A * 10/1988 LOCHSCIO
`323/275
`
`5,363,288 A * 11/1994 Castell et al.
`..
`...... 363/59
`.................. 363/34
`5,465,011 A * 11/1995 Miller et al.
`5,479,090 A * 12/1995 Schultz ....................... 323/284
`5,490,055 A *
`2/1996 Boylan et al.
`................ 363/41
`
`5,568,041 A * 10/1996 Hesterman .................. 323/207
`5,684,686 A * 11/1997 Reddy .........
`363/97
`
`.....
`.. 327/393
`5,955,910 A *
`9/1999 Levin et a1.
`11/2000 AlNahas et al.
`.............. 327/65
`6,147,517 A
`
`OTHER PUBLICATIONS
`
`Linear Technology. “LTC1530 High Power Synchronous
`Switching Regulator Controller,” 1998, pp. 1—24. No Date.
`National Semiconductor Corporation. “AN—1146 Designing
`a Multi—phase Asynchronous Buck Regulator Using the
`LM2639”, Mar. 2000, pp. 1—5.
`
`* cited by examiner
`
`Primary Examiner—Rajnikant B. Patel
`74 Altorne 3A em, or Firm—Testa, Hurwitz & Thibeault,
`(Lu),
`I
`g
`ABSTRACT
`(57)
`.
`.
`.
`,
`.
`This invention synchronizes the control Signals generated by
`the out-of-range detection circuits with a predefined event.
`In one aspect, the invention relates to a method 0f control-
`lin a switchin re
`lator to re ulate an out ut volta e. The
`ghd'ldg gu"
`fig bl'pldg d
`met 0 incu es receivmg a
`rst ena e s1gna an asecon
`enable signal, comparing a feedback voltage representative
`of the output voltage to a first reference voltage and gener-
`ating a first limit signal in response thereto and generating,
`in response to the first enable signal, a close switch com-
`mand if the first limit signal indicates that the feedback
`voltage is less than the first reference voltage. The method
`further includes comparing the feedback voltage to a second
`reference voltage and generating a second limit signal in
`response thereto and generating, in response to the second
`enable signal, an open switch command if the second limit
`signal indicates that the feedback voltage is greater than the
`second reference voltage
`'
`
`37 Claims, 17 Drawing Sheets
`
`'— ____________
`
`
`
`100
`
`'
`
`LOW LIMIT MODULE fl
`
`
`
`
`
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`OUTPUT
`
`LOGIC
`MODULE
`PWM MODULE m
`
`
`
`172
`121
`
`FEEDBACK
`HIGH LIMIT MODULE fl
`MODULE
`
`
`g
`
`
`1
`
`APPLE 1027
`
`APPLE 1027
`
`1
`
`

`

`US. Patent
`
`Jan. 28, 2003
`
`Sheet 1 0f 17
`
`US 6,512,353 B2
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`US. Patent
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`Jan. 28, 2003
`
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`US. Patent
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`Jan. 28, 2003
`
`Sheet 6 0f 17
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`US 6,512,353 B2
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`US. Patent
`
`Jan. 28, 2003
`
`Sheet 7 0f 17
`
`US 6,512,353 B2
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`FIG. FIG.
`7A
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`

`US. Patent
`
`Jan. 28, 2003
`
`Sheet 8 0f 17
`
`US 6,512,353 B2
`
`CONTINUOUS/
`
`DISCONTINUOUS
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`PROGRAM
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`US. Patent
`
`Jan. 28, 2003
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`US. Patent
`
`Jan. 28, 2003
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`Sheet 10 0f 17
`
`US 6,512,353 B2
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`US. Patent
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`Jan. 28, 2003
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`Sheet 11 0f 17
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`US 6,512,353 B2
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`Jan. 28, 2003
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`US 6,512,353 B2
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`US. Patent
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`Jan. 28, 2003
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`US 6,512,353 B2
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`US. Patent
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`Jan. 28, 2003
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`Sheet 17 0f 17
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`US 6,512,353 B2
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`

`US 6,512,353 B2
`
`1
`SYNCHRONIZED, RIPPLE INDEPENDENT
`WINDOW COMPARATOR FOR SWITCH-
`MODE POWER CONVERTERS
`
`CROSS-REFERENCE TO RELATED
`APPLICATIONS
`
`This application claims priority to US. provisional appli-
`cation Ser. No. 60/217,949, filed Jul. 13, 2000.
`
`FIELD OF THE INVENTION
`
`This invention relates generally to the field of regulated
`power sources and more specifically,
`to a method and
`apparatus for improving the response of switching regulators
`to load transients.
`
`BACKGROUND OF THE INVENTION
`
`FIG. 1 depicts, at a high level, a system 10 known to the
`prior art for controlling a switching regulator to regulate an
`output voltage. The system includes a PWM module 14, a
`first comparator 18, a second comparator 22, a first logic
`element 26 and a second logic element 30. The output of the
`second logic element 30 controls a switch 34 of a switching
`regulator. The PWM module 14 generates a pulse width
`modulated command signal to control the switch 34. When-
`ever the first comparator 18 detects that the output voltage
`38 goes out of range (i.e., decreases below a first predeter—
`mined acceptable level), the first comparator 18, via logic
`element 30, rapidly overrides the control signal generated by
`the PWM module 14 and controls the switch 34 until the out
`
`of range condition ends. Similarly, whenever the second
`comparator 22 detects that the output voltage 38 goes out of
`range (i.e., increases above a second predetermined accept—
`able level), the second comparator 22, via logic elements 26
`and 30, rapidly overrides the control signal generated by the
`PWM module 14 and controls the switch 34 until the out of
`
`range condition ends. This substantially immediate exit from
`the PWM control can lead to undesirable effects in the
`regulated output voltage.
`
`SUMMARY OF THE INVENTION
`
`It is an object of this invention to synchronize the action
`taken by the out-of—range detection circuits with one or more
`predefined events. In one aspect, the invention relates to a
`method of controlling a switching regulator to regulate an
`output voltage. The method includes receiving a first enable
`signal and a second enable signal, comparing a feedback
`voltage representative of the output voltage to a first refer-
`ence voltage and generating a first limit signal in response
`thereto, and generating, in response to the first enable signal,
`a close switch command if the first limit signal indicates that
`the feedback voltage is less than the first reference voltage.
`The method further includes comparing the feedback volt-
`age to a second reference voltage and generating a second
`limit signal in response thereto, and generating, in response
`to the second enable signal, an open switch command if the
`second limit signal indicates that the feedback voltage is
`greater than the second reference voltage.
`In one embodiment, the method includes comparing the
`feedback voltage to a third reference voltage and generating
`a threshold signal in response thereto, and inhibiting the
`close switch command if the threshold signal indicates that
`the feedback voltage is greater than the third reference
`voltage. In another embodiment, the method includes gen-
`erating a switch control signal. In another embodiment, the
`step of generating the switch control signal further includes
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`receiving a clock signal, asserting a first state of the switch
`control signal in response to the clock signal, and comparing
`the feedback voltage to a fourth reference voltage and
`generating a difference signal in response thereto. The step
`of generating the switch control signal also includes corri-
`paring the difference signal and a timed ramp signal and
`asserting a second state of the switch control signal
`in
`response to the comparison of the difference signal and the
`timed ramp signal.
`In another embodiment,
`the method
`includes generating the first enable signal in response to the
`switch control signal. In another embodiment, the method
`includes generating the second enable signal in response to
`the clock signal.
`In another embodiment, the method includes receiving a
`switch type signal having a first state and a second state. In
`another embodiment, the method includes converting the
`switch control signal into a drive signal compatible with a
`p-channel switching device in response to the first state of
`the switch type signal and converting the switch control
`signal
`into a drive signal compatible with a n-channel
`switching device in response to the second state of the
`switch type signal.
`In another embodiment,
`the method
`includes using the switch control signal to control a syn-
`chronous switching regulator. In another embodiment, the
`method includes generating the first enable signal
`in
`response to a logical combination of a plurality of regulator
`signals. In another embodiment, the method includes gen-
`erating the second enable signal in response to a logical
`combination of the plurality of regulator signals.
`In another aspect, the invention relates to a method of
`controlling a switching regulator
`to regulate an output
`voltage. The method includes receiving an enable signal,
`comparing a feedback voltage representative of the output
`voltage to a first reference voltage and generating a limit
`signal in response thereto, and generating, in response to the
`enable signal, a close switch command if the limit signal
`indicates that
`the feedback voltage is less than the first
`reference voltage. In one embodiment, the method includes
`comparing the feedback voltage to a second reference volt—
`age and generating a threshold signal in response thereto,
`and inhibiting the close switch command if the threshold
`signal indicates that the feedback voltage is greater than the
`second reference voltage.
`In another embodiment, the method includes generating a
`switch control signal. In another embodiment, the step of
`generating the switch control signal also includes receiving
`a clock signal, asserting a first state of the switch control
`signal in response to the clock signal, and comparing the
`feedback voltage to a third reference voltage and generating
`a difference signal in response thereto. The method further
`includes comparing the difference signal and a timed ramp
`signal and asserting a second state of the switch control
`signal in response to the comparison of the difference signal
`and the timed ramp signal.
`In another embodiment,
`the
`method includes generating the enable signal in response to
`the switch control signal.
`In another embodiment, the method includes receiving a
`switch type signal having a first state and a second state. In
`another embodiment, the method includes converting the
`switch control signal into a drive signal compatible with a
`p-channel switching device in response to the first state of
`the switch type signal and converting the switch control
`signal
`into a drive signal compatible with a n-channel
`switching device in response to the second state of the
`switch type signal.
`In another embodiment,
`the method
`includes using the switch control signal to control a syn-
`chronous switching regulator. In another embodiment, the
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`US 6,512,353 B2
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`3
`method includes generating the enable signal in response to
`a logical combination of a plurality of regulator signals.
`In another aspect the invention relates to a method of
`controlling a switching regulator to regulate an output
`voltage. The method includes receiving an enable signal,
`comparing a feedback voltage representative of the output
`voltage to a first reference voltage and generating a limit
`signal in response thereto, and generating, in response to the
`enable signal, an open switch command if the limit signal
`indicates that the feedback voltage is greater than the first
`reference voltage. In one embodiment, the method includes
`generating a switch control signal. The step of generating the
`switch control signal
`includes receiving a clock signal,
`asserting a first state of the switch control signal in response
`to the clock signal, and comparing the feedback voltage to
`a second reference voltage and generating a difference signal
`in response thereto. The step of generating the switch control
`signal further includes comparing the difference signal and
`a timed ramp signal and asserting a second state of the
`switch control signal in response to the comparison of the
`difference signal and the timed ramp signal.
`In another embodiment, the method includes generating
`the enable signal in response to the clock signal. In another
`embodiment, the method includes receiving a switch type
`signal having a first state and a second state. In another
`embodiment,
`the method includes converting the switch
`control signal
`into a drive signal compatible with a
`p-channel switching device in response to the first state of
`the switch type signal and converting the switch control
`signal
`into a drive signal compatible with a n-channel
`switching device in response to the second state of the
`switch type signal.
`In another embodiment,
`the method
`includes using the switch control signal to control a syri-
`chronous switching regulator. In another embodiment, the
`method includes comprising generating the enable signal in
`response to a logical combination of a plurality of regulator
`signals.
`In another aspect, the invention relates to a system for
`controlling a switching regulator to regulate an output
`voltage. The system includes a main control module, a high
`limit module, a low limit module and an output
`logic
`module. The main control module includes a main control
`module output terminal, a main control module input ter-
`minal configured to receive a feedback voltage representa-
`tive of the regulated output voltage and a main control
`module clock terminal configured to receive a master clock
`signal. The main control module further includes a main
`control module ramp input terminal configured to receive a
`timed ramp signal and a reference input terminal configured
`to receive a first reference signal representative of a regu-
`lation value of the feedback voltage. The high limit module
`includes an output terminal, a first input terminal in com-
`munication with the main control module input terminal, a
`reference input
`terminal configured to receive a second
`reference signal representative of a high limit and a timing
`input
`terminal in communication with the main control
`module clock terminal. The low limit module includes an
`
`output terminal, an input terminal in communication with
`the main control module input terminal, a first reference
`input terminal configured to receive a third reference signal
`representative of a low limit and a timing input terminal in
`communication with the main control module output termi-
`nal. The output logic module includes a first input terminal
`in communication with the main control module output
`terminal, a second input terminal in communication with the
`high limit module output terminal, a third input terminal in
`communication with the low limit module output terminal,
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`and an output terminal for providing a switch command
`signal to control the switching regulator.
`In one embodiment, the low limit module includes a first
`comparator and a flip-flop. The first comparator includes a
`first input terminal in communication with the first reference
`input
`terminal of the low limit module, a second input
`terminal in communication with the input terminal of the
`low limit module and an output
`terminal. The flip-flop
`includes an input terminal in communication with the output
`terminal of the first comparator, a timing input terminal in
`communication with the timing input terminal of the low
`limit module, a reset terminal and an output terminal in
`communication with the output terminal of the low limit
`module.
`In another embodiment,
`the low limit module
`includes a second reference input terminal configured to
`receive a fourth reference signal representative of a thresh-
`old limit. In another embodiment,
`the low limit module
`includes a second comparator. The second comparator
`includes a first input terminal in communication with the
`second reference input terminal of the low limit module, a
`second input terminal in communication with the input
`terminal of the low limit module and an output terminal in
`communication with the reset terminal of the flip-flop.
`In another embodiment, the high limit module includes a
`comparator and a flip-flop. The comparator includes an
`output terminal, a first input terminal in communication with
`the reference input terminal of the high limit module and a
`second input terminal in communication with the first input
`terminal of the high limit module. The flip—flop includes an
`input terminal in communication with the output terminal of
`the comparator, a timing input terminal in communication
`with the timing input terminal of the high limit module and
`an output terminal in communication with the output termi-
`nal of the high limit module. In another embodiment, the
`output logic module includes an AND gate and an OR gate.
`The AND gate includes an output terminal, a first input
`terminal in communication with the first input terminal of
`the output logic module and an inverting input terminal in
`communication with the second input terminal of the output
`logic module. The OR gate includes a first input in com-
`munication with the third input terminal of the output logic
`module, a second input terminal in communication with the
`output terminal of the AND gate and an output terminal in
`communication with the output terminal of the output logic
`module.
`
`In another embodiment, the main control module includes
`an amplifier, a compensation network, a comparator and a
`flip-flop. The amplifier includes an output terminal, a first
`input
`terminal
`in communication with the main control
`module input
`terminal and a second input
`terminal
`in
`communication with the reference input terminal of the main
`control module. The compensation network includes a first
`terminal in communication with the output terminal of the
`amplifier and a second terminal in communication with a
`voltage node. The comparator includes an output terminal, a
`first input terminal in communication with the output ter-
`minal of the amplifier and a second input
`terminal
`in
`communication with the main control module ramp input
`terminal. The flip-flop includes a set terminal in communi-
`cation with the main control module clock terminal, a reset
`terminal in communication with the output terminal of the
`comparator and an output terminal in communication with
`the main control module output
`terminal.
`In another
`embodiment, the system includes a capacitive element elec-
`trically connected between the first and second terminals of
`the compensation network.
`In another embodiment,
`the
`system includes a filter in communication with the first input
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`US 6,512,353 B2
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`5
`terminal of the high limit module. In another embodiment,
`the system includes a filter in communication with the first
`input terminal of the low limit module.
`In another aspect, the invention relates to a system for
`controlling a switching regulator to regulate an output
`voltage. The system includes a means for receiving a first
`enable signal and a second enable signal, a means for
`comparing a feedback voltagc representative of the output
`voltage to a first reference voltage and generating a first limit
`signal in response thereto, and a means for generating, in
`response to the first enable signal, a close switch command
`if the first limit signal indicates that the feedback voltage is
`less than the first reference voltage. The system fiirther
`includes a means for comparing the feedback voltage to a
`second reference voltage and generating a second limit
`signal in response thereto, and a means for generating, in
`response to the second enable signal, an open switch com-
`mand if the second limit signal indicates that the feedback
`voltage is greater than the second reference voltage. In one
`embodiment, the system includes a means for comparing the
`feedback voltage to a third reference voltage and generating
`a threshold signal in response thereto, and a means for
`inhibiting the close switch command if the threshold signal
`indicates that the feedback voltage is greater than the third
`reference voltage.
`In another aspect, the invention relates to a system of
`controlling a switching regulator to regulate an output
`voltage. The system includes a means for receiving an
`enable signal, a means for comparing a feedback voltage
`representative of the output voltage to a first reference
`voltage and generating a limit signal in response thereto, and
`a means for generating, in response to the enable signal, a
`close switch command if the limit signal indicates that the
`feedback voltage is less than the first reference voltage. In
`one embodiment, the system includes a means for compar-
`ing the feedback voltage to a second reference voltage and
`generating a threshold signal
`in response thereto, and a
`means for inhibiting the close switch command if the
`threshold signal indicates that the feedback voltage is greater
`than the second reference voltage,
`In another aspect, the invention relates to a system of
`controlling a switching regulator to regulate an output
`voltage. The system includes a means for receiving an
`enable signal, a means for comparing a feedback voltage
`representative of the output voltage to a reference voltage
`and generating a limit signal
`in response thereto, and a
`means for generating, in response to the enable signal, an
`open switch command if the limit signal indicates that the
`feedback voltage is greater than the reference voltage.
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`Other objects, features and advantages will occur to those
`skilled in the art from the following description of a pre-
`ferred embodiment and the accompanying drawings,
`in
`which:
`
`FIG. 1 is a high-level block diagram of an embodiment of
`a regulating circuit constructed in accordance with the prior
`art;
`FIG. 2 is a high-level block diagram of one embodiment
`of a regulating circuit constructed in accordance with the
`invention;
`FIG. 3 is a more detailed block diagram of the embodi—
`ment of the circuit shown in FIG. 2;
`FIG. 4 is a flow diagram of one embodiment in accor-
`dance with the invention;
`FIG. 5 is a flow diagram of another embodiment of a
`method of controlling a switching regulator performed in
`accordance with the invention;
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`FIG. 6 is a timing diagram of electrical signals of one
`embodiment in accordance with the invention;
`FIG. 7 is a detailed block diagram of an embodiment of
`an integrated circuit
`to control a switching regulator in
`accordance with the invention; and
`FIG. 8 is a detailed block diagram of another embodiment
`of an integrated circuit to control a switching regulator in
`accordance with the invention.
`
`DETAILED DESCRIPTION OF PREFERRED
`EMBODIMENTS
`
`FIG. 2 depicts, at a high level, an embodiment of a system
`100 for controlling a switching regulator 101 to regulate an
`output voltage 121 constructed in accordance with the
`invention. The system 100 includes a PWM module 104, a
`high limit module 108, a low limit module 112 and an output
`logic module 116. The output terminal 128 of the output
`logic module 116 drives a switch 120 of a switching regu-
`lator 101 to regulate an output voltage 121 by using a
`feedback voltage 124, which is representative of the output
`voltage 121.
`In one embodiment,
`the system 100 also
`includes an optional feedback module 122. The feedback
`module 122 conditions the output voltage 121 as necessary,
`in accordance with the design requirements of the other
`modules 104, 108 and 112, as understood by one skilled in
`the art. For example, the feedback module 122 can include
`a buffer for load isolation, a resister divider for voltage
`shifting, and the like. In another embodiment, there are three
`feedback modules 122', 122", 122'" (not shown), one cor—
`responding to each module 104, 108 and 112, respectively,
`and designed for the needs of the particular corresponding
`module. In another embodiment, the feedback voltage 124 is
`the output voltage 121 directly.
`The main control loop to regulate the output voltage 121
`is performed by the PWM module 104. The high limit
`module 108 takes control of the switch 120 if the feedback
`
`voltage 124 exceeds a maximum voltage limit determined
`by Vrefl 132. The low limit module 112 takes control of the
`switch 120 if the feedback voltage 124 falls below a mini-
`mum voltage limit determined by Vref2 136. In both cases,
`the control of the switch 120 by modules 108 and 112 is
`synchronized with the control of the switch 120 by the PWM
`module 104. The synchronization is performed by only
`allowing the modules 108 and 112 to control the switch 120
`at certain predefined events, for example transitions from
`one state to another state of certain signals received by or
`generated from the PWM module 104. Preferably synchro-
`nization occurs just prior to a switch transition (e.g., switch
`opening or switch closing) so that the high limit module 108
`and the low limit module 112 avoid noise from the switch
`
`transition. Switching noise can introduce errors in the deter-
`mination of whether the feedback voltage 124 is within the
`limits. Synchronization just prior to a switch transition also
`prevents spurious switching of the switch 120.
`The PWM module 104 includes a PWM output terminal
`140; a PWM input terminal 144 electrically connected to the
`representative feedback voltage node 124; and a PWM clock
`terminal 148 configured to receive a master clock signal 152.
`The PWM module 104 also includes a PWM ramp input
`terminal 156 configured to receive a timed ramp signal 160
`and a reference input terminal 164 configured to receive a
`reference voltage Vref3 168. Vref3 168 is a value corre-
`sponding to the desired value for the feedback voltage 124.
`Although this embodiment illustrates a PWM module 104 as
`the main control module for performing the main loop
`control for the switching regulator 101, other embodiments
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`US 6,512,353 B2
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`7
`can employ different control loop algorithms. For example,
`the system 100 can regulate the output voltage 121 using
`current mode, ripple, hysteretic or multiphase algorithms, or
`an amalgam of these types of algorithms known in the art.
`In another embodiment, the system operates without any
`main control loop, and simply regulates about the limits
`determined by the high limit module 108 and the low limit
`module 112.
`
`The high limit module 108 includes an output terminal
`172; a first input terminal 176 electrically connected to the
`feedback voltage node 124; and a timing input terminal 184
`configured to receive the master clock signal 152. The high
`limit module 108 also includes a reference input terminal
`180 configured to receive the reference voltage Vrefl 132.
`Vrefl 132 is the value of the high (maximum) regulation
`limit for the feedback voltage 124.
`The low limit module 112 includes an output terminal
`188; an input terminal 192 electrically connected to the
`feedback voltage node 124; and a timing input terminal 196
`electrically connected with the PWM output terminal 140.
`The low limit module 112 also includes a first reference
`
`input terminal 200 configured to receive the reference volt-
`age VrefZ 136. Vref2 136 is the value of a low (minimum)
`regulation limit for the feedback voltage 124.
`In one embodiment, the low limit module 112 further
`comprises a second reference input terminal 208 configured
`to receive a reference volta