Trials@uspto.gov
`571-272-7822
`
`Paper 26
`Date: January 3, 2020
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`APPLE INC.,
`Petitioner,
`
`v.
`
`QUALCOMM INCORPORATED,
`Patent Owner.
`____________
`
`IPR2018-01315
`IPR2018-01316
`Patent 8,063,674 B2
`____________
`
`Before TREVOR M. JEFFERSON, DANIEL J. GALLIGAN, and
`SCOTT B. HOWARD, Administrative Patent Judges.
`
`HOWARD, Administrative Patent Judge.
`
`
`
`
`JUDGMENT
`Final Written Decision
`Determining All Challenged Claims Unpatentable
`35 U.S.C. § 318(a)
`
`
`
`

`

`IPR2018-01315, IPR2018-01316
`Patent 8,063,674 B2
`
`
`INTRODUCTION
`
`In these inter partes reviews, instituted pursuant to 35 U.S.C. § 314,
`
`Apple Inc. (“Petitioner”) challenges claims 1, 2, 5–9, 12, 13, and 16–22
`
`(“the challenged claims”) of U.S. Patent No. 8,063,674 B2 (Ex. 1001, “the
`
`’674 patent”), owned by Qualcomm Incorporated (“Patent Owner”).
`
`As explained in detail below, the references applied against the
`
`challenged claims are identical in each of the cases. A joint hearing was
`
`held for these cases. The parties rely on the same declarants submitting
`
`identical declarations in each case for testimonial evidence. Under these
`
`circumstances, we determine that a combined Final Decision will promote a
`
`just, speedy, and inexpensive resolution of these proceedings.
`
`The Board has jurisdiction under 35 U.S.C. § 6(b). This Final Written
`
`Decision issues pursuant to 35 U.S.C. § 318(a). For the reasons that follow,
`
`we determine that Petitioner has shown by a preponderance of the evidence
`
`that the challenged claims are unpatentable.
`
`A.
`
`IPR2018-01315 Procedural History
`
`Petitioner filed a Petition to institute an inter partes review of claims
`
`1, 2, and 5–7 of the ’674 patent pursuant to 35 U.S.C. §§ 311–319. Paper 21
`
`(“Petition” or “Pet.”). Patent Owner filed a Preliminary Response. Paper 6.
`
`We instituted an inter partes review of claims 1, 2, and 5–7 on all grounds of
`
`unpatentability alleged in the Petition. Paper 7 (“Institution Decision” or
`
`“Inst. Dec.”).
`
`
`1 Unless otherwise noted, all citations are to IPR2018-01315. We note that
`identical exhibits were filed in each of the proceedings.
`
`2
`
`

`

`IPR2018-01315, IPR2018-01316
`Patent 8,063,674 B2
`
`
`After institution of trial, Patent Owner filed a Response (Paper 12,
`
`“PO Resp.”), Petitioner filed a Reply (Paper 16, “Pet. Reply”), and Patent
`
`Owner filed a Sur-reply (Paper 19, “PO Sur-reply”).
`
`A joint hearing for IPR2018-01315 and IPR2018-01316 was held on
`
`October 11, 2019. Paper 25 (“Tr.”).
`
`B.
`
`IPR2018-01316 Procedural History
`
`Petitioner filed a Petition to institute an inter partes review of claims
`
`8, 9, 12, 13, and 16–22 of the ’674 patent pursuant to 35 U.S.C. §§ 311–319.
`
`IPR2018-01316, Paper 2 (“1316 Pet.”). Patent Owner filed a Patent Owner
`
`Preliminary Response. IPR2018-01316, Paper 6. We instituted an inter
`
`partes review of claims 8, 9, 12, 13, and 16–22 on all grounds of
`
`unpatentability alleged in the Petition. IPR2018-01318, Paper 7 (“1316 Inst.
`
`Dec.”).
`
`After institution of trial, Patent Owner filed a Response (IPR2018-
`
`01316, Paper 12, “1316 PO Resp.”), Petitioner filed a Reply (IPR2018-
`
`01316, Paper 16, “1316 Pet. Reply”), and Patent Owner filed a Sur-reply
`
`(IPR2018-01316, Paper 19, “1316 PO Sur-reply”).
`
`A joint hearing for IPR2018-01315 and IPR2018-01316 was held on
`
`October 11, 2019. IPR2018-01316, Paper 25 (“Tr.”).
`
`C.
`
`Real Party in Interest
`
`Petitioner identified Apple, Inc. as the real party in interest. Pet. 64.
`
`Patent Owner identified Qualcomm Incorporated as the real party in
`
`interest. Patent Owner’s Mandatory Notices, Paper 3, 2; IPR2018-01315
`
`Patent Owner’s Mandatory Notices, Paper 3, 2.
`
`3
`
`

`

`IPR2018-01315, IPR2018-01316
`Patent 8,063,674 B2
`
`
`D.
`
`Related Proceedings
`
`The parties identified the following patent litigation proceedings in
`
`which the ’674 patent was asserted: In re Certain Mobile Electronic
`
`Devices and Radio Frequency and Processing Components Thereof (ITC
`
`Inv. No. 337-TA-1093) and Qualcomm Inc. v. Apple Inc., Case No. 3:17-cv-
`
`02398 (S.D. Cal.). Id. at 64–65; Patent Owner’s Mandatory Notices,
`
`Paper 3, 2.2
`
`E.
`
`The ’674 Patent
`
`The ’674 patent is titled “Multiple Supply-Voltage Power-Up/Down
`
`Detectors.” Ex. 1001, code (54). According to the ’674 patent, “many
`
`newer integrated circuit devices include dual power supplies: one lower-
`
`voltage power supply for the internally operating or core applications, and a
`
`second higher-voltage power supply for the I/O circuits and devices.” Id. at
`
`1:22–25.
`
`The ’674 patent further states that “[i]n order to facilitate
`
`communication between the core and I/O devices, level shifters are
`
`employed.” Id. at 1:28–29. “Because the I/O devices are connected to the
`
`core devices through level shifters, problems may occur when the core
`
`devices are powered-down.” Id. at 1:29–32. An example of such a problem
`
`described in the ’674 patent is how stray currents while the core is powering
`
`down can cause the level shifters to “send a signal to the I/O devices for
`
`transmission” resulting in the I/O devices “transmit[ting] the erroneous
`
`signal into the external environment.” Id. at 1:34–40.
`
`
`2 According to Petitioner, the district court proceeding and the ITC
`investigation have been dismissed. Petitioner’s Updated Mandatory Notices,
`Paper 15, 1.
`
`4
`
`

`

`IPR2018-01315, IPR2018-01316
`Patent 8,063,674 B2
`
`
`One prior art solution identified in the ’674 patent is the use of
`
`“power-up/down detectors to generate a power-on/off-control (POC) signal
`
`internally [which] instructs the I/O devices when the core devices are shut
`
`down.” Ex. 1001, 1:55–58. Figure 1 of the ’674 patent is reproduced below.
`
`Figure 1 “is a circuit diagram illustrating a conventional POC system for
`
`multiple supply voltage devices” which is identified as being prior art. Id. at
`
`
`
`4:18–19, Fig. 1.
`
`The ’674 patent identifies a number of issues associated with the
`
`Figure 1 design. For example, when I/O power supply 104 is on and core
`
`power supply 103 is off, powering on the core power supply results in “a
`
`period in which all three transistors within power up/down detector 100 are
`
`on,” resulting in a virtual short “to ground causing a significant amount of
`
`current to flow from I/O power supply 104 to ground.” Ex. 1001, 2:21–29.
`
`“This ‘glitch’ current consumes unnecessary power.” Id. at 2:29–30.
`
`Although the glitch current can be reduced by reducing the size of transistors
`
`M1-M3, such a reduction limits “the actual amount of current that can pass
`
`through the transistors” and reduces their switching speeds, which
`
`5
`
`

`

`IPR2018-01315, IPR2018-01316
`Patent 8,063,674 B2
`
`“translates into less sensitivity in detecting power-up/down of core supply
`
`voltage 103 or longer processing time for power-up/down events.” Id. at
`
`2:31–39; see also id. at 2:63–3:11.
`
`According to the ’674 patent, these problems can be solved by using
`
`“one or more feedback circuits coupled to the up/down detector” that “are
`
`configured to provide feedback signals to adjust a current capacity of said
`
`up/down detector.” Ex. 1001, 3:31–34. An example of such a feedback
`
`circuit is shown in Figure 4, reproduced below:
`
`Figure 4 “is a circuit diagram illustrating another POC network configured
`
`according to the teachings of the present disclosure.” Id. at 4:28–30. The
`
`’674 patent describes the operation of the feedback circuit in Figure 4 as
`
`
`
`follows:
`
`The feedback network 310 comprises a transistor M8
`connected in parallel to the transistor M4. The transistor M8 is
`also configured as a p-type transistor, such that when the
`feedback signal from the inverting amplifier 400 is high, the
`transistor M8 is switched off, and when the feedback signal is
`low, the transistor M8 is switched on. Thus, when the Vcore 301
`is off, producing a high detection signal, the inverting amplifier
`
`6
`
`

`

`IPR2018-01315, IPR2018-01316
`Patent 8,063,674 B2
`
`
`400 inverts that signal to a logic low which causes the transistor
`M8 to switch on. As the Vcore 301 is powered-on, the detection
`signal changes to a logic low, which changes the feedback
`signal from the inverting amplifier 400 to a logic high, which,
`in turn, turns the transistor M8 off. While the transistor M8 is
`off, the power up/down detector 306 has a decreased current
`capacity, i.e., smaller current will flow through the transistor
`M8 because of the amplified low signal. The voltage level
`caused by the Vcore 301 on the gate terminals of M4 and M5
`could in some glitch or stray signal situations, cause leakage
`through M4 and M5. Because the feedback signal for the
`transistor M8 is received from the inverting amplifier 400,
`when the Vcore 301 powers-down, the feedback signal will
`switch quickly from a logic high to a logic low, which will then
`switch the transistor M8 on. Thus, in the circuit configuration
`depicted in FIG. 4, the power up/down detector 40 will detect
`the Vcore 301 powering down more quickly than the existing
`POC networks.
`
`Id. at 6:4–28.
`
`F.
`
`Illustrative Claim
`
`Petitioner challenges claims 1, 2, and 5–9, 12, 13, and 16–22 of the
`
`’674 patent. Pet. 1; 1316 Pet. 1. Claim 1 is independent, is illustrative of the
`
`subject matter of the challenged claims, and reads as follows:
`
`1.
`
`A multiple supply voltage device comprising:
`
`a core network operative at a first supply voltage; and
`
`a control network coupled to said core network wherein
`said control network is configured to transmit a control signal,
`said control network comprising: an up/down (up/down)
`detector configured to detect a power state of said core network;
`processing circuitry coupled to said up/down detector and
`configured to generate said control signal based on said power
`state;
`
`one or more feedback circuits coupled to said up/down
`detector, said one or more feedback circuits configured to
`
`7
`
`

`

`IPR2018-01315, IPR2018-01316
`Patent 8,063,674 B2
`
`
`provide feedback signals to adjust a current capacity of said
`up/down detector;
`
`at least one first transistor coupled to a second supply
`voltage, the at least one more first transistor being configured to
`switch on when said first supply voltage is powered down and
`to switch off when said first supply voltage is powered on;
`
`at least one second transistor coupled in series with the at
`least one first transistor and coupled to said first supply voltage,
`the at least one second transistor being configured to switch on
`when said first supply voltage is powered on and to switch off
`when said first supply voltage is powered down;
`
`at least one third transistor coupled in series between the
`at least one first transistor and the at least one second transistor.
`
`Ex. 1001, 8:44–9:3 (the ’674 patent).
`
`G.
`
`Prior Art and Asserted Grounds
`
`Petitioner asserts that claims 1, 2, and 5–9, 12, 13, and 16–22 are
`
`unpatentable on the following grounds:
`
`Claims Challenged
`1, 2, 5–9, 12, 13, 16–
`22
`
`35 U.S.C. §
`
`References/Basis
`
`103(a)3
`
`Steinacker,4 Doyle,5 and Park6
`
`
`3 The Leahy-Smith America Invents Act (“AIA”) included revisions to 35
`U.S.C. §§ 102, 103 that became effective on March 16, 2013. Because the
`’674 patent issued from an application filed before March 16, 2013, we
`apply the pre-AIA versions of the statutory bases for unpatentability.
`
`4 Steinacker, US 7,279,943 B2, issued Oct. 9, 2007 (Ex. 1005).
`
`5 Doyle, US 4,717,836, issued Jan. 5, 1988 (Ex. 1006).
`
`6 Park, J. C. & Mooney, V. J. (Nov. 2006). Sleepy Stack Leakage
`Reduction. IEEE Transactions on Very Large Scale Integration (VLSI)
`Systems, 14(11), 1250–1263 (Ex. 1007).
`
`8
`
`

`

`IPR2018-01315, IPR2018-01316
`Patent 8,063,674 B2
`
`
`Claims Challenged
`1, 2, 5, 6, 8, 9, 12, 13,
`17–21
`
`7, 16, 22
`
`35 U.S.C. §
`
`References/Basis
`
`103(a)
`
`103(a)
`
`AAPA,7 Majcherczak
`
`AAPA, Majcherczak,
`Matthews8
`
`A. Legal Principles
`
`ANALYSIS
`
`In Graham v. John Deere Co. of Kansas City, 383 U.S. 1 (1966), the
`
`Supreme Court set out a framework for assessing obviousness under
`
`35 U.S.C. § 103 that requires consideration of four factors: (1) the “level of
`
`ordinary skill in the pertinent art,” (2) the “scope and content of the prior
`
`art,” (3) the “differences between the prior art and the claims at issue,” and
`
`(4) “secondary considerations” of non-obviousness such as “commercial
`
`success, long-felt but unsolved needs, failure of others, etc.” Id. at 17–18.
`
`“While the sequence of these questions might be reordered in any particular
`
`case,” KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 407 (2007), the Federal
`
`Circuit has “repeatedly emphasized that an obviousness inquiry requires
`
`examination of all four Graham factors and that an obviousness
`
`determination can be made only after consideration of each factor.” Nike,
`
`Inc. v. Adidas AG, 812 F.3d 1326, 1335 (Fed. Cir. 2016), overruled on other
`
`grounds by Aqua Products, Inc. v. Matal, 872 F.3d 1290 (Fed. Cir. 2017) (en
`
`banc). We note that, with respect to the fourth Graham factor, the parties
`
`have not presented argument or evidence directed to secondary
`
`
`7 Petitioner identifies Figure 1 and the text at column 1, line 22 through
`column 2, line 39 of the ’674 patent as Applicant Admitted Prior Art. See
`Pet. 37, 43, 46.
`
`8 Matthews, US 6,646,844 B1, issued Nov. 11, 2003 (Ex. 1009).
`
`9
`
`

`

`IPR2018-01315, IPR2018-01316
`Patent 8,063,674 B2
`
`considerations of nonobviousness. The analysis below addresses the first
`
`three Graham factors.
`
`B.
`
`Level of Ordinary Skill in the Art
`
`The level of ordinary skill in the art is “a prism or lens” through which
`
`we view the prior art and the claimed invention. Okajima v. Bourdeau, 261
`
`F.3d 1350, 1355 (Fed. Cir. 2001). Factors pertinent to a determination of the
`
`“level of ordinary skill in the art include (1) educational level of the
`
`inventor; (2) type of problems encountered in the art; (3) prior art solutions
`
`to those problems; (4) rapidity with which innovations are made; (5)
`
`sophistication of the technology; and (6) educational level of workers active
`
`in the field.” Envtl. Designs, Ltd. v. Union Oil Co. of Cal., 713 F.2d 693,
`
`696–697 (Fed. Cir. 1983) (citing Orthopedic Equip. Co. v. All Orthopedic
`
`Appliances, Inc., 707 F.2d 1376, 1381–82 (Fed. Cir. 1983)). Not all such
`
`factors may be present in every case, and one or more of these or other
`
`factors may predominate in a particular case. Id. Moreover, “[t]hese factors
`
`are not exhaustive but are merely a guide to determining the level of
`
`ordinary skill in the art.” Daiichi Sankyo Co. Ltd, Inc. v. Apotex, Inc., 501
`
`F.3d 1254, 1256 (Fed. Cir. 2007).
`
`Dr. Horst testifies that a person having ordinary skill in the art would
`
`have had “at least an undergraduate degree in electrical engineering, or a
`
`related field, and three years of experience in circuit and system design.”
`
`Ex. 1003 ¶ 33. Additionally, Dr. Horst testifies that “a person of ordinary
`
`skill with less than the amount of experience noted above could have had a
`
`correspondingly greater amount of educational training such a graduate
`
`degree in a related field.” Id.
`
`10
`
`

`

`IPR2018-01315, IPR2018-01316
`Patent 8,063,674 B2
`
`
`In our Institution Decision, “we adopt[ed] Dr. Horst’s definition of the
`
`level of ordinary skill in the art, with the exception of the language ‘at least’
`
`. . . .” Inst. Dec. 13; 1316 Inst. Dec. 13. Patent Owner agrees with our
`
`formulation, see PO Resp. 9; 1316 PO Resp. 9, and Petitioner did not
`
`address it in its Reply. See generally Pet. Reply; 1316 Pet. Reply.
`
`Accordingly, we find on the record as a whole that a person of
`
`ordinary skill in the art would have an undergraduate degree in electrical
`
`engineering, or a related field, and three years of experience in circuit and
`
`system design. Additionally, a person of ordinary skill with less than the
`
`amount of experience noted above could have had a correspondingly greater
`
`amount of educational training such a graduate degree in a related field.
`
`C.
`
`Claim Construction
`
`In this inter partes review, we construe claim terms in an unexpired
`
`patent according to their broadest reasonable construction in light of the
`
`specification of the patent in which they appear. 37 C.F.R. § 42.100(b)
`
`(2018).9 “Under a broadest reasonable interpretation, words of the claim
`
`must be given their plain meaning, unless such meaning is inconsistent with
`
`the specification and prosecution history.” Trivascular, Inc. v. Samuels, 812
`
`F.3d 1056, 1062 (Fed. Cir. 2016). In addition, the Board may not “construe
`
`claims during [an inter partes review] so broadly that its constructions are
`
`unreasonable under general claim construction principles.” Microsoft Corp.
`
`
`9 We apply the district court claim construction standard to petitions filed on
`or after November 13, 2018. See Changes to the Claim Construction
`Standard for Interpreting Claims in Trial Proceedings Before the Patent
`Trial and Appeal Board, 83 Fed. Reg. 51340 (Oct. 11, 2018) (to be codified
`at 37 C.F.R. pt. 42). Because Petitioner filed its petitions before November
`13, 2018 (see Pet.; 1316 Pet.), we apply the BRI standard.
`
`11
`
`

`

`IPR2018-01315, IPR2018-01316
`Patent 8,063,674 B2
`
`v. Proxyconn, Inc., 789 F.3d 1292, 1298 (Fed. Cir. 2015) (emphasis
`
`omitted), overruled on other grounds by Aqua Products, Inc. v. Matal, 872
`
`F.3d 1290 (Fed. Cir. 2017) (en banc). An inventor may provide a meaning
`
`for a term that is different from its ordinary meaning by defining the term in
`
`the specification with reasonable clarity, deliberateness, and precision. In re
`
`Paulsen, 30 F.3d 1475, 1480 (Fed. Cir. 1994).
`
`Use of the word means in a claim gives rise to a rebuttable
`
`presumption that 35 U.S.C. § 112, sixth paragraph, analysis applies to
`
`interpret the claim. Williamson v. Citrix Online, LLC, 792 F.3d 1339, 1348
`
`(Fed. Cir. 2015). Construing a means-plus-function claim term is a two-step
`
`process, wherein we first identify the claimed function and then determine
`
`what structure, if any, disclosed in the specification corresponds to the
`
`claimed function. Id. at 1348–51. Our rules specifically require that a
`
`petition for inter partes review identify how each challenged claim is to be
`
`construed, including identification of the corresponding structure for means-
`
`plus-function limitations. See 37 C.F.R. § 42.104(b)(3) (2017) (“Where the
`
`claim to be construed contains a means-plus-function . . . limitation as
`
`permitted under 35 U.S.C. 112[(6)], the construction of the claim must
`
`identify the specific portions of the specification that describe the structure,
`
`material, or acts corresponding to each claimed function.”).10 “[S]tructure
`
`disclosed in the specification is ‘corresponding’ structure only if the
`
`specification or prosecution history clearly links or associates that structure
`
`
`10 37 C.F.R. § 42.104(b)(3) refers to § 112(f). Section 4(c) of the AIA
`redesignated 35 U.S.C. § 112, sixth paragraph as 35 U.S.C. § 112(f).
`Because the ’674 patent has a filing date before the effective date of this
`provision of the AIA, we use the citation § 112, sixth paragraph.
`
`12
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`

`

`IPR2018-01315, IPR2018-01316
`Patent 8,063,674 B2
`
`to the function recited in the claim.” Med. Instrumentation & Diagnostics
`
`Corp. v. Elekta AB, 344 F.3d 1205, 1210 (Fed. Cir. 2003) (quoting B.
`
`Braun Med. Inc. v. Abbott Labs., 124 F.3d 1419, 1424 (Fed. Cir. 1997)).
`
`Petitioner proposes a claim construction for “processing circuitry.”
`
`Pet. 10; 1316 Pet. 5. Petitioner also contends that the claims contain several
`
`means-plus-function limitations. 1316 Pet. 6–9.
`
`Patent Owner does not believe the term “processing circuitry” or the
`
`means-plus-function limitations need to be construed. PO Resp. 8; 1316 PO
`
`Resp. 8–9.
`
`Having considered the evidence presented, we conclude that, with the
`
`exception of the means-plus-function limitations, no express claim
`
`construction of any term is necessary. See Nidec Motor Corp. v. Zhongshan
`
`Broad Ocean Motor Co., 868 F.3d 1013, 1017 (Fed. Cir. 2017) (stating that
`
`“we need only construe those claim limitations ‘that are in controversy, and
`
`only to the extent necessary to resolve the controversy’” (quoting Vivid
`
`Techs., Inc. v. Am. Sci. & Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir. 1999))).
`
`With regard to the means-plus-function limitations, we are persuaded
`
`by Petitioner’s identification of both the function set forth in the claim and
`
`the structure in the written description that is linked to the function, and
`
`adopt them as our own. See 1316 Pet. 6–9.
`
`D. Obviousness over AAPA in View of Majcherczak
`
`1.
`
`Overview of AAPA
`
`The ’674 patent describes a prior art “power-up/down detector[] to
`
`generate a power-on/off-control (POC) signal internally.” Ex. 1001, 1:55–
`
`57, Fig. 1. The prior art design is shown in Figure 1, reproduced below.
`
`13
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`

`

`IPR2018-01315, IPR2018-01316
`Patent 8,063,674 B2
`
`
`
`
`Id. at Fig. 1. “FIG. 1 is a circuit diagram illustrating a conventional POC
`
`system for multiple supply voltage devices” and is identified as prior art. Id.
`
`at 4:18–19, Fig. 1. According to the ’674 patent, the POC “is made up of
`
`three functional blocks: power-up/down detector 100, signal amplifier 101,
`
`and output stage 102. Power-up/down detector 100 has PMOS transistor M1
`
`and NMOS transistors M2-M3.” Id. at 1:60–63.
`
`2.
`
`Overview of Majcherczak
`
`Majcherczak is titled “Power Supply Detection Device” and relates
`
`“to a power supply detection device for an integrated circuit using at least
`
`two power supply voltages.” Ex. 1008, code (54), ¶ 1. Majcherczak
`
`describes a voltage detection device that detects when the core voltage is
`
`powered down or there is an excessively slow build-up of the voltage.
`
`Ex. 1008, code (57), ¶¶ 8–11.
`
`Figure 2 of Majcherczak is shown below.
`
`14
`
`

`

`IPR2018-01315, IPR2018-01316
`Patent 8,063,674 B2
`
`
`Figure 2 shows a detection device “compris[ing] an output stage E3
`
`following the input stage E1, to obtain the desired output levels for the
`
`inverse detection signal CORE-OFFn.” Ex. 1008, ¶¶ 35–37.
`
`
`
`3.
`
`Using Applicant Admitted Prior Art During an Inter
`Partes Review
`
`a.
`
`Patent Owner’s Arguments
`
`Patent Owner argues that the grounds based on AAPA “are improper
`
`because the America Invents Act (AIA) does not permit inter partes review
`
`based on so-called [AAPA].” PO Resp. 17; see also id. at 17–20; PO Sur-
`
`reply 1–2.11 Specifically, Patent Owner argues that “that inter partes review
`
`be available ‘only on the basis of prior art consisting of patents or printed
`
`publications’” and that “[p]ortions of the patent under review – which the
`
`Petitioner has characterized as the AAPA – cannot be considered ‘prior art
`
`consisting of patents or printed publications’ within the plain meaning of the
`
`
`11 Although we only cite to IPR2018-01315 in this section, the same
`arguments were made by the parties in IPR2018-01316.
`
`15
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`IPR2018-01315, IPR2018-01316
`Patent 8,063,674 B2
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`statute.” PO Resp. 17–18 (quoting 35 U.S.C. § 311(b)). Patent Owner
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`further argues that “the regulations governing inter partes review require that
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`the petition ‘specify where each element of the claim is found in the prior art
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`patents or printed publications relied upon.’” Id. at 18 (quoting 37 C.F.R.
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`§ 42.104(b)(4)). According to Patent Owner, an admission in “the patent
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`under review cannot reasonably be considered a ‘prior art patent or printed
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`publication’ because the patent is not prior art to itself.” PO Resp. 18.
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`Patent Owner also argues that the Board erred in the Institution
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`Decision by “fail[ing] . . . to recognize other PTAB decisions that have
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`correctly held that AAPA does not qualify as prior art under Section
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`311(b).” Id. at 18–19 (citing LG Electronics, Inc. v. Core Wireless
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`Licensing S.A.R.L., IPR2015-01987, Paper 7 at 18 (PTAB Mar. 24, 2016)
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`(Institution Decision); Sony Corp. v. Collabo Innovations, Inc., IPR2016-
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`00940, Paper 7 at 30 (PTAB Oct. 24, 2016) (Institution Decision)).
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`Additionally, Patent Owner argues that “counsel for Petitioner agrees
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`that AAPA is not eligible for inter partes review, as evidenced by arguments
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`recently made by Petitioner’s counsel in IPR2017-00126.” PO Resp. 19
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`(citing Ex. 2004 (Patent Owner’s Request for Rehearing in
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`IPR2017-00126)); Ex. 2005 (Patent Owner’s Response in IPR2017-00126)).
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`Moreover, Patent Owner argues that Petitioner’s Reply “does not disagree
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`that AAPA is not proper prior art for IPR proceedings” and “never makes
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`the affirmative statement that AAPA should be considered prior art in IPRs.”
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`PO Sur-reply 1 (citing Paper 16, 1–2).
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`Patent Owner further argues that One World, cited by Petitioner in the
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`Reply, is distinguishable from the facts of this case. PO Sur-reply 1 n.1.
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`Specifically, Patent Owner argues in One World “AAPA was relied on as a
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`16
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`IPR2018-01315, IPR2018-01316
`Patent 8,063,674 B2
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`secondary reference in an obviousness ground” but, “in the present case,
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`Petitioner attempts to rely on AAPA as a primary reference.” Id. (citing One
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`World Techs., Inc. v. Chamberlain Group, Inc., IPR2017-00126, Paper 56, 6
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`(PTAB Oct. 24, 2018) (Final Written Decision Public Version)).12
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`b.
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`Petitioner’s Arguments
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`In the Petition, Petitioner did not address whether an inter partes
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`review can be based on applicant admitted prior art. See generally Pet. In
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`its Reply, Petitioner argues that “Patent Owner provides no basis upon
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`which the Board should revisit the position expressed in the Institution
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`Decision (‘ID’) that AAPA is an eligible ground for an IPR.” Pet. Reply 1
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`(citing Inst. Dec. 21–22); see also id. at 1–2. According to Petitioner, “the
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`Board diligently followed the logic articulated by the panel in IPR2017-
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`12 Additionally, Patent Owner argues that “this issue should be elevated for
`Precedential Opinion Panel review should the Board continue its improper
`consideration of the alleged AAPA.” PO Resp. 19; see also Tr. 46:7–11.
`Patent Owner further argues that allowing a petitioner to rely on AAPA is
`unsound policy because “it dissuades patent applicants from including a
`background section in their patent applications.” PO Sur-reply 2 n.2.
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`We do not address Patent Owner’s argument that allowing inter partes
`review to consider applicant admitted prior art will dissuade patent
`applicants from including a background section in their patent applications.
`See PO Sur-reply 2 n.1. Such policy arguments regarding the impact of our
`decision on what patent applicants will do are beyond our purview. See 35
`U.S.C. § 3(a)(2)(A) (“The Director shall be responsible for providing policy
`direction . . . for the Office . . . .”). If Patent Owner wishes the Precedential
`Opinion Panel to address the policy argument or any alleged inconsistency
`between PTAB panels, Patent Owner should follow the procedure set forth
`in Standard Operating Procedure 2, which can be found here:
`https://www.uspto.gov/sites/default/files/documents/
`SOP2%20R10%20FINAL.pdf.
`
`17
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`IPR2018-01315, IPR2018-01316
`Patent 8,063,674 B2
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`00126 [(One World)] regarding the availability of AAPA.” Pet. Reply 1.
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`Petitioner further argues that “the exact same language used in 35 U.S.C.
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`§ 311(b) to define eligible prior art has been previously held by the Federal
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`Circuit [in the context of pre-AIA reexamination proceedings] to encompass
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`AAPA.” Id. at 1–2 (citation omitted). Therefore, according to Petitioner,
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`“[b]ecause Patent Owner fails to advance any new arguments that were not
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`otherwise addressed by the ID or by the panel’s decisions in IPR2017-
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`00126, Patent Owner’s arguments regarding the availability of AAPA in
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`IPRs should be dismissed.” Id. at 2.
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`During the Oral Hearing, counsel for Petitioner explicitly stated that it
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`is Petitioner’s position that AAPA can be used in an inter partes review.
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`Tr. 19:23–20:2.
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`c.
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`Our Analysis
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`We agree with Petitioner that an admission in the patent that is the
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`subject to an inter partes review—that is, applicant admitted prior art—can
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`be used to challenge claims in an inter partes review.
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`We begin our analysis with the statute. 35 U.S.C. § 311(b) provides
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`that “[a] petitioner in an inter partes review may request to cancel as
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`unpatentable 1 or more claims of a patent only on a ground that could be
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`raised under section 102 or 103 and only on the basis of prior art consisting
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`of patents or printed publications.” (emphasis added). Our regulations
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`provide substantially the same limitation. See 37 C.F.R. § 42.104(b)(2)
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`(2019) (requiring the petition to “identify . . . the patents or printed
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`publications relied upon for each ground” (emphasis added)). The only
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`requirement is that the “prior art consist[] of patents or printed publications.”
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`18
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`IPR2018-01315, IPR2018-01316
`Patent 8,063,674 B2
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`Because AAPA is admitted to be prior art and is found in the ’674 patent, it
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`can be used to challenge the claims in an inter partes review.
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`This is consistent with prior use of identical statutory language. Prior
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`to enactment of the Leahy-Smith America Invents Act (“AIA”), Congress
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`used the phrase “prior art consisting of patents or printed publications” to
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`exclusively identify the prior art that could be relied upon in reexamination
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`proceedings. See 35 U.S.C. § 302 (1980) (“Any person . . . may file a
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`request for reexamination . . . on the basis of any prior art cited under the
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`provisions of section 301.”); 35 U.S.C. § 301 (1980) (identifying “prior art
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`consisting of patents or printed publications” as the only prior art that could
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`be cited in reexamination proceedings). The Federal Circuit found that
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`applicant admitted prior art could be cited and relied upon to support the
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`Board’s findings in such proceedings. See In re NTP, Inc., 654 F.3d 1279,
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`1304 (Fed. Cir. 2011). By finding that applicant admitted prior art could be
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`used in combination with another reference in a pre-AIA reexamination
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`proceeding in which only “prior art consisting of patents or printed
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`publications” could be cited, the Federal Circuit has found, as we do above,
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`that “prior art consisting of patents or publications” includes applicant
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`admitted prior art. See NTP, 654 F.3d at 1304;13 see also In re Nomiya, 509
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`F.2d 566, 570–71 (CCPA 1975) (holding that applicant admitted prior art
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`may “be considered as prior art in determining obviousness of their
`
`
`13 As Patent Owner pointed out during the Oral Hearing, the patent owner in
`NTP did not appeal the Board’s decision to rely on the applicant admitted
`prior art. Tr. 41:8–12; see also NTP, 654 F.3d 1279. However, the Federal
`Circuit’s decision is still, at a minimum, persuasive authority for the
`proposition that application admitted prior art is “prior art consisting of
`patents . . .”
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`19
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`IPR2018-01315, IPR2018-01316
`Patent 8,063,674 B2
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`improvement”). Because Congress used the same language—“prior art
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`consisting of patents or printed publications”—in both the pre-AIA
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`reexamination statute and the inter partes review statute, we give the same
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`phrase the same meaning. See also One World, Paper 56 at 35–41 (holding
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`that applicant admitted prior art can be used to challenge the claims in an
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`inter partes review).
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`We do not agree with Patent Owner that, based on our rules, an
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`admission in “the patent under review cannot reasonably be considered a
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`‘prior art patent or printed publication’ because the patent is not prior art to
`
`itself.” PO Resp. 18 (emphasis in original); see also id. (“Likewise, the
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`regulations governing inter partes review require that the petition “specify
`
`where each element of the claim is found in the prior art patents or printed
`
`publications relied upon.” (quoting 37 C.F.R. § 42.104(b)(4)) (emphasis in
`
`original)). However, the language in Rule 42.104(b)(4) cannot be read in
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`isolation, as Patent Owner has don