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`IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`Chang Ki Kwon et al.
`In re Patent of:
`8,063,674
`U.S. Patent No.:
`November 22, 2011
`Issue Date:
`Appl. Serial No.: 12/365,559
`Filing Date:
`February 4, 2009
`Title:
`Multiple supply-voltage power-up/down detectors
`
`
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`DECLARATION OF ROBERT W. HORST, PH.D.
`
`I, Robert W. Horst, Ph.D., of San Jose, CA, declare that:
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`I.
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`Qualifications and Background Information
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`
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`I am currently an Adjunct Research Professor in the Department of
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`Electrical and Computer Engineering the University of Illinois at Urbana-Cham-
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`paign and am also an independent consultant at HT Consulting. I am an independ-
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`ent consultant with more than 30 years of expertise in the design and architecture
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`of computer systems. I have testified as an expert witness and consultant in patent
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`and intellectual property litigation as well as inter partes reviews and re-examina-
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`tion proceedings. My curriculum vitae is provided as APPLE-1004.
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`
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`I earned my M.S. (1978) in electrical engineering and Ph.D. (1991) in
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`computer science from the University of Illinois at Urbana-Champaign after earn-
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`ing my B.S. (1975) in electrical engineering from Bradley University. During my
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`master’s program, I designed, constructed and debugged a shared memory parallel
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`APPLE 1003
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`1
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`microprocessor system. During my doctoral program, I designed and simulated a
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`massively parallel, multi-threaded task flow computer.
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`After receiving my bachelor’s degree and while pursuing my master’s
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`degree, I worked for Hewlett-Packard Co. While at Hewlett-Packard, I designed
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`the micro-sequencer and cache of the HP3000 Series 64 processor. From 1980 to
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`1999, I worked at Tandem Computers, which was acquired by Compaq Computers
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`in 1997. While at Tandem, I was a designer and architect of several generations of
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`fault-tolerant computer systems and was the principal architect of the NonStop Cy-
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`clone superscalar processor. The system development work at Tandem also in-
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`cluded development of the ServerNet System Area Network and applications of
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`this network to fault tolerant systems and clusters of database servers.
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`
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`Since leaving Compaq in 1999, I have worked with several technol-
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`ogy companies, including 3Ware, Network Appliance, Tibion, and AlterG in the
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`areas of network-attached storage and biomedical devices. From 2012 to 2015, I
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`was Chief Technology Officer of Robotics at AlterG, Inc., where I worked on the
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`design of anti-gravity treadmills and battery-powered orthotic devices to assist
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`those with impaired mobility.
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`In 2001, I was elected an IEEE Fellow “for contributions to the archi-
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`tecture and design of fault tolerant systems and networks.” I have authored over
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`2
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`30 publications, have worked with patent attorneys on numerous patent applica-
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`tions, and I am a named inventor on 82 issued U.S. patents.
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` My patents include those directed to computer systems with multiple
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`supply voltages including U.S. Pat. No. 6,496,940 (Multiple processor system with
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`standby sparing) and U.S. Pat. No. 5,193,175 (Fault-tolerant computer with three
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`independently clocked processors asynchronously executing identical code that are
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`synchronized upon each voted access to two memory modules). My patents also
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`include aspects of circuit design including U.S. Pat. No 5,034,964 (N:1 time-volt-
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`age matrix encoded I/O transmission system) and U.S. Pat. No. 9,893,604 (Circuit
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`with low DC bias storage capacitors for high density power conversion).
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`
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`In writing this Declaration, I have considered the following: my own
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`knowledge and experience, including my work experience in the fields of com-
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`puter systems and circuit design and my experience in working with others in-
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`volved in those fields. In addition, I have analyzed the following publications and
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`materials, in addition to other materials I cite in my declaration:
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`• U.S. Patent No. 8,063,674 (APPLE-1001), and its accompanying
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`prosecution history (APPLE-1002)
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`• U.S. Patent No. 7,279,943 to Ulrich Steinaker (“Steinaker”) (APPLE-
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`1005)
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`• U. S. Patent No. 4,717,836 to James Doyle (”Doyle”) (APPLE-1006)
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`3
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`• J. C. Park and V. J. Mooney III, “Sleepy Stack Leakage Reduction,”
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`14 IEEE Transactions on Very Large Scale Integration (VLSI)
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`Systems 11, pp. 1250-1263 (Nov. 2006) (“Park”) (APPLE-1007)
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`• U.S. Patent Application No. 2002/0163364 to Sylvain Majcherczak
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`(“Majcherczak”) (APPLE-1008)
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`• U.S. Patent No. 6,646,844 to Lloyd P. Matthews (“Matthews”)
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`(APPLE-1009)
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`• G. W. Griffiths, “A Review of Semiconductor Packaging and Its Role
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`in Electronics Manufacturing,” 8th IEEE/CHMT International
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`Conference on Electronic Manufacturing Technology Symposium
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`(1990) (APPLE-1010)
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`• Wang-Chang Albert Gu, “RF Front-End Modules in Cellular
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`Handsets,” 2004 IEEE Compound Semiconductor Integrated Circuit
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`Symposium (Feb. 2005) (APPLE-1011)
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`• Roy, K, S Mukhopadhyay, and H Mahmoodi Meimand, “Leakage
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`current mechanisms and leakage reduction techniques in deep-
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`submicrometer CMOS circuits,” 91 Proceedings of the IEEE 2, pp.
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`305-327 (Apr. 2003) (“Roy”) (APPLE-1012)
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`• Y. Ye, S. Borkar and V. De, “A new technique for standby leakage
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`reduction in high-performance circuits,” 1998 Symposium on VLSI
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`4
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`Circuits. Digest of Technical Papers (Cat. No.98CH36215), Honolulu,
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`HI, USA, 1998, pp. 40-41 (“Borkar”) (APPLE-1013)
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`• U.S. Patent No. 7,049,865 to Parker et al. (“Parker”) (APPLE-1014)
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`• Qadeer A. Khan et al., “A Sequence Independent Power-on-Reset
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`Circuit for Multi-Voltage Systems,” 2006 IEEE International
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`Symposium on Circuits and Systems (Sep. 2006) (APPLE-1015)
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`II. Legal Principles
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`
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`In forming my opinions expressed in this declaration, I have applied
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`the legal principles described in the following paragraphs.
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`A. Legal Standards for Prior Art
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`I am not an attorney. My understanding of the legal standards
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`throughout this section are based on discussion with Counsel and my experience in
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`prior patent cases.
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`I understand that a patent or other publication must first qualify as
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`prior art before it can be used to invalidate a patent claim.
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`I understand that a U.S. or foreign patent qualifies as prior art to an as-
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`serted patent if the date of issuance of the patent is prior to the effective filing date
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`of the asserted patent. I further understand from Counsel that a printed publication,
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`such as an article published in a journal, magazine, or trade publication, qualifies
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`as prior art to an asserted patent if the date of publication is prior to the effective
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`filing date of the asserted patent.
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`I further understand that a U.S. patent can qualify as prior art to the
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`asserted patent if the application for that patent was filed in the United States be-
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`fore the effective filing date of the asserted patent.
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` Counsel has informed me that certain exceptions can apply to disqual-
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`ify a reference as prior art, but for the purpose of my analysis in this declaration, I
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`have assumed that the standards discussed above for assessing prior art eligibility
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`apply.
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`B. Anticipation
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`I understand that patents or printed publications that qualify as prior
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`art can be used to invalidate a patent claim as anticipated or as obvious.
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`I understand that, once the claims of a patent have been properly con-
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`strued, the second step in determining anticipation of a patent claim requires a
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`comparison of the properly construed claim language to the prior art on a limita-
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`tion-by-limitation basis.
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`I understand that a prior art reference “anticipates” an asserted claim,
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`and thus renders the claim invalid, if all limitations of the claim are disclosed in
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`that prior art reference, either explicitly or inherently (i.e., necessarily present).
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`I understand that anticipation in an inter partes review must be proven
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`by a preponderance of the evidence.
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`C. Obviousness
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`I understand that even if a patent is not anticipated, it is still invalid if
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`the differences between the claimed subject matter and the prior art are such that
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`the subject matter as a whole would have been obvious at the time the invention
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`was made to a POSITA.
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`I understand that a POSITA provides a reference point from which the
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`prior art and claimed invention should be viewed. This reference point is applied
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`instead of someone using his or her own insight or hindsight in deciding whether a
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`claim is obvious.
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`I also understand that an obviousness determination includes the con-
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`sideration of various factors such as: (1) the scope and content of the prior art, (2)
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`the differences between the prior art and the asserted claims, (3) the level of ordi-
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`nary skill in the pertinent art, and (4) the existence of secondary considerations
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`such as commercial success, long-felt but unresolved needs, failure of others, etc.
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`I understand that an obviousness evaluation can be based on a combi-
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`nation of multiple prior art references. I understand that the prior art references
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`themselves may provide a suggestion, motivation, or reason to combine, but other
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`7
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`times the linkage between two or more prior art references is common sense. I fur-
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`ther understand that obviousness analysis recognizes that market demand, rather
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`than scientific literature, often drives innovation, and that a motivation to combine
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`references may be supplied by the direction of the marketplace.
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`I understand that if a technique has been used to improve one device,
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`and a POSITA would recognize that it would improve similar devices in the same
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`way, using the technique is obvious unless its actual application is beyond his or
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`her skill.
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`I also understand that practical and common sense considerations
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`should guide a proper obviousness analysis, because familiar items may have obvi-
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`ous uses beyond their primary purposes. I further understand that a POSITA look-
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`ing to overcome a problem through invention will often be able to fit together the
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`teachings of multiple publications. I understand that obviousness analysis there-
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`fore takes into account the inferences and creative steps that a POSITA would em-
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`ploy under the circumstances.
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`I understand that a particular combination may be proven obvious
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`merely by showing that it was obvious to try the combination. For example, when
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`there is a design need or market pressure to solve a problem and there are a finite
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`number of identified, predictable solutions, a POSITA has good reason to pursue
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`the known options within his or her technical grasp because the result is likely the
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`product not of innovation but of ordinary skill and common sense.
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` The combination of familiar elements according to known methods is
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`likely to be obvious when it does no more than yield predictable results. When a
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`work is available in one field of endeavor, design incentives and other market
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`forces can prompt variations of it, either in the same field or a different one. If a
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`POSITA can implement a predictable variation, the patent claim is likely obvious.
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`It is further my understanding that a proper obviousness analysis fo-
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`cuses on what was known or obvious to a POSITA, not just the patentee. Accord-
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`ingly, I understand that any need or problem known to those of ordinary skill in the
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`field of endeavor at the time of invention and addressed by the patent can provide a
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`reason for combining the elements in the manner claimed.
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`I understand that a claim can be obvious in light of a single reference,
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`without the need to combine references, if the elements of the claim that are not
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`found explicitly or inherently in the reference can be supplied by the common
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`sense of one of ordinary skill in the art.
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`I understand that secondary indicia of non-obviousness may include
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`(1) a long felt but unmet need in the prior art that was satisfied by the invention of
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`the patent; (2) commercial success of processes covered by the patent; (3) unex-
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`pected results achieved by the invention; (4) praise of the invention by others
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`skilled in the art; (5) taking of licenses under the patent by others; (6) deliberate
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`copying of the invention; (7) failure of others to find a solution to the long felt
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`need; and (8) skepticism by experts. I understand that evidence of secondary indi-
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`cia of non-obviousness, if available, should be considered as part of the obvious-
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`ness analysis.
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`I also understand that there must be a relationship between any such
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`secondary considerations and the invention. I further understand that contempora-
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`neous and independent invention by others is a secondary consideration supporting
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`an obviousness determination.
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`In sum, my understanding is that prior art teachings are properly com-
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`bined where a POSITA having the understanding and knowledge reflected in the
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`prior art and motivated by the general problem facing the inventor, would have
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`been led to make the combination of elements recited in the claims. Under this
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`analysis, the prior art references themselves, or any need or problem known in the
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`field of endeavor at the time of the invention, can provide a reason for combining
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`the elements of multiple prior art references in the claimed manner.
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`I understand that obviousness in an inter partes review must be
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`proven by a preponderance of the evidence.
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`III. Background Knowledge One of Skill in the Art Would Have Had Prior
`To the Priority Date of the ’674 Patent
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` The technology in the ’674 Patent at issue generally relates to the de-
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`sign of power up/down circuits for semiconductor devices with multiple power
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`supplies. APPLE-1001, 1:6-8. Prior to the priority date of the ’674 Patent, there
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`existed numerous products, publications, and patents that implemented or de-
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`scribed the functionality claimed in the ’674 Patent—some of which are detailed
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`below. The patent specification and figures of the ’674 Patent include CMOS cir-
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`cuits, flowcharts and block diagrams. The figures and specification describe
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`CMOS circuits, but do not, for example, include any guidance on certain key pa-
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`rameters of the transistors (e.g., threshold voltages and drain-source impedance) re-
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`quired to make the circuits operational. Hence a person of ordinary skill in the art
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`would have needed a high enough degree of experience and training in circuits and
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`systems to determine these and other missing implementation details.
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` Thus, based on the foregoing and upon my experience in this area, a
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`person of ordinary skill in the art in this field at and around the February 4, 2009
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`filing date of the ’674 Patent (hereinafter “POSITA”) would have had at least an
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`undergraduate degree in electrical engineering, or a related field, and three years of
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`experience in circuit and system design. Alternatively, a person of ordinary skill
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`with less than the amount of experience noted above could have had a correspond-
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`ingly greater amount of educational training such a graduate degree in a related
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`field.
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` Based on my experiences, I have a good understanding of the capabil-
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`ities of a POSITA. Indeed, I have participated in organizations and worked closely
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`with many such persons over the course of my career.
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`I am well qualified in the design of circuits and systems related to
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`the ’674 Patent and I was a person of at least ordinary skill in the art in the ’674
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`timeframe.
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`IV. State of the Art and Overview of Technology at Issue
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`A. Circuit Design
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` The ’674 Patent and related prior art include circuit diagrams pre-
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`sented at both the gate level (e.g., AND, NAND, OR, NOR and inverters) and indi-
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`vidual transistor level. The gate-level diagrams use standard notation for gates and
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`use bubbles to indicate signal inversion.
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` The circuit-level diagrams across the various references to which I
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`cite use a variety of different conventions to draw transistors. For the art cited in
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`this report, the transistors are primarily enhancement mode Metal Oxide Semicon-
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`ductor Field Effect Transistors (MOSFETs). Below I have shown some of the dif-
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`ferent ways of drawing these transistors:
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`12
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` When used in switching circuits, P-channel and N-channel transistors
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`can generally be analyzed as if they are ideal switches, with the P channels con-
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`ducting when the gate (G) is negative relative to the source (S), and the N channels
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`conducting when gate is positive relative to the source. Many circuits include a
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`mix of N-channel and P-channel transistors, often configured as standard CMOS
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`(complementary metal-oxide semiconductor) logic circuits. For instance, a CMOS
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`inverter has N-channel and P-channel transistors with both gates connected to the
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`input, the source terminals to voltage rails (ground and the positive voltage), and
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`the drains connected together and to the output. This is illustrated in FIG. 2A of
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`Doyle, which describes this as “the basic well-known CMOS inverter structure.”
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`APPLE-1006, 4:3-6.
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`P-Channel
`MOSFETs
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`G
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`S
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`G
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`S
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`G
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`S
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`G
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`S
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`G
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`S
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`G
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`D
` Park,
`Steinacker
`D
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`G
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`N-Channel
`MOSFETs
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`D
`Doyle,
`Majcherczak
`D
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`G
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`G
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`S
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`S
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`D
`D
`D
`------------------- Other -------------------
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`G
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`D
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`S
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`G
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`D
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`S
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`G
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`D
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`S
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`D
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`D
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`S
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`S
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`FIG. 2A of Doyle
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` The transistors in the ’674 Patent circuits are used for more than just
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`logic circuits. The characteristics of these transistors dictate voltage detection lev-
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`els and the amount of sub-threshold leakage of the circuits described in the ’674
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`Patent, requiring a deeper understanding of the transistor parameters. For example,
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`the MOSFET threshold voltage, usually abbreviated Vth, determines the voltage
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`level at which the transistor is switched on and can conduct current. When FETs
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`are used for voltage level detection, as in the ’674 Patent, the detected voltage is
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`directly influenced by the Vth of the selected transistors.
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` When a MOSFET switches on, it acts like a resistor, but depending on
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`the way it is constructed, the resistance can vary from a few milliohms to several
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`thousand ohms. A transistor’s impedance or resistance—abbreviated Rdson or just
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`Ron—determines the current that can be conducted through the transistor and deter-
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`mines the voltage drop and power loss. Moreover, the Ron of the transistors deter-
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`mines how currents are shared when transistors are connected in parallel, such as
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`the feedback transistors in the ’674 Patent circuits.
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` The ’674 Patent does not specify Vth or Ron for the transistors in the
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`circuits in the drawings and specification. The fact that the ’674 Patent does not
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`give guidance in the selection of these key parameters indicates that a POSITA
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`should be assumed to have sufficient skill in circuit design to understand and mod-
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`ify circuits in a way that a POSITA would be able to select the appropriate parame-
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`ters, or to construct stacks of transistors to obtain the desired and useful power de-
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`tection functionality described in the ’674 Patent.
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`B.
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`Leakage
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` The term “leakage” generally refers to unwanted current that flows
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`when the switching elements are nominally off. Leakage increases power dissipa-
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`tion and drains the battery in portable devices, thus reduction in leakage is highly
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`desirable.
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` The causes of leakage include “subthreshold leakage” and “gate-oxide
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`leakage”. Subthreshold leakage is the current that flows in transistors that are
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`nominally switched off:
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`One of the main reasons causing the leakage power increase is the
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`increase of subthreshold leakage power. When technology feature size
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`scales down, supply voltage and threshold voltage also scale down.
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`Subthreshold leakage power increases exponentially as threshold
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`voltage decreases. Furthermore, the structure of the short channel
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`device decreases the threshold voltage even lower.
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`APPLE-1007, p. 1 (emphasis added).
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` Gate-oxide leakage is determined by process parameters:
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`In addition to subthreshold leakage, another contributor to leakage
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`power is gate-oxide leakage power due to the tunneling current
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`through the gate-oxide insulator. Since gate-oxide thickness may
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`reduce as the channel length decreases, in sub 0.1- µm technology,
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`gate-oxide leakage power may be comparable to subthreshold leakage
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`power if not handled properly
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`Id. (emphasis added).
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` The ’674 Patent discusses “leakage” but does not distinguish between
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`the different types of leakage. A POSITA would understand that it is referring to
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`subthreshold leakage because circuit design techniques do not have an effect on
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`gate-oxide leakage.
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` Subthreshold leakage can be decreased by circuit design techniques
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`that drive the gate voltage farther from the threshold. The following figure from
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`Roy shows that driving the gate voltage lower in an NMOS transistor can reduce
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`the leakage current (ID) by orders of magnitude. Each tick mark on the vertical
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`axis is a power of 10 reduction in leakage.
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`Roy, page 305
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` The sub-threshold leakage can be reduced by driving the gate voltage
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`further from the threshold by circuit design techniques. Using stacked transistors
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`reduces the sub-threshold leakage because, in the case of NMOS transistor, one of
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`the series transistors has a higher source voltage, making its gate voltage negative
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`with respect to its source. The use of stacked transistors to reduce leakage current
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`was well known before the priority date of the ’674 Patent as described in Borkar
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`(1998), Roy (2003) and Park (2006). See generally APPLE-1007; APPLE-1012;
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`APPLE-1013. The use of stacked transistors for leakage reduction is included in
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`some of the circuits of the ’674 Patent.
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`C.
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`Processor I/O and Core Voltages and Reset Circuits
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` Processors are generally designed with multiple different voltage lev-
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`els. For instance, the processor core is typically set to a low voltage, often around
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`1V, to minimize power dissipation, while I/O interfaces are typically set to a stand-
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`ard voltage such as 3.3 or 5 V to support interoperability with other components
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`supporting those standards. After applying power to a system, there is a period of
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`time before voltages have stabilized and processors are prevented from executing
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`code until the operating voltages are known to be good. A reset signal delays exe-
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`cution until the voltages are known to be good. The name of this signal varies (e.g.
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`RESET, power-on-reset (POR), power-on-control (POC), or CORE-OFF). The re-
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`set signal is sometimes active low, meaning that the reset occurs when the signal is
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`at ground potential. Active low signals are often indicated with an overbar or suf-
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`fix. The ’674 Patent uses an active high reset signal called PON. Steinaker’s reset
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`signal is the output of Voltage Level Detector 5. Majcherczak names the active
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`low reset signal CORE-OFF/n.
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`In systems with multiple voltages, the sequences of applying the dif-
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`ferent voltages may be carefully controlled or the voltages may become valid at
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`any time. Khan describes techniques for generating reset signals in multi-voltage
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`systems:
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`Khan drawing of a multi-voltage power-on sequence.
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` While Khan describes circuits that delays reset until all voltages are
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`valid, the ’674 Patent uses a simpler circuit that depends on a valid I/O voltage in
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`order to detect the level of the core voltage.
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`D. Hysteresis
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`19
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` The term “hysteresis” is used in electronics to refer to circuits that
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`have different voltage thresholds when detecting rising voltages than falling volt-
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`ages. Hysteresis is desirable for reliably detecting voltage transitions to prevent
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`the output from oscillating rapidly when the input voltage is at or near the thresh-
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`old. Buffers or inverters designed with hysteresis are called Schmitt triggers.
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`When the voltage is rising, the threshold is higher than when the voltage is falling.
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`Thus, if the input voltage lingers near the threshold, the output remains high if it
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`had previously been high or remains low if it had previously been low.
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` Hysteresis is especially desirable for detection of power voltages be-
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`cause these voltages change slowly, and the processor should remain reset until the
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`input voltage is reliably above the higher threshold. This concept is described by
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`Doyle as follows:
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`In order to provide good noise immunity for a logic circuit, including
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`a CMOS logic circuit, it is sometimes desirable to provide hysteresis
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`in the input circuitry of an integrated circuit chip.
`
`APPLE-1006, 1:60-63
`
` Steinacker describes voltage detector 5 that can take “the form of a
`
`Schmitt trigger with an inverting output . . . an inverter circuit, a comparator circuit
`
`or comparable circuits.” APPLE-1005, 4:49-55. Thus, Steinacker recognizes the
`
`advantage of introducing hysteresis in voltage detection circuits.
`
`
`
`20
`
`
`
`
`
`tion:
`
` Majcherczak also describes the benefits of hysteresis in voltage detec-
`
`With the output stage E3, a hysteresis detection is obtained with a low
`
`threshold of switching from a state of the presence of a core power
`
`supply to a state of the absence of a core power supply, and a high
`
`threshold of switching of the detection circuit from a state of absence
`
`of the core supply to a state of presence of the core supply. In
`
`particular, if the output node Nin of the input stage is at Vdd3, then
`
`the signal IN applied to its input rises sufficiently to force the output
`
`node Nin downwards, and consequently, cut off the pull-down
`
`transistor M6. In a practical example, for integrated circuits using 0.18
`
`µ technology with a core supply voltage of 1.8 volts, the high
`
`threshold may thus be equal to 0.98 volts and the low threshold may
`
`be equal to 0.33 volts.
`
`APPLE-1008, ¶ 0038.
`
` The ’674 Patent does not discuss hysteresis or Schmitt triggers, but it
`
`does disclose feedback transistors that give the positive feedback required to alter
`
`the input threshold, and the disclosed circuits do exhibit hysteresis in the same way
`
`as the prior art. In the ’674 Patent, feedback is shown, for instance, in Fig. 3B as
`
`Feedback Network 310 and in Fig. 4 as the signal to the gate of transistor M8.
`
`V. Overview of the ’674 Patent
`
`
`
`21
`
`
`
`
`
` The power-on/off-control (POC) device described in the ’674 Patent
`
`was intended for use in “newer integrated circuit devices include dual power sup-
`
`plies: one lower-voltage power supply for the internally operating or core applica-
`
`tions, and a second higher-voltage power supply for the I/O circuits and devices.”
`
`APPLE-1001, 1:22-25. The POC device described in the ’674 Patent was intended
`
`to provide more accurate communications between newer, low power circuits (i.e.,
`
`the “core network”) and the legacy, high power devices with which the core net-
`
`work interfaces (i.e., the “I/O network”). See APPLE-1001, 1:12-58.
`
` The logic high signal of the core network is a function of the lower
`
`supply voltage of the core network (e.g., 1.8 volts), whereas the logic high signal
`
`of the I/O network is a function of the high supply voltage of the I/O network (e.g.,
`
`3 volts). See id.; see also APPLE-1008, [0001]-[0004], [0040]. In order for the
`
`logic signals of the core network to be communicated to the I/O network in a man-
`
`ner that the circuits of the I/O network can properly interpret the signals (and vice
`
`versa), the logic signals of the two networks must be translated to the proper levels.
`
`See APPLE-1001, 1:26-29. Circuits called level shifters essentially shift the volt-
`
`age levels of any communications that occur between the I/O network and the core
`
`network. See APPLE-1001, 4:59-61. In effect, these level shifters translate a logic
`
`‘1’ from approximately the value of the lower supply voltage (or a function
`
`thereof) to approximately the value of the higher supply voltage (or a function
`
`
`
`22
`
`
`
`
`
`thereof) and vice versa. As a result, the logic signals communicated between the
`
`core network devices and the I/O network devices are translated into the appropri-
`
`ate voltage levels.
`
` However, common power-saving techniques employed in core net-
`
`works can cause the level shifters to send erroneous signals to the I/O network that
`
`can cause problems. See APPLE-1001, 1:26-40. “Powering down or power col-
`
`lapsing is a common technique used to save power when no device operations are
`
`pending or in progress.” APPLE-1001, 1:32-34. As the core network is being
`
`power collapsed, it can generate “stray currents or the like,” which are translated
`
`by the level shifters as legitimate signals and output to the I/O network. See AP-
`
`PLE-1001, 1:34-37. “The I/O devices assume that the core devices have initiated
`
`this communication, and will, therefore, transmit the erroneous signal into the ex-
`
`ternal environment.” APPLE-1001, 1:37-40. These illegitimate signals can cause
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`costly errors within the system.
`
` Accordingly, the ’674 Patent teaches that it was known to use special
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`circuits that monitor the power supply of the core network and notify the I/O net-
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`work when the core network power supply is collapsed, so that the I/O network can
`
`be transitioned into a “known state” (i.e., a state in which it can ignore any stray
`
`signals that may be output by the level shifters). See APPLE-1001, 1:41-58. On
`
`
`
`23
`
`
`
`
`
`such type of circuit is a power up/down detector that generates a power-on/off-con-
`
`trol (POC) signal. APPLE-1001, 1:55-57. “The POC signal instructs the I/O de-
`
`vices when the core devices are shut down.” APPLE-1001, 1:57-58.
`
`
`
`In its background section, the ’674 Patent acknowledges that a “stand-
`
`ard” POC system 10 for multiple supply voltage devices was known at the time of
`
`the filing of the ’674 Patent. See APPLE-1001, 1:57-2:39. This known POC sys-
`
`tem 10 is shown in FIG. 1 to include a power-up/down detector 100, a signal am-
`
`plifier 101, and an output stage 102. See id. at FIG. 1, 1:57-62. The main differ-
`
`ence between this prior art POC system 10 and the purported invention of the ’674
`
`Patent is the addition of a feedback network 310. A comparison of FIG. 1 and
`
`FIG. 4 illuminates the addition made by the inventors of the ’674 Patent.
`
` The ’674 Patent describes that the prior art POC system 10 suffered
`
`from “leakage current between I/O power supply 104 and ground” and/or slower
`
`“switching/detecting times” (i.e., the speed with which the prior art POC system 10
`
`
`
`
`
`power up/
`down detector
`
`signal processor
`
`power up/
`down detector
`
`feedback
`network
`
`signal processor
`
`24
`
`
`
`
`
`detects that the core supply voltage has powered down). See APPLE-1001, 2:25-
`
`3:11. The feedback network 310 increases the current capacity when it is “on,” re-
`
`sulting in increased sensitivity. See APPLE-1001, 5:16-23. Conversely, the feed-
`
`back network 310 decreases the current capacity when it is “off,” which “will limit
`
`and reduce the amount of leakage current that may be dissipated through the power
`
`up/down detector.” See APPLE-1001, 5:29-38.
`
` Each of the three implementations of the feedback network 310 de-
`
`scribed in the ’674 Patent—corresponding to FIGS. 4, 5, and 6 of the ’674 Pa-
`
`tent—will increase and decrease the current capacity of the power up/down detec-
`
`tor. For example, in FIG. 4 (a highlighted and annotated version of which is repro-
`
`duced below), the transistor M8 is in parallel1 with the transistor M4. APPLE-
`
`
`1 The ’674 Patent uses the term “parallel” to refer to both (1) the traditional case in
`
`which two circuit components have the same potential difference (i.e., voltage)
`
`across their ends (e.g., transistor M4 is “coupled in parallel” with transistor M8 in
`
`FIG. 4 of the ’674 Patent); and (2) when a single circuit component has the same
`
`potential difference across its ends as multiple components connected in series
`
`have across the two ends of the series chain (e.g., transistors M9 and M10 are
`
`
`
`
`
`25
`
`
`
`
`
`1001, 6:4-5. Due to the configuration of the transistor M8, it is generally “on”
`
`when the transistor M4 is “on” and is “off” when the transistor M4 is “off” (except
`
`for a short delay during transitions in Vcore). See APPLE-1001, 6:4-28. This is be-
`
`cause the power up/down detector 306 acts as an
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