UNITED STATES PATENT AND TRADEMARK OFFICE
`
`____________
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`____________
`
`
`APPLE INC.,
`Petitioner,
`
`v.
`
`QUALCOMM INCORPORATED,
`Patent Owner.
`
`____________
`
`
`Case IPR2018-01316
`Patent 8,063,674
`
`____________
`
`
`
`PETITIONERS’ REPLY TO PATENT OWNER RESPONSE
`
`PURSUANT TO 37 C.F.R. § 42.23
`
`
`
`
`
`
`
`
`
`____________
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`____________
`
`
`APPLE INC.,
`Petitioner,
`
`v.
`
`QUALCOMM INCORPORATED,
`Patent Owner.
`
`____________
`
`
`Case IPR2018-01316
`Patent 8,063,674
`
`____________
`
`
`
`PETITIONERS’ REPLY TO PATENT OWNER RESPONSE
`
`PURSUANT TO 37 C.F.R. § 42.23
`
`
`
`
`
`
`
`
`
`Proceeding No.: IPR2018-01316
`Attorney Docket: 39521-0053IP2
`
`TABLE OF CONTENTS
`
`I. THE BOARD’S PRECEDENT CLEARLY ARTICULATES THAT
`GROUNDS IN AN IPR MAY BE BASED ON AAPA ............................... 1
`
`II. EXPLICIT MOTIVATION TO COMBINE THE AAPA WITH
`MAJCHERCZAK, AS DESCRIBED IN THE PRIOR ART, IS NOT
`OBVIATED BY POTENTIAL DISADVANTAGES OF THE
`COMBINATION ALLEGED BY PATENT OWNER ................................ 2
`
`A. There Exists Explicit Motivation in Majcherczak to Combine the AAPA
`and Majcherczak ......................................................................................... 3
`
`B. The Motivation of Gaining Hysteresis in the AAPA is Not Obviated by
`Patent Owner’s Allegations of Potential Disadvantage Arising from the
`Combination ............................................................................................... 7
`
`III. EXPLICIT MOTIVATION IN THE PRIOR ART TO COMBINE
`STEINACKER, DOYLE, AND PARK IS NOT OBVIATED BY
`POTENTIAL DISADVANTAGES OF THE COMBINATION ALLEGED
`BY PATENT OWNER ................................................................................ 12
`
`A. Explicit Teachings in Steinacker, Doyle, and Park Motivate the
`Combination Set Forth in the Petition ...................................................... 13
`
`B.
`
`Patent Owner’s Allegations of Certain Disadvantages Do Not Obviate the
`Prior Art’s Motivation to Combine Steinacker, Doyle, and Park ............ 24
`
`IV. CONCLUSION ................................................................................................ 24
`
`
`
`
`
`
`
`
`i
`
`
`
`Proceeding No.: IPR2018-01316
`Attorney Docket: 39521-0053IP2
`
`EXHIBITS
`
`APPLE-1001
`
`U.S. Patent No. 8,063,674 to Kwon et al. (“the ’674 patent”)
`
`APPLE-1002
`
`Excerpts from the Prosecution History of the ’674 Patent (“the
`Prosecution History”)
`
`APPLE-1003
`
`Declaration of Dr. Robert Horst
`
`APPLE-1004
`
`Curriculum Vitae of Dr. Robert Horst
`
`APPLE-1005
`
`U.S. Patent No. 7,279,943 to Steinacker (“Steinacker”)
`
`APPLE-1006
`
`U.S. Patent No. 4,717,836 to Doyle (“Doyle”)
`
`APPLE-1007
`
`Jun Cheol Park and Vincent J. Mooney, Sleepy Stack Leakage
`Reduction, 14 IEEE Transactions On Very Large Scale
`Integration (VLSI) Systems 1251 (2006) (“Park”)
`
`APPLE-1008
`
`U.S. Pat. Appl. Pub. No. 2002/0163364 to Majcherczak et al.
`(“Majcherczak”)
`
`APPLE-1009
`
`U.S. Patent No. 6,646,844 to Matthews (“Matthews”)
`
`APPLE-1010
`
`G. W. Griffiths, “A Review of Semiconductor Packaging and
`Its Role in Electronics Manufacturing,” 8th IEEE/CHMT
`International Conference on Electronic Manufacturing
`Technology Symposium (1990)
`
`APPLE-1011
`
`Wang-Chang Albert Gu, “RF Front-End Modules in Cellular
`Handsets,” 2004 IEEE Compound Semiconductor Integrated
`Circuit Symposium (2005)
`
`APPLE-1012
`
`Kaushik Roy et al., “Leakage current mechanisms and leakage
`reduction techniques in deep-submicrometer CMOS circuits,”
`91 Proceedings of the IEEE 2, pp. 305-327 (Apr. 2003) (“Roy”)
`
`
`
`ii
`
`
`
`Proceeding No.: IPR2018-01316
`Attorney Docket: 39521-0053IP2
`
`APPLE-1013
`
`Yangyang Ye et al., “A new technique for standby leakage
`reduction in high-performance circuits,” 1998 Symposium on
`VLSI Circuits. Digest of Technical Papers (Cat.
`No.98CH36215), Honolulu, HI, USA, 1998, pp. 40-41
`(“Borkar”)
`
`APPLE-1014
`
`U.S. Patent No. 7,049,865 to Parker et al. (“Parker”)
`
`APPLE-1015
`
`Qadeer A. Khan et al., “A Sequence Independent Power-on-
`Reset Circuit for Multi-Voltage Systems,” 2006 IEEE
`International Symposium on Circuits and Systems (Sep. 2006)
`
`APPLE-1016
`
`Declaration of Jacob Munford (with attachments)
`
`APPLE-1017
`
`Transcript of Deposition of Dr. Massoud Pedram
`
`APPLE-1018
`
`Supplemental Declaration of Dr. Robert Horst
`
`APPLE-1019
`
`U. Daya Perera, Reliability of Mobile Phones, 1995 IEEE
`Proceedings Annual Reliability and Maintainability Symposium
`(Jan. 1995)
`
`APPLE-1020
`
`One World Technologies, Inc. v. The Chamberlain Group, Inc.,
`IPR2017-00126, Paper 56 (Final Written Decision) (PTAB Oct.
`24, 2018)
`
`APPLE-1021
`
`One World Technologies, Inc. v. The Chamberlain Group, Inc.,
`IPR2017-00126, Paper 67 (Denial of Rehearing Request), 14-
`21 (PTAB Apr. 4, 2019)
`
`APPLE-1022
`
`U.S. Patent No. 5,386,153 to Peer H. Voss et al. (“Voss”)
`
`APPLE-1023
`
`Wikipedia Entry for “LTspice” available at
`https://en.wikipedia.org/wiki/LTspice (accessed on July 17,
`2019)
`
`APPLE-1024
`
`John F. Wakerly, DIGITAL DESIGN PRINCIPLES AND PRACTICES
`4th Ed. (2006)
`
`
`
`iii
`
`
`
`Proceeding No.: IPR2018-01316
`Attorney Docket: 39521-0053IP2
`
`APPLE-1025
`
`Bruce Jacob, ENEE 359a Digital VLSI Design - Transistor
`Sizing & Logical Effort, available at
`https://ece.umd.edu/courses/enee359a.S2007/ (Internet Archive
`cached version of this address demonstrating presentation was
`available at least as early as July 4, 2008)
`
`
`
`
`
`iv
`
`
`
`Proceeding No.: IPR2018-01316
`Attorney Docket: 39521-0053IP2
`
`I. The Board’s Precedent Clearly Articulates that Grounds in an IPR May Be
`Based on AAPA
`
`Relevant only to Ground 2, Patent Owner argues that the America Invents
`
`Act (AIA) does not permit inter partes review based on so-called Applicant’s
`
`Admitted Prior Art (AAPA). POR (Paper 12), 18-20. This argument mimics the
`
`argument advanced in the Patent Owner Preliminary Response, with one
`
`exception—Patent Owner now additionally asserts that arguments made by
`
`Petitioner’s counsel on behalf of an entirely different party in a different
`
`proceeding (IPR2017-00126) support its position. Compare POPR (Paper 6), 34-
`
`35 to POR, 18-20. No new legal authority has been identified by Patent Owner.
`
`Thus, Patent Owner provides no basis upon which the Board should revisit the
`
`position expressed in the Institution Decision (“ID”) that AAPA is an eligible
`
`ground for an IPR. ID (Paper 7), 22.
`
`In its ID in this proceeding, the Board diligently followed the logic
`
`articulated by the panel in IPR2017-00126 regarding the availability of AAPA. Id.
`
`In the final written decision in IPR2017-00126, the panel explained that the same
`
`language used in 35 U.S.C. § 311(b) (i.e., “prior art consisting of patents or printed
`
`publications”) was previously used by Congress to restrict the prior art available
`
`for use in pre-AIA reexamination proceedings. APPLE-1020, 37-38. Yet, the
`
`panel found that, “despite this restriction on the prior art that could be cited in pre-
`
`
`
`1
`
`
`
`Proceeding No.: IPR2018-01316
`Attorney Docket: 39521-0053IP2
`
`AIA reexamination proceedings, the Federal Circuit nonetheless found that AAPA
`
`could be cited and relied upon to support the Board’s findings in such
`
`proceedings.” APPLE-1020, 38 (citing In re NTP, Inc., 654 F.3d 1279, 1304 (Fed.
`
`Cir. 2011)). In other words, the exact same language used in 35 U.S.C. § 311(b) to
`
`define eligible prior art has been previously held by the Federal Circuit to
`
`encompass AAPA.
`
`Because Patent Owner fails to advance any new arguments that were not
`
`otherwise addressed by the ID or by the panel’s decisions in IPR2017-00126,
`
`Patent Owner’s arguments regarding the availability of AAPA in IPRs should be
`
`dismissed.
`
`II. Explicit Motivation to Combine the AAPA with Majcherczak, as Described
`in the Prior Art, Is Not Obviated by Potential Disadvantages of the
`Combination Alleged by Patent Owner
`
`Beyond this procedural issue, Patent Owner’s only substantive argument
`
`challenging Ground 2 is a purported lack of motivation to combine. This argument
`
`does not account for, much less traverse, motivation taught in Majcherczak.
`
`In establishing its prima facie case to combine the AAPA with Majcherczak,
`
`the Petition explained that “[a] POSITA would have been motivated to integrate
`
`the feedback transistor M6 from Majcherczak’s voltage detector into the POC
`
`system 10 of the AAPA in order to ‘enable[] the proper stabilizing of the detection
`
`device,’” through hysteresis, as described in Majcherczak itself. Pet., 53 (citing
`
`
`
`2
`
`
`
`Proceeding No.: IPR2018-01316
`Attorney Docket: 39521-0053IP2
`
`APPLE- 1008, ¶0037; APPLE-1003, ¶150). This proposed combination was based
`
`on an explicit motivation in the prior art itself, ensuring hindsight is not at issue.
`
`See id. Indeed, hindsight was not accused by Patent Owner. See generally POR
`
`20-31. In its Institution Decision, the Board found “Petitioner sufficiently
`
`demonstrates . . . that a person of ordinary skill in the art had a reason to combine
`
`the teachings of [the AAPA with Majcherczak] with a reasonable expectation of
`
`success.” ID, 26.
`
`Patent Owner does not dispute that the proposed integration of
`
`Majcherczak’s feedback transistor M6 into the AAPA would achieve the
`
`advantages of hysteresis described in the prior art. See generally POR, 20-31; Ex.
`
`2002, ¶¶67-85. Instead, Patent Owner alleges disadvantages surmised to arise in
`
`the proposed combination to reach its allegation that “there is no conceivable
`
`reason why a POSA would be motivated to make Petitioner’s proposed
`
`combination.” POR, 31. Yet, these arguments are legally improper and factually
`
`unsupported.
`
`A. There Exists Explicit Motivation in Majcherczak to Combine the
`AAPA and Majcherczak
`
`Ground 2 demonstrates that a POSITA would have had a reason to
`
`incorporate the feedback transistor M6 from Majcherczak into the AAPA power
`
`up/down detector. Majcherczak provides an explicit motivation to add its feedback
`
`
`
`3
`
`
`
`Proceeding No.: IPR2018-01316
`Attorney Docket: 39521-0053IP2
`
`transistor M6 to a power detection circuit in a multi-supply voltage environment,
`
`teaching that “positive pull-down transistor M6 enables the proper stabilizing of
`
`the detection device.” APPLE-1008, ¶¶0013, 0037. Majcherczak also describes
`
`that the stabilization of the detection device is a result of the hysteresis introduced
`
`into the detection device from the presence of feedback transistor M6. See
`
`APPLE-1008, ¶0038; see also APPLE-1003, ¶150. As explained by Petitioner’s
`
`expert, Dr. Horst, a POSITA would have known that the hysteresis detection taught
`
`by Majcherczak “is useful for ensuring that the level shifters only operate to
`
`facilitate communications between the core network and the I/O network when the
`
`core supply voltage is stably on.” APPLE-1003, ¶¶51-55, 138; see also APPLE-
`
`1024, 87-89. In other words, a POSITA would have understood that Majcherczak
`
`explicitly teaches an advantage in adding a feedback transistor M6 to a circuit with
`
`a purpose and architecture nearly identical to the circuit disclosed in the AAPA.
`
`See APPLE-1003, ¶¶129, 140 (describing how “the signals observed at the output
`
`of the input stage E1 (Nin) and at the output of the inverter IV in Majcherczak’s
`
`voltage detector are effectively the same those observed at the output of the power
`
`up/down detector and at the output of the inverting amplifier 105 of the AAPA’s
`
`POC system 10”).
`
`Thus, the combination of the AAPA and Majcherczak is no more than the
`
`use of a known technique (a feedback transistor to provide hysteresis) to improve
`
`
`
`4
`
`
`
`Proceeding No.: IPR2018-01316
`Attorney Docket: 39521-0053IP2
`
`similar devices (detection circuits in multiple supply voltage devices) in the same
`
`way taught in the prior art. APPLE-1003, ¶151; see also KSR Int’l Co. v. Teleflex
`
`Inc., 550 U.S. 398, 417 (2007) (“if a technique has been used to improve one
`
`device, and a person of ordinary skill in the art would recognize that it would
`
`improve similar devices in the same way, using the technique is obvious unless its
`
`actual application is beyond his or her skill.”). Moreover, as noted above, both
`
`references relate to multiple supply voltage devices, and are thus analogous art. In
`
`re Bigio, 381 F.3d 1320, 1325 (Fed. Cir. 2004).
`
`It is undisputed in the POR or by Dr. Pedram that adding Majcherczak’s
`
`feedback transistor M6 to the AAPA as described in the Petition achieves the
`
`advantageous hysteresis described in Majcherczak. See generally POR, 20-31; Ex.
`
`2002, ¶¶67-85. In fact, Dr. Pedram admits that it was possible to add hysteresis to
`
`the AAPA circuit shown in FIG. 1 of the ’674 Patent, and that such an addition
`
`could help improve noise immunity of the circuit. APPLE-1017, 46:22-47:10 (“If
`
`someone told you to solve a noise immunity problem by adding hysteresis to the
`
`prior art Figure 1 circuit in the ’674 patent, in 2001, how would you have gone
`
`about adding hysteresis to that circuit? A. . . . one could potentially use feedback to
`
`create that kind of different response to different transitions that you have. Again,
`
`yes, it’s possible to do. And one could try to do some of these things, yes.”
`
`(emphasis added)).
`
`
`
`5
`
`
`
`Proceeding No.: IPR2018-01316
`Attorney Docket: 39521-0053IP2
`
`Patent Owner’s argument that the inventors of the ’674 patent added the
`
`feedback circuit to the AAPA for a purpose other than hysteresis—purportedly, “to
`
`reduce leakage current while also improving power-up/down detection speed”—
`
`does not make the Challenged Claims any less obvious to a POSITA. “The reason
`
`or motivation to modify a reference may often suggest what the inventor has done,
`
`but for a different purpose or to solve a different problem.” MPEP § 2144(IV). It
`
`is not necessary that the prior art suggest the combination to achieve the same
`
`advantage or result purportedly discovered by the Patent Owner. See, e.g., In re
`
`Kahn, 441 F.3d 977, 987 (Fed. Cir. 2006) (motivation question arises in the
`
`context of the general problem confronting the inventor rather than the specific
`
`problem solved by the invention); Cross Med. Prods., Inc. v. Medtronic Sofamor
`
`Danek, Inc., 424 F.3d 1293, 1323 (Fed. Cir. 2005) (“One of ordinary skill in the art
`
`need not see the identical problem addressed in a prior art reference to be
`
`motivated to apply its teachings.”). In other words, KSR’s “technique . . . used to
`
`improve one device” need not be the same improvement sought by the inventor of
`
`a challenged patent. Thus, it is irrelevant whether the prior art’s explicit
`
`motivation to integrate Majcherczak’s feedback transistor M6 into the AAPA
`
`matches the problem statement of the ’674 Patent. Cross Med. Prods., 424 F.3d at
`
`1323. The POSITA had a stated reason to incorporate feedback into the AAPA,
`
`and the resulting circuit renders the Challenged Claims obvious.
`
`
`
`6
`
`
`
`Proceeding No.: IPR2018-01316
`Attorney Docket: 39521-0053IP2
`
`B. The Motivation of Gaining Hysteresis in the AAPA is Not Obviated
`by Patent Owner’s Allegations of Potential Disadvantage Arising
`from the Combination
`
`At best, Patent Owner’s arguments of alleged disadvantages flowing from
`
`the combination of AAPA and Majcherczak is a “teaching away”-type defense. “A
`
`reference may be said to teach away when a person of ordinary skill, upon reading
`
`the reference, would be discouraged from following the path set out in the
`
`reference, or would be led in a direction divergent from the path that was taken by
`
`the applicant.” In re Gurley, 27 F.3d 551, 553 (Fed. Cir. 1994) (emphasis added).
`
`However, neither the POR nor Dr. Pedram cite to any references to support the list
`
`of disadvantages that are proclaimed as allegedly arising from the Petition’s
`
`combination of AAPA with Majcherczak. Rather, Dr. Pedram’s list of potential
`
`disadvantage is at best hypothetical, as he admits that he never simulated any of the
`
`prior art or proposed combinations to determine what, if any, performance issues
`
`would arise from the proposed combination.1 See APPLE-1017, 40:15-41:13,
`
`167:20-23, 171, 20-172:1, 180:6-16; see also id. at 45:9-15, 59:4-8, 61:4-10, 65:7-
`
`14, 170:13-17, 187:25-188:9 (generally reiterating the standard practice of
`
`
`1 In contrast, Dr. Horst provides analysis in his supplemental declaration of
`
`simulations challenging each of Dr. Pedram’s alleged disadvantages, as discussed
`
`infra.
`
`
`
`7
`
`
`
`Proceeding No.: IPR2018-01316
`Attorney Docket: 39521-0053IP2
`
`simulating circuits). Without corroborating evidence to contradict the explicit
`
`motivating teaching of Majcherczak, Dr. Pedram’s statements are unsupported,
`
`exposing them as insufficient to establish substantial evidence addressing or
`
`confronting the affirmative proof offered by Petitioner. Ericsson Inc. v.
`
`Intellectual Ventures I LLC, 890 F. 3d 1336, 1346 (Fed. Cir. 2018) (“To contradict
`
`a reference, an unsupported opinion is not substantial evidence.”)
`
`Even assuming, arguendo, that Dr. Pedram’s allegations regarding the
`
`disadvantages were entitled to any weight, which they should not be, they fail to
`
`demonstrate the absence of motivation. It is well understood that “a given course
`
`of action often has simultaneous advantages and disadvantages, and this does not
`
`necessarily obviate motivation to combine.” Medichem, S.A. v. Rolabo, S.L., 437
`
`F.3d 1157, 1165 (Fed. Cir. 2006) (citing Winner Int’l Royalty Corp. v. Wang, 202
`
`F.3d 1340, 1349 n. 8 (Fed. Cir. 2000) (“The fact that the motivating benefit comes
`
`at the expense of another benefit, however, should not nullify its use as a basis to
`
`modify the disclosure of one reference with the teachings of another. Instead, the
`
`benefits, both lost and gained, should be weighed against one another.”). Here, the
`
`explicit benefit articulated in Majcherczak is not undone or outweighed by the
`
`vague and unsupported disadvantages described in the POR and by Dr. Pedram.
`
`As a technical matter, none of the Patent Owner’s hypothetical
`
`disadvantages presents a legitimate challenge to the implementation of the
`
`
`
`8
`
`
`
`Proceeding No.: IPR2018-01316
`Attorney Docket: 39521-0053IP2
`
`proposed combination of AAPA and Majcherczak. The Patent Owner identified:
`
`(1) increased leakage current resulting from the proposed integration of
`
`Majcherczak’s feedback transistor M6 into the AAPA; (2) increased glitch current
`
`from the proposed integration; and (3) the creation of a DC fighting condition from
`
`the proposed integration. See generally POR, 21-31. In each case, Dr. Pedram
`
`admits, and Dr. Horst confirms, that any such problem is not inherent in the
`
`proposed architectural combination. Rather, such issues would only potentially
`
`arise due to an improper selection of design characteristics such as the transistor
`
`sizes, threshold voltages, and values of VI/O and Vcore.. APPLE-1018, ¶¶7-9, 74-77.
`
`Thus, even if Patent Owner is correct that these problems exist, Patent Owner
`
`nevertheless fails to demonstrate that they impact all implementations of a circuit
`
`resulting from the combination, nor that a POSITA would fail to be motivated for
`
`reasons demonstrated by Petitioner to achieve noted advantages in at least one
`
`specific implementation of the circuit, which is legally sufficient to support the
`
`proposed combination of the references.
`
`Dr. Pedram acknowledged that the ’674 Patent does not describe specific
`
`implementation details such as transistor sizes, threshold voltages, or values of VI/O
`
`and Vcore for any of its proposed designs, much less dictate limitations on these
`
`values in the claims. See APPLE-1017, 40:15-41:2, 69:11-76:3. Instead the ’674
`
`Patent leaves these details to the designer. See id. As Dr. Horst explained in his
`
`
`
`9
`
`
`
`Proceeding No.: IPR2018-01316
`Attorney Docket: 39521-0053IP2
`
`original declaration, “the fact that the ’674 Patent does not give guidance in the
`
`selection of these key parameters indicates that a POSITA should be assumed to
`
`have sufficient skill in circuit design to understand and modify circuits in a way
`
`that a POSITA would be able to select the appropriate parameters, or to construct
`
`stacks of transistors to obtain the desired and useful power detection functionality
`
`described in the ’674 Patent.” APPLE-1003, ¶41.
`
`With regard to the first alleged problem of additional leakage current, Dr.
`
`Pedram acknowledged that it is the unclaimed design details—transistor sizes,
`
`threshold voltages, and values of VI/O and Vcore—that will determine the amount of
`
`leakage present in the proposed combination. See APPLE-1017, 63:22-65:20. As
`
`Dr. Horst shows through simulation of these designs, proper selection of the
`
`transistor sizes, threshold voltages, and values of VI/O and Vcore would allow a
`
`POSITA implementing the proposed combination to mitigate any potentially
`
`problematic increase in leakage current, leaving the power consumption due to
`
`leakage current to be relatively the same or even better than either the AAPA or
`
`Majcherczak alone. APPLE-1018, ¶¶50-64, 68-73.
`
`With regard to the second alleged problem of glitch current, the ’674 Patent
`
`acknowledged that glitch current was already a concern in the AAPA circuit shown
`
`in FIG. 1, so the addition of Majcherczak’s feedback transistor would not have
`
`created a new problem in the circuit. See APPLE-1001, 2:25-30; see also APPLE-
`
`
`
`10
`
`
`
`Proceeding No.: IPR2018-01316
`Attorney Docket: 39521-0053IP2
`
`1018, ¶¶31, 56-57, 75-77. As demonstrated by Dr. Horst in his supplemental
`
`declaration through the simulation of these circuits, proper selection of threshold
`
`voltages can mitigate the glitch current problems alleged by Dr. Pedram. APPLE-
`
`2018, ¶¶21-31, 50-64. Moreover, the ’674 Patent describes that it was well known
`
`to balance lower glitch current and switching speed using selection of transistor
`
`sizes. APPLE-1001, 2:31-49. Therefore, the possibility of glitch current in the
`
`proposed combination was manageable and relatively minor, and would not have
`
`dissuaded a POSITA from making the combination. APPLE-2018, ¶¶64, 67.
`
`With regard to the final alleged problem, a DC fighting condition alleged by
`
`the Patent Owner to “potentially result[] in a complete circuit breakdown” (POR,
`
`29-30), Dr. Pedram admits that this situation “could happen” only on “rare
`
`occasions,” making any assessment of a hypothetical DC fighting condition a
`
`“complicated task.” APPLE-1017, 181:10-24. The condition is so complicated
`
`and rare, in fact, that Dr. Pedram believes that a POSITA would not even see or be
`
`aware of this disadvantage when analyzing the proposed combinations. APPLE-
`
`1017, 175:11-15 (“And the POSA would not even be aware of a DC fighting
`
`situation. I guarantee you. Very high likelihood a POSA looking at this wouldn’t
`
`even see where the problems are. Potential problems he would even try to address.
`
`He wouldn’t see it.”). A POSITA cannot have been dissuaded by a potential,
`
`“rare” problem he/she would not even have been aware of. Regardless, Dr.
`
`
`
`11
`
`
`
`Proceeding No.: IPR2018-01316
`Attorney Docket: 39521-0053IP2
`
`Pedram acknowledged that this condition would likewise be completely dependent
`
`on proper selection of the transistor sizes, threshold voltages, and values of VI/O
`
`and Vcore, and this alleged problem did not arise in Dr. Horst’s simulations. See
`
`APPLE-1017, 172:10-173:16, 178:9-181:24; see also APPLE-1018, ¶¶30, 32-33.
`
`Even assuming a POSITA would have considered these as potential
`
`disadvantages in implementing the proposed combination, the POSITA would
`
`nevertheless have been motivated for reasons cited within Majcherczak to make
`
`the combination, as the POR’s alleged disadvantages and their potential adverse
`
`impacts either would not have been observed or a POSITA would have been able
`
`to minimize them. APPLE-1018, ¶¶50-64. Further, as Dr. Horst demonstrates in
`
`his simulations, there exist common circumstances (e.g., a noisy supply voltage) in
`
`which a POSITA would have been motivated to gain the advantage of adding
`
`hysteresis to the AAPA even if the problems alleged in the POR would have
`
`persisted, as the problems solved by hysteresis would have directly impacted the
`
`intended operation of the circuit while the POR’s alleged problems would not.
`
`APPLE-1018, ¶67.
`
`III. Explicit Motivation in the Prior Art to Combine Steinacker, Doyle, and
`Park is Not Obviated by Potential Disadvantages of the Combination
`Alleged by Patent Owner
`
`As to Ground 1, Patent Owner’s only substantive argument is again
`
`regarding motivation to combine. In setting forth Ground 1, the Petition explained
`
`
`
`12
`
`
`
`Proceeding No.: IPR2018-01316
`Attorney Docket: 39521-0053IP2
`
`the motivation to combine Steinacker, Doyle, and Park. Pet., 20-21. The
`
`Institution Decision asked the parties to address with particularity during the trial
`
`the following issues: (1) whether impermissible hindsight was used in the selection
`
`and combination of the prior art, (2) whether the reasons given in the Petition are
`
`generic statements divorced from the prior art elements or focus on the specific
`
`references used, and (3) whether a person of ordinary skill in the art would have
`
`selected the forced stack technique over the sleepy stack technique. Id. at 40.
`
`Each of these is addressed below, confirming a POSITA was motivated to make
`
`the proposed combination.
`
`A. Explicit Teachings in Steinacker, Doyle, and Park Motivate the
`Combination Set Forth in the Petition
`
`A complete review of the references and the evidence of record
`
`demonstrates that Steinacker, Doyle, and Park are indeed “pieces of a puzzle” and
`
`that “evidence before the time of invention” sets forth a motivation to combine
`
`these puzzle pieces exactly as set forth in the Challenged Claims, demonstrating
`
`that the proposed combination does not rely upon hindsight.
`
`Under KSR, an obviousness analysis “need not seek out precise teachings
`
`directed to the specific subject matter of the challenged claim, for a court can take
`
`account of the inferences and creative steps that a person of ordinary skill in the art
`
`would employ.” KSR, 550 U.S. at 417-418 (2007). Indeed, “in many cases a
`
`
`
`13
`
`
`
`Proceeding No.: IPR2018-01316
`Attorney Docket: 39521-0053IP2
`
`person of ordinary skill will be able to fit the teachings of multiple patents together
`
`like pieces of a puzzle.” Id. at 420. Interpreting KSR, the Federal Circuit has held
`
`that “a flexible approach to the [teaching, suggestion, and motivation] test prevents
`
`hindsight and focuses on evidence before the time of invention, without unduly
`
`constraining the breadth of knowledge available to one of ordinary skill in the art
`
`during the obviousness analysis.” In re Translogic Technology, Inc., 504 F.3d
`
`1249, 1260 (Fed. Cir. 2007) (internal citations omitted).
`
`As described in the Petition, Steinacker and the ’674 Patent both address
`
`systems having at least two circuit blocks operating at different supply voltages,
`
`and both describe using a power detection circuit to ensure reliable operation when
`
`the different supply voltages are turned on and off independently of one another.
`
`Compare APPLE-1005, 1:49-52, 2:14-43, 4:45-64 to APPLE-1001, 1:12-54, 1:55-
`
`58; see also Pet., 10-11. In Steinacker, the power detection circuit is the voltage
`
`detector 5, and in the ’674 Patent, the power detection circuit is the power-on/off-
`
`control (POC) system 10. Id. A comparison of FIG. 3A of the ’674 Patent
`
`(reproduced below on top) and FIG. 1 of Steinacker (reproduced below on bottom)
`
`illustrate the similarities between these two systems.
`
`
`
`14
`
`
`
`Proceeding No.: IPR2018-01316
`Attorney Docket: 39521-0053IP2
`
`
`
`For these reasons, Steinacker is clearly analogous art to the ’674 Patent, as it
`
`is in the same field of endeavor as the claimed invention. Bigio, 381 F.3d at 1325.
`
`Thus, there is no merit to Patent Owner’s argument that “none of the references are
`
`relevant to the specific invention recited in independent claim 1.” POR, 34.
`
`
`
`15
`
`
`
`Proceeding No.: IPR2018-01316
`Attorney Docket: 39521-0053IP2
`
`Though Steinacker does not depict the transistor-level arrangement of its
`
`voltage level detector 5, Steinacker gives the POSITA explicit instructions as to
`
`which well-known circuits could be used. Specifically, Steinacker describes that
`
`“the voltage level detector 5 is in the form of a Schmitt trigger with an inverting
`
`output. However, it is likewise conceivable for the voltage level detector 5 to be in
`
`the form of an inverter circuit, a comparator circuit or comparable circuits.”
`
`APPLE-1005, 4:49-53 (emphasis added); see also Pet., 12. Describing his work
`
`from 2001—eight years before the Critical Date—Dr. Pedram acknowledged that
`
`he personally used an inverter circuit as a “power up/down detector” in a circuit
`
`with “multiple voltage domains” in which “some of the power domains could be
`
`independently turned on and off”—the same circumstance described in Steinacker.
`
`APPLE-1017, 28:5-19, 29:3-31:5, 137:8-14.2 Steinacker’s omission of the
`
`transistor-level details of the voltage level detector 5 confirms that Steinacker left
`
`implementation of its circuit to POSITAs, with the expectation that such POSITAs
`
`were capable of implementing a Schmitt trigger, inverter circuit, comparator circuit
`
`
`2 This testimony directly contradicts Patent Owner’s passing assertion that “none
`
`of the references applied in Ground 1 discloses an up/down detector,” as
`
`Steinacker’s use of an inverter clearly does. POR, 34.
`
`
`
`16
`
`
`
`Proceeding No.: IPR2018-01316
`Attorney Docket: 39521-0053IP2
`
`or comparable circuit as voltage level detector 5. Pet., 12 (citing APPLE-1003,
`
`¶93).
`
`In FIG. 1, Steinacker provides further guidance to direct a POSITA in the
`
`selection of an appropriate voltage level detector 5. As Dr. Pedram described, FIG.
`
`1 of Steinacker depicts the voltage level detector 5 as “a triangle with a bullet at
`
`the end that shows it’s inverting. And this particular notation which I describe to
`
`you to indicate there’s hysteresis between the falling and rising trip point of this
`
`inverter.” APPLE-1017, 135:10-136:2, 139:6-14; see also APPLE-1018, ¶¶34-36.
`
`Annotated Excerpt of Steinacker FIG. 1
`
`
`
`Here, even Dr. Pedram acknowledges that Steinacker recommends a voltage
`
`level detector 5 that has both an inverting output and hysteresis, leading a POSITA
`
`away from a conventional two-transistor invertor (e.g., as shown in FIG. 2A of
`
`
`
`17
`
`
`
`Proceeding No.: IPR2018-01316
`Attorney Docket: 39521-0053IP2
`
`Doyle) that Patent Owner incorrectly alleges would have been a more obvious
`
`choice. See POR, 44; see also APPLE-1018, ¶39. The prior art thus sets forth an
`
`explicit motivation to incorporate an inverter circuit with hysteresis as the voltage
`
`level detector in Steinacker’s multiple supply voltage system.
`
`A POSITA seeking an inverter circuit with hysteresis for use as a voltage
`
`level detector in a multiple supply voltage system would naturally have considered
`
`Doyle’s inverter circuit, which satisfies each of these requirements. APPLE-1018,
`
`¶40. Doyle describes a multiple supply voltage system3 that uses an inverter with a
`
`feedback circuit to perform voltage level detection with hysteresis. See APPLE-
`
`1006, 2:37-46, 3:7-14; see also APPLE-1018, ¶40. Specifically, Doyle’s improved
`
`inverter of FIG. 2 includes a “second P-channel pullup MOSFET . . . provided in
`
`parallel with the first, and has its gate coupled to a feedback signal produced by a
`
`second CMOS inverting stage in order to provide a ‘polarized’ hysteresis
`
`characteristic of the MOS level shifting circuit, making the trip point or switching
`
`point of the MOS level shifting circuit relatively independent of the power supply
`
`voltage applied across the CMOS level shifting circuit.” APPLE-1006, 3:7-14
`
`(emphasis added).
`
`
`3 The TTL and CMOS logic levels referred to in Doyle are based on two different
`
`standard voltages. APPLE-1018, ¶40.
`
`
`
`18
`
`
`
`Proceeding No.: IPR2018-01316
`Attorney Docket: 39521-0053IP2
`
`
`
`The feedback transistor 18 in FIG. 2 is the source of the hysteresis effect, and
`
`provides Doyle’s advantage of a “stable trip point or switching point.” See id.; see
`
`also APPLE-1018, ¶40. Dr. Pedram agreed that “Doyle sets forth in his
`
`background section the idea that hysteresis can be achieved in the input circuitry of
`
`an integrated circuit chip using a feedback transistor.” APPLE-1017, 133:17-21;
`
`see also id., 125:21-126:
Accessing this document will incur an additional charge of $.
After purchase, you can access this document again without charge.
Accept $ Charge
Still Working On It
This document is taking longer than usual to download. This can happen if we need to contact the court directly to obtain the document and their servers are running slowly.
Give it another minute or two to complete, and then try the refresh button.
A few More Minutes ... Still Working
It can take up to 5 minutes for us to download a document if the court servers are running slowly.
Thank you for your continued patience.
This document could not be displayed.
We could not find this document within its docket. Please go back to the docket page and check the link. If that does not work, go back to the docket and refresh it to pull the newest information.
Your account does not support viewing this document.
You need a Paid Account to view this document. Click here to change your account type.
Your account does not support viewing this document.
Set your membership
status to view this document.
With a Docket Alarm membership, you'll
get a whole lot more, including:
- Up-to-date information for this case.
- Email alerts whenever there is an update.
- Full text search for other cases.
- Get email alerts whenever a new case matches your search.
One Moment Please
The filing “” is large (MB) and is being downloaded.
Please refresh this page in a few minutes to see if the filing has been downloaded. The filing will also be emailed to you when the download completes.
Your document is on its way!
If you do not receive the document in five minutes, contact support at support@docketalarm.com.
Sealed Document
We are unable to display this document, it may be under a court ordered seal.
If you have proper credentials to access the file, you may proceed directly to the court's system using your government issued username and password.
Access Government Site
