UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`APPLE INC.,
`Petitioner,
`
`v.
`
`QUALCOMM INCORPORATED,
`Patent Owner.
`____________
`
`Case IPR2018-01315
`Case IPR2018-01316
`Patent 8,063,674 B2
`____________
`
`Record of Oral Hearing
`Held: October 11, 2019
`___________
`
`
`Before TREVOR M. JEFFERSON, DANIEL J. GALLIGAN, and
`SCOTT B. HOWARD, Administrative Patent Judges.
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`
`
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`APPLE INC.,
`Petitioner,
`
`v.
`
`QUALCOMM INCORPORATED,
`Patent Owner.
`____________
`
`Case IPR2018-01315
`Case IPR2018-01316
`Patent 8,063,674 B2
`____________
`
`Record of Oral Hearing
`Held: October 11, 2019
`___________
`
`
`Before TREVOR M. JEFFERSON, DANIEL J. GALLIGAN, and
`SCOTT B. HOWARD, Administrative Patent Judges.
`
`
`
`
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`
`
`Case IPR2018-01315
`Case IPR2018-01316
`Patent 8,063,674 B2
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`
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`APPEARANCES:
`
`ON BEHALF OF THE PETITIONER:
`
`
`W. KARL RENNER, ESQUIRE
`WHITNEY A. REICHEL, ESQUIRE
`DAVID L. HOLT, ESQUIRE
`FISH & RICHARDSON, P.C.
`One Marina Park Drive
`Boston, Massachusetts 02210-1878
`
`
`
`ON BEHALF OF THE PATENT OWNER:
`
`JOSEPH M. SAUER, ESQUIRE
`DAVID B. COCHRAN, ESQUIRE
`JONES DAY
`901 Lakeside Avenue
`Cleveland, Ohio 44114
`
`
`
`
`The above-entitled matter came on for hearing on October 11, 2019,
`commencing at 10:00 a.m., at the U.S. Patent and Trademark Office,
`Madison Building, 600 Dulany Street, Alexandria, Virginia, 22314.
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`Case IPR2018-01316
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` (Proceedings begin at 10:00 a.m.)
` JUDGE HOWARD: Good morning. This is an oral
`hearing for case numbers IPR2018-01315 and IPR2018-01316
`between the petitioner, Apple Inc., and patent owner,
`Qualcomm Incorporated, concerning United States Patent
`8,063,674.
` I'm Judge Howard. Joined with me is Judge Jefferson
` in Alexandria, and Judge Galligan in Dallas.
` And just a few administrative matters before we
` begin.
` Per our hearing order, each side will have 60
` minutes to present its case. Petitioner will proceed first
` and may reserve up to half its time for rebuttal.
` Once petitioner has finished its initial
` presentation, patent owner may proceed with its case.
` If petitioner reserves time for rebuttal, patent
` owner can reserve time for a brief sur-rebuttal.
` For the sake of the judges who are participating
` remotely, we cannot see the screen in the courtroom, but we
` have your slides. So for clarity and so that we're able to
` look exactly at what you want us to look at, could you
` please refer to the slide number during your presentation so
` that we can follow along.
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` If you have any objections, we ask that you do not
` interrupt each other during the proceedings. Please save
` time for them during your argument time and we can address
` them at that point.
` At this time, I'd like counsel to introduce
` yourselves and who you have with you.
` If you could begin with petitioner.
` MR. RENNER: Good morning, Your Honors. This is
`Karl Renner from Fish & Richardson, and I am joined by three
`colleagues; Tom Rozylowicz, who will begin speaking today,
`David Holt, who will follow, and Whitney Reichel.
` And Your Honor, if we could, as for formalities,
` we'll want to reserve 25 minutes for rebuttal.
` JUDGE HOWARD: Okay.
` MR. RENNER: And if I may approach the bench with a
`written copy of the materials?
` JUDGE JEFFERSON: Yes, please.
` JUDGE HOWARD: You may.
` And patent owner?
` MR. SAUER: Good morning, Your Honors. Joe Sauer
`for patent owner Qualcomm.
` With me today is my colleague, Dave Cochran, who
`will be presenting today, and Allen Eaton, who is helping
`with the slides.
` Also in the courtroom are representatives from
` patent owner Qualcomm.
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` If I can approach?
` JUDGE HOWARD: Thank you. And how much time does
`patent owner want to reserve for sur-rebuttal?
` MR. SAUER: 15 minutes, please.
` MR. RENNER: Your Honor, as one more formality, just
`to assist everyone in the courtroom, including opposing
`counsel. There will be two exhibits outside of the
`demonstratives that might be easier for you to load. I know
`you're remote so it will be harder for you to see.
` So it's Apple 1007, page 2, and Apple 1017,
`page 175.
` JUDGE HOWARD: Thank you.
` MR. RENNER: You bet.
` JUDGE HOWARD: All right. You may begin.
` MR. ROZYLOWICZ: Good morning, Your Honor. My name
`is Tom Rozylowicz, and I'd like to briefly speak to a little
`bit of the background of the '674 patent.
` Slide 3, please.
` And when we speak to the background of the '674
` patent, we're really speaking to a situation in which we
` have processors that are operating at one class of voltages,
` that is the core, and I/O devices that are operating at a
` different class of voltages, that would be V I/O.
` Now, when we have systems that include both I/O and
` core systems together, one of the things that's been done is
` the desire to turn down -- turn off the microprocessors when
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` they're not in use, thus to achieve further power savings.
` But when we have -- also have multiple -- systems at
` multiple voltage settings like this, one of the things that
` can occur is when these systems are -- have the potential to
` be spun off like this, the detector circuits can sometimes
` achieve erroneous inputs, and as a result of that, when the
` state of the core processer is uncertain, it can be used to
` achieve -- or it can cause complications with improperly
` reading a datos (sounds like) that when the processer in
` fact should be turned off.
` Further, the process of toggling the core processer
` on and off can be wildly inefficient from a power
` perspective.
` Now, looking at Figure 1 in the left, we see the
` power up detector that appears in the left-hand side. This
` is from the slide -- Figure 1 labeled "Prior Art in the '674
` Patent".
` In addition, we have the feedback network that
` appears from Figure 4, and that's used to -- it can be used
` to provide further stability.
` Now, the patent owner repeatedly tried to argue that
` the feedback network would be the basis for allowance, and
` the Office refused to accept that as a basis for novelty.
` Instead, it was only when the three transistors were
` clarified to be part of the power up/down detector on the
` left-hand side that the case was actually allowed.
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` So any arguments that would suggest that the state
` of the feedback network was in fact novel should be
` discounted as that position was previously rejected by the
` Office.
` Then to Slide 2.
` I'd like to identify the set of issues that we'll be
` speaking to today, but first I think it's important to speak
` to what's not in dispute today.
` There's no argument about claim construction,
` there's no argument about whether any particular limitation
` of the independent claims is not met by the prior art,
` there's no argument about whether there is a reasonable
` expectation of success, and there's no argument about
` secondary considerations.
` The only issue before us today is whether there
` exists motivation to combine with each of the proposed
` combinations.
` Turning to Slide 11, please.
` So we then turn, at least for the first ground of
` rejection, I'll be speaking to the AAPA combination in
` association with Majcherczak, but my colleague, Mr. Holt,
` will be speaking to the product Park/Steinaker/Doyle
` combination.
` In slide 11 we see the motivation to combine
` Majcherczak and its voltage detector with the AAPA power on
` POC system.
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` In this regard, we see that adding the -- adding the
` feedback network shown on the right-hand side is integrated
` with the POC system shown on the left-hand side in Figure 1.
` By doing this, we know that it achieves hysteresis.
` That it achieves immunity to noise. And we know that noise
` can cause complications that would either improperly toggle
` the circuit or cause erroneous signals to be sent to the I/O
` system, or the I/O system to process them as being
` erroneous.
` So that's actually what we're actually combining.
` The question is, why do we do this combination? And again,
` we're doing this to achieve hysteresis, that is, immunity to
` noise.
` We see that the integration of the feedback
` transistor achieves proper stabilizing. And as we pointed
` out in the petition on page 45, the POC system panel will be
` well served by hysteresis detection. It's motivation to
` combine appearing within Majcherczak itself.
` In 13, we see that Majcherczak is speaking to desire
` to achieve hysteresis in a detection device that is ramping
` up the core voltage.
` Figure 1 of the AAPA is a voltage detection circuit
` and multiple -- of a multiple power system device of the
` type provided by -- or desired by Majcherczak. Thus, we see
` Majcherczak as -- that speaks to a subset of uses within a
` broader domain contemplated by the AAPA detection devices
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` appearing in the AAPA.
` Further, and with respect to Slide 14, we see that
` the record supports the use of hysteresis in these
` environments. Qualcomm's expert, Dr. Pedram, first tells
` you that you would use feedback networks to achieve
` hysteresis. This is a statement in the upper box appearing
` from his deposition.
` Further, Qualcomm, in its sur-reply, speaks that --
` the desire to use Majcherczak in these circumstances as it
` would be an innovative solution at hysteresis.
` Finally, and with respect to Slide 15, we see that
` the third parties also agree. Looking at the graphs on the
` right-hand side, we first see a voltage that is being ramped
` up as V course being elevated. Superimposed over this with
` the sinusoidal wave formats that's gradually increasing, it
` is the impact of noise on the circuit.
` Now, without a feedback network, we only have VT --
` and again, this appears from the Wakerly textbook, I think
` it's Apple Exhibit 1024 -- the impact of noise relative to
` the threshold level that appears at 2.5 volts, we can see
` that although it initially surpasses it in the upper
` left-hand column, noise causes it to drop below the
` threshold voltage, and as a result of that, we see the
` circuit toggle as shown in the middle column in the initial
` dip down about a third of the way through the graph.
` Finally, as we see it gradually increases and still
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` dips below it, we see every time it crosses below that
` threshold voltage, it causes hysteresis.
` And we know hysteresis is very expensive insofar as
` the circuit must be charged up at -- to power up the core
` voltage, and that is a huge power cost for devices that
` could, for example, be used in mobile devices.
` But the impact on hysteresis can't be overstated.
` Hysteresis gives us, in this case, as shown in the upper
` right -- in the upper right-hand graph, it actually gives us
` a threshold voltage in this case of V 2.9 and a lower
` threshold voltage of 2.1.
` As a result of this, it only toggles a circuit when
` it exceeds that level and then goes below it.
` So in this case, the impact of the hysteresis is
` that, instead of having the toggling seen in the middle
` graph, we actually have the clean signal shown below on the
` right-hand column.
` Slide 16, please.
` So taking stock of what we have, let's look at the
` three sources for the motivation to combine.
` First, we look at the references itself, and
` Majcherczak in particular, telling us that we should achieve
` hysteresis.
` Second of all, we look at their experts saying that
` the feedback network would be used to achieve hysteresis.
` Finally, we have the Wakerly textbook that tells us
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` that hysteresis can be used to avoid circuit toggling that
` is introduced as stability and avoids improper toggling.
` Slide 19, please.
` So Qualcomm would have asked us to account for three
` design considerations in this combination.
` First, they would tell us that there would be more
` leakage current than the AAPA itself.
` Second, they tell us there would be more leakage
` current than Majcherczak itself.
` Third, they speak to two other complications; that
` of an increased glitch current, and also the DC fighting
` condition.
` So before we speak to each of these design
` considerations in and of itself, I'd like to pause and take
` stock of what we've already considered.
` First, these design considerations are the same
` magnitude as with --
` First, these design considerations and the magnitude
` are the same are alleged with the support of Dr. Pedram
` alone and without any corroboration. As we'll speak to, on
` further review, when he was deposed, Dr. Pedram indicated
` that a POSITA wouldn't even be aware of some of these
` criteria.
` Second, and during the same deposition, Dr. Pedram
` indicated that when one was dealing with these design
` considerations in the context of how he would task some of
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` his graduate students to go about these assignments, he
` indicated that they would simply go off and model different
` values for different parameters in order to make it work.
` It's his routine. Indeed, not even necessarily at the level
` of a POSITA. Rather, this was simply in a classroom
` environment, how he would have his students go about and try
` and model a solution that would make these work.
` Next slide, please.
` On Slide 20, we see why these aspects are not
` obstacles to giving the combination of AAPA and Majcherczak
` operational.
` And so first, in Slide 20, we actually see that
` Pedram says, "The impact of leakage can be mitigated by
` POSITAs."
` Please, again, understand that during this question
` and answer period during his deposition, we're asking him to
` speak to Figure 1 of the AAPA.
` We asked him in this context if he was asking his
` class to engage on how you would go about implementing a
` solution based on AAPA Figure 1.
` We asked him, and I quote, "Dr. Pedram, if you
` handed one of your graduate students prior art Figure 1 from
` the '674 patent and asked them to propose a method of
` reducing power consumption by any amount, so a small or
` large amount, what would your student have been able to, in
` February 2009, propose ways of reducing power consumption?"
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` (Inaudible) said, "And now take this design and make
` sure you reduce the leakage."
` Dr. Pedram then notes, "And the student would say,
` "What optimization tabs would I have?" I'd say, "You can
` size it and do VT adjustment."
` That is Dr. Pedram, in going about this exercise
` with his class, indicated that he would ask them to adjust
` the size of the transistors that could affect the
` parameters, and he would also ask them to adjust the
` threshold voltages. These are levers that circuit designers
` have in dealing with these concerns.
` Turn to the Slide 21.
` Dr. Pedram goes on. He indicates that he would
` maybe have them -- and I quote -- "Maybe do an exhaustive
` enumeration of different transistor sizes we see in M1, M2,
` and M3 there. Pick the best one, come back, and give it to
` me. Yeah, he could have done that."
` A POSITA would have been able to optimize these
` parameters in order to be able to minimize leakage.
` Turning to Slide 22.
` Our expert, Dr. Horst agrees. He noted that, "It
` was clear, the setting of the Majcherczak thresholds is key
` to making these circuits function as intended."
` Now, mind you, no record evidence has been submitted
` that offer or that suggest that leakage current cannot be
` addressed in the ways proposed above; that is, adjusting the
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` transistor sizes and threshold voltage.
` This means that even if a POSITA had identified
` leakage current as a design criteria, they would have been
` able to -- using tools at their disposal, they would have
` been able to accomplish those design criteria by setting
` transistor size and threshold voltage.
` Turning to Slide 23.
` You see why this is the case and why a POSITA would
` have understood the appropriate transistor values and
` thresholds would mitigate any challenges.
` Dr. Horst points out that the '674 patent provides
` no context or settings for its design. In looking at the
` specification of the '674 patent, it doesn't give you design
` widths or threshold voltages.
` Thus, one would presume that a POSITA, having the
` '674 patent in front of them, would have been expected to
` account for and use their working knowledge of transistor
` theories found in configuration as in environments and
` accounting for that in going about implementing the -- the
` particular solution.
` Now, turning to Slide 26, we see the same holds true
` in dealing with a glitch, that glitch can be mitigated.
` Horst says, and I quote, "It was clear that the
` setting of the MOSFET thresholds was key to making the
` circuit function as intended. Glitch current is reduced to
` a very low value by setting this threshold near the inverter
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` threshold where the feedback network -- where the feedback
` transistor turns off." Thus, with proper thresholds, none
` of these currents -- none of these circuits would have had
` high glitch current or high leakage, and again, there is no
` record evidence to the contrary.
` Slide 25, please.
` And I'd like to speak to the purported DC fighting
` condition.
` Here, we see that POSITAs don't ordinarily mitigate
` because this is a rare condition and that only when you
` don't size the transistors properly.
` Pedram says, and I quote, "It would only arise that
` if you don't do the right sizing and the right threshold
` voltage assignment."
` Further -- and I'm calling your attention to
` Exhibit 1017, page 175, lines 11 through 15 -- we relied
` upon, in page 11 of our reply. In this deposition,
` Dr. Pedram testified, "The POSA would not even be aware of a
` DC fighting condition. I guarantee you very high likelihood
` that a POSA wouldn't look at this, even see where the
` problems are. Potential problems he would even try to
` address. He wouldn't see it.
` So a POSITA wouldn't -- since the DC fighting
` condition wouldn't even have been aware of these conditions,
` according to Dr. Pedram, it couldn't possibly have dissuaded
` them from accounting for this in their design
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` considerations.
` Turning to Slide 27.
` Let's walk through their design considerations that
` they would ask us to account for.
` First, we know from Dr. Horst's testimony that the
` leakage current is about comparable to what he would expect
` it would be, and they could use normal enumeration and
` optimization techniques to account for any challenges that
` arose. This speaks to why the first and second design
` criteria for the -- any purported leakage current over AAPA
` or Majcherczak itself would not preclude the combination.
` Further, we know that, again, through using the same
` optimization and modeling techniques, that the increased
` glitch -- increased glitch current would not cause problems.
` Finally, we know that the DC fighting condition is
` not something that a -- according to Dr. Pedram's testimony,
` that they would even be aware of.
` Again, we've looked at the sum total of their
` evidence as to why Qualcomm believes there's no motivation
` to combine. Again, not that there are -- not that there are
` these problems, rather -- rather, there's a possibility of
` these design criteria that might need to be addressed.
` And turning to Slide 28.
` We believe that we have met our motivation as by
` providing a motivation to combine, and also, underscore that
` with evidence from Drs. Pedram and Horst explaining why the
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` three aspects of leak current -- leakage current, glitch,
` and the DC fighting condition wouldn't discourage a
` combination of AAPA and Majcherczak.
` As we'll discuss -- as we discussed, all these
` circuits will necessarily have some level of leakage and
` glitch. The question is, how much and how we account for
` that in our design process.
` But if we were to -- left with Dr. Pedram's opinions
` alone, we'd have no basis to understand how they could be
` concerns or how we would have to account for these criteria.
` There's simply no record on, beyond alluding to these design
` criteria, how we would account for that.
` And so trying to speak to that and give this
` audience some context, we went to Apple's exert, Dr. Horst;
` went one step further and did the necessary analysis that
` Dr. Pedram failed to undertake. He went into the prior art
` and other references, corroborating evidences such as Voss
` in a related field and looked for comparable settings, such
` as transistor dimension and voltage thresholds.
` In using these models, he then went into spike
` simulation and modeled each of the circuits to account for
` the level of -- to account for the different impact on
` leakage current and glitch to demonstrate that it in fact
` would not be an obstacle to achieving hysteresis going
` forward.
` Again, not that there's not leakage current, not
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` that there's not glitch, but for the benefit of achieving
` hysteresis, these -- he went in there to demonstrate that,
` by accounting for these criteria with design -- with
` transistor size or voltage threshold, these concerns --
` these design criteria could be managed in ways that would
` still allow you to achieve the benefits of hysteresis with
` avoiding -- and thus, avoiding improper circuit detection or
` improper output triggering, as well as the energy costs of
` powering a circuit up.
` Again, Dr. Pedram agreed that Dr. Horst's values
` were appropriate. And in paragraphs -- so again, turning
` then to Slide 29, which is that in paragraph 29, Dr. Horst
` indicates that the spike simulation reveals that the
` differences in current are in the milowatt or microwatt
` range.
` Further, in paragraph 64, Dr. Horst reveals that the
` AAPA/Majcherczak combination results in significant power
` savings.
` Finally, in the third paragraph on the right,
` Dr. Horst reveals that AAPA/Majcherczak combination
` results -- I'm sorry -- is the leak -- leakage current is
` extremely low, and further, the circuit achieves the benefit
` by not pulling down the PN node when the input is falling.
` Qualcomm's protestations regarding these simulations
` are mere attorney argument and are tied to little or no
` weight in the face of Dr. Horst's corroborated and reasoned
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` approach.
` I pause to see if there's any questions. And if
` not, I'll turn the floor over to my colleague, Mr. Holt, who
` will speak to --
` JUDGE HOWARD: Well, I do have a question before you
`move on then. And the question that was raised by patent
`owner in their sur-reply -- and this relates to our ability to
`use applicant admitted prior art -- they point out that at no
`point in the petition or the reply does the petitioner say
`affirmatively that we can rely on applicant admitted art.
` Let us just ask you the question right now, can we rely
` on applicant-admitted prior art during an IPR proceeding?
` MR. ROZYLOWICZ: Your Honor, I think, looking at
`recent cases from the PTAB, we've seen that they have allowed
`petitioners to rely on applicant-admitted prior art. I know
`that this matter is briefed.
` And further (inaudible) the other cases, I don't
`believe that Qualcomm has provided any arguments that would
`distinguish this particular case from other cases where AAPA
`was -- was considered.
` Did that answer your question, Your Honor?
` JUDGE HOWARD: Which doesn't quite answer my
`question. I guess, my question is, is it Apple's position
`that we can consider applicant-admitted prior art, or is it
`taking a position on that?
` MR. ROZYLOWICZ: Yes, Your Honor. We believe
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`that -- that the board can consider applicant-admitted prior
`art.
` JUDGE HOWARD: Thank you.
` MR. ROZYLOWICZ: And if there's no further
`questions, I'll turn the floor over to my colleague,
`Mr. Holt.
` MR. HOLT: All right, Your Honors. So I'll be
`talking today about the next combination which is Steinaker
`in view of Doyle and Park. And that particular combination
`was labeled as Ground 1 in the petition.
` And just like we were talking about with regard to
`the AAPA in view of Majcherczak, the core issue here with
`regard to this combination is whether or not there's
`motivation to combine.
` There's been no argument as to whether or not this
`combination, as it comes together, meets the claim
`limitations, whether or not a person of ordinary skill in the
`art would have a reasonable expectation of success or whether
`there's any secondary considerations to consider. It's
`really just about whether or not there's a motivation to
`combine.
` And if you look to Slide -- we can turn to Slide 40,
` we set out in the our original petition on pages 43 through
` 45 a motivation that starts with Steinaker, looks to Doyle,
` and looks to Park for the motivation for combination.
` And here on Slide 40 we see that in the Institution
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` decision, Your Honors asked several questions about that
` motivation in order to gain clarification about that
` motivation.
` And so in order to answer these questions, we
` thought it would be helpful to actually sit back and walk
` through that motivation with regard to each reference and
` what it teaches and its relevance to the overall system
` that's at issue here. And in doing so, we will attempt to
` walk through and actually answer these questions.
` So if you turn to Slide 41, what you see here is
` that the Steinaker reference -- which is our base reference
` and that's where we're going to start here, just like we did
` in the petition -- is actually extraordinarily similar to
` the system in the '674 patent. That makes it analogous art
` under In Re Bigio.
` What you see here in the -- on the right is
` Steinaker's system, and what you see are two circuit blocks
` operating at different supply voltages. You've got a core
` network on the left, the first circuit block operating at
` the first supply voltage, and an I/O network 3 highlighted
` on the right operating in a different supply voltage, and
` they need to be communicating with one another.
` And in the process of doing that communication,
` Steinaker teaches a circuit that's voltage detector 5 shown
` in purple here, and that voltage detector 5 is intended to
` indicate to the system when the first supply voltage shuts
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` down or turns on.
` That's exactly what the POC network that's
` highlighted in purple on the left in the '674 patent is
` achieving.
` So these two systems are achieving effectively the
` same thing, and what we find out is that they can achieve --
` it would have been obvious to achieve it in the same way.
` So let's take a look at the actual voltage
` detector 5, and we can turn to Slide 42.
` So when you look at the actual voltage detector 5,
` Steinaker doesn't limit to a specific circuit implementation
` for that voltage detector 5. Instead, he leaves it to a
` POSITA to select an appropriate circuit, and in doing so, it
` provides various teachings to help guide the POSITA in
` making that selection.
` What we see at the bottom is a discussion of the
` voltage detector in Column 4 of Steinaker. And what
` Steinaker tells us is that the voltage detector can be a
` Schmidt trigger, an inverter, a comparator circuit, or a
` comparable circuit.
` But that's not all. What we see when we actually
` look at Figure 1 is that the voltage detector 5 depiction
` also provides additional information. What you can see here
` in Figure 1 is that the voltage detector 5 is a circuit
` element depicted as having inversion, and that's shown by
` the triangle with the dot at the end of it, and there's a
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` graph inside of that triangle. And what does that
` triangle -- what does that graph mean? It means that
` they're seeking hysteresis.
` But don't take my word for that, you can go to
` Dr. Pedram's testimony on Slide 43.
` And Dr. Pedram tells us that, "When a POSITA
` reviewed Steinaker and looked at Figure 1, and looks at that
` voltage detector 5, they would see a triangle with a circle
` at the end of it, that's inverting, and they would see the
` graph which is indicating hysteresis."
` So as he says in the bottom there on the right, "And
` this particular notation which I described to you to
` indicate there is hysteresis between the falling and rising
` trip point of this inverter."
` So what do we know from Steinaker? We know that
` you're looking for an inverter that shows hysteresis, and we
` know that you're looking for something that's useful in the
` mul
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