Paper 49
`Trials@uspto.gov
`571-272-7822 Date: March 21, 2023
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`INTEL CORPORATION,
`Petitioner,
`
`v.
`
`QUALCOMM INCORPORATED,
`Patent Owner.
`
`IPR2018-013341
`Patent 8,838,949 B2
`
`
`
`
`
`
`
`
`
`Before TREVOR M. JEFFERSON, DANIEL J. GALLIGAN, and
`AARON W. MOORE, Administrative Patent Judges.
`
`Opinion for the Board filed by Administrative Patent Judge
`DANIEL J. GALLIGAN.
`
`Opinion Concurring-in-Part and Dissenting-in-Part filed by Administrative
`Patent Judge AARON W. MOORE.
`
`GALLIGAN, Administrative Patent Judge.
`
`
`JUDGMENT
`Final Written Decision on Remand
`Determining Challenged Claims Unpatentable
`35 U.S.C. § 318(a)
`
`
`
`
`
`
`1 IPR2018-01335 and IPR2018-01336 have been consolidated with the
`instant proceeding.
`
`
`
`
`Trials@uspto.gov
`571-272-7822 Date: March 21, 2023
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`INTEL CORPORATION,
`Petitioner,
`
`v.
`
`QUALCOMM INCORPORATED,
`Patent Owner.
`
`IPR2018-013341
`Patent 8,838,949 B2
`
`
`
`
`
`
`
`
`
`Before TREVOR M. JEFFERSON, DANIEL J. GALLIGAN, and
`AARON W. MOORE, Administrative Patent Judges.
`
`Opinion for the Board filed by Administrative Patent Judge
`DANIEL J. GALLIGAN.
`
`Opinion Concurring-in-Part and Dissenting-in-Part filed by Administrative
`Patent Judge AARON W. MOORE.
`
`GALLIGAN, Administrative Patent Judge.
`
`
`JUDGMENT
`Final Written Decision on Remand
`Determining Challenged Claims Unpatentable
`35 U.S.C. § 318(a)
`
`
`
`
`
`
`1 IPR2018-01335 and IPR2018-01336 have been consolidated with the
`instant proceeding.
`
`
`
`
`
`IPR2018-01334
`Patent 8,838,949 B2
`
`
`I. INTRODUCTION
`
`This case is on remand from the Court of Appeals for the Federal
`
`Circuit to address the patentability of claims 1–9, 12, 16, and 17 of U.S.
`
`Patent No. 8,838,949 B2 (“the ’949 patent,” Ex. 1001). See Intel Corp. v.
`
`Qualcomm Inc., 21 F.4th 801, 814 (Fed. Cir. 2021).
`
`For the reasons discussed below, we determine that Petitioner has
`
`proven by a preponderance of the evidence that claims 1–9, 12, 16, and 17
`
`are unpatentable. See 35 U.S.C. § 316(e) (“In an inter partes review
`
`instituted under this chapter, the petitioner shall have the burden of proving a
`
`proposition of unpatentability by a preponderance of the evidence.”).
`
`A. Background
`
`On July 3, 2018, Intel Corporation (“Petitioner”) filed three petitions
`
`challenging claims of the ’949 patent as follows: IPR2018-01334 (claims
`
`1–9, 22, and 23), IPR2018-01335 (claims 10–17), and IPR2018-01336
`
`(claims 18–21). Petitioner asserts that the claims are unpatentable on the
`
`following grounds:
`
`In IPR2018-01334:
`
`Claim(s) Challenged
`1–9, 22, 23
`
`
`35 U.S.C. §2
`103(a)
`
`Reference(s)/Basis
`Bauer,3 Svensson,4 Kim5
`
`
`2 The Leahy-Smith America Invents Act (“AIA”) included revisions to
`35 U.S.C. §§ 103 and 112 that became effective after the filing of the
`application for the ’949 patent. Therefore, we apply the pre-AIA versions of
`these sections.
`3 US 2006/0288019, published Dec. 21, 2006 (Ex. 1009).
`4 US 7,356,680 B2, issued Apr. 8, 2008 (Ex. 1010).
`5 Korean Patent Application Publication No. 10-2002-0036354, published
`May 16, 2002 (Ex. 1011). References to Kim in this Decision are to the
`English translation provided by Petitioner as Exhibit 1012.
`
`
`
`2
`
`
`
`IPR2018-01334
`Patent 8,838,949 B2
`
`
`In IPR2018-01335:
`
`Claim(s) Challenged
`10–15
`16, 17
`
`
`35 U.S.C. §
`103(a)
`103(a)
`
`Reference(s)/Basis
`Bauer, Svensson, Kim
`Bauer, Svensson, Kim, Zhao6
`
`In IPR2018-01336:
`
`Claim(s) Challenged
`18–21
`
`
`35 U.S.C. §
`103(a)
`
`Reference(s)/Basis
`Bauer, Svensson, Kim, Lim7
`
`We instituted review in each case on all grounds presented.
`
`IPR2018-01334, Paper 10 (“Dec. on Inst.”), 29; IPR2018-01335, Paper 10
`
`(“1335 Dec. on Inst.”),8 38; IPR2018-01336, Paper 10 (“1336 Dec. on
`
`Inst.”), 32.
`
`After institution, we consolidated IPR2018-01335 and
`
`IPR2018-01336 with IPR2018-01334 and terminated IPR2018-01335 and
`
`IPR2018-01336. Paper 12.
`
`During the trial, Qualcomm Incorporated (“Patent Owner” or
`
`“Qualcomm”) filed a Response (Paper 16, “PO Resp.”), Petitioner filed a
`
`Reply (Paper 21, “Pet. Reply”), and Patent Owner filed a Sur-reply (Paper
`
`25, “PO Sur-reply”).
`
`An oral hearing was held on December 12, 2019, a transcript of which
`
`appears in the record. Paper 29 (“Tr.”).
`
`
`6 US 2007/0140199 A1, published June 21, 2007 (Ex. 1013).
`7 US 7,203,829 B2, published Apr. 10, 2007 (Ex. 1014).
`8 We use prefixes “1335” and “1336” to denote papers and exhibits from
`IPR2018-01335 and IPR2018-01336, respectively. We do not use a prefix
`for papers and exhibits from IPR2018-01334.
`
`
`
`3
`
`
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`IPR2018-01334
`Patent 8,838,949 B2
`
`
`B. Final Written Decision and Federal Circuit Appeal
`
`We issued a Final Written Decision holding that Petitioner had proven
`
`claims 10, 11, 13–15, and 18–23 unpatentable but had not proven claims
`
`1–9, 12, 16, and 17 unpatentable. Paper 30 (“Final Decision” or “Final
`
`Dec.”) at 63–64.
`
`Petitioner filed a Notice of Appeal of the Final Decision with the
`
`United States Court of Appeals for the Federal Circuit as to our
`
`determination with respect to claims 1–9, 12, 16, and 17. Paper 31. Patent
`
`Owner filed a Notice of Cross-Appeal as to our determination with respect
`
`to claims 10, 11, 13–15, and 18–23. Papers 32, 33.
`
`On December 28, 2021, the Federal Circuit issued a decision in the
`
`appeal vacating our Final Decision as to claims 1–9, 12, 16, and 17 and
`
`remanding for further proceedings. Intel, 21 F.4th at 814. In particular, the
`
`Federal Circuit “vacate[d] the Board’s construction of the term ‘hardware
`
`buffer,’ its determination that claims 1–9 and 12 were non-obvious over the
`
`prior art, and its conclusion that claims 16–17 lacked sufficient
`
`corresponding structure in the specification, and . . . remand[ed] for further
`
`proceedings consistent with this opinion.” Id. At the Federal Circuit, Patent
`
`Owner dropped its challenge to our determination of unpatentability as to
`
`claims 10, 11, 13–15, and 18–23. See id. at 806 (“The Board ruled that Intel
`
`had proved the unpatentability of claims 10, 11, 13–15, and 18–23, but
`
`Qualcomm, despite filing a cross-appeal to raise the issue, no longer
`
`challenges that ruling.”).
`
`The Federal Circuit issued its mandate on February 3, 2022.
`
`
`
`4
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`IPR2018-01334
`Patent 8,838,949 B2
`
`
`C. Remand Proceedings
`
`On February 17, 2022, we held a conference call with counsel for the
`
`parties to discuss a schedule on remand. See Paper 34 at 2–4. Before the
`
`call, the parties met and conferred and agreed to a schedule, which we
`
`adopted. See Paper 34; Ex. 3001. The parties filed the following briefing
`
`according to that schedule: Petitioner’s Opening Brief on Remand
`
`(Paper 35, “Pet. Remand Br.”); Patent Owner’s Response Brief on Remand
`
`(Paper 37, “PO Remand Br.”); Petitioner’s Reply on Remand (Paper 39,
`
`“Pet. Remand Reply”); and Patent Owner’s Sur-reply on Remand (Paper 40,
`
`“PO Remand Sur-reply”).
`
`An oral hearing to discuss the issues on remand was held on August 4,
`
`2022, a transcript of which appears in the record. Paper 46 (“Remand Tr.”).
`
`D. Real Parties in Interest
`
`Petitioner identifies itself and Apple Inc. as real parties in interest.
`
`Pet. 2. Patent Owner identifies itself as the real party in interest. Paper 4, 2.
`
`E. The ’949 Patent and Illustrative Claim
`
`The ’949 patent generally relates to loading software from one
`
`processor to another in a multi-processor system. Ex. 1001, code (57). One
`
`example disclosed in the ’949 patent involves loading modem image
`
`executable data by first retrieving and processing an image header, which
`
`“includes information used to identify where the modem image executable
`
`data is to be eventually placed into the system memory of the secondary
`
`processor.” Ex. 1001, 8:9–21. Figure 3 of the ’949 patent is reproduced
`
`below.
`
`
`
`5
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`IPR2018-01334
`Patent 8,838,949 B2
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`
`
`
`Figure 3 shows “operational flow for an exemplary loading process for
`
`loading an executable image from a primary processor to a secondary
`
`processor according to one aspect of the present disclosure.” Ex. 1001,
`
`4:10–13. Referring to various components depicted in Figure 3, the ’949
`
`patent discloses the following:
`
`The header information is used by the secondary processor 302
`to program the scatter loader/direct memory access controller
`304 receive address when receiving the actual executable data.
`Data segments are then sent from system memory 307 to the
`primary hardware transport mechanism 308. The segments are
`
`
`
`6
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`
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`IPR2018-01334
`Patent 8,838,949 B2
`
`
`then sent from the hardware transport mechanism 308 of the
`primary processor 301 to a hardware transport mechanism 309
`of
`the secondary processor 302 over an
`inter-chip
`communication bus 310 (e.g., a HS-USB cable.) The first
`segment transferred may be the image header, which contains
`information used by the secondary processor to locate the data
`segments into target locations in the system memory of the
`secondary processor 305. The image header may include
`information used to determine the target location information for
`the data.
`
`Ex. 1001, 8:21–35. Of particular relevance on remand is that the ’949 patent
`
`discloses scatter loading data segments “directly” from a “hardware buffer”
`
`to their final locations in the secondary processor’s “system memory.”
`
`Ex. 1001, 2:58–63.
`
`As noted above, claims 1–9, 12, 16, and 17 are at issue on remand.
`
`Claims 1 and 16 are independent claims, claims 2–9 depend from claim 1,
`
`and claim 17 depends from claim 16. Claim 12 depends from independent
`
`claim 10, which is unpatentable. See Final Dec. 50, 63; Intel, 21 F.4th at
`
`806 (noting that Patent Owner dropped its challenge to the Board’s
`
`unpatentability determination for claim 10).
`
`Claims 1, 10, 12, and 16 are reproduced below.
`
`1.
`
`A multi-processor system comprising:
`a secondary processor comprising:
`system memory and a hardware buffer for receiving
`an image header and at least one data segment of an
`executable software image, the image header and each
`data segment being received separately, and
`a scatter loader controller configured:
`to load the image header; and
`to scatter load each received data segment
`based at least in part on the loaded image header,
`directly from the hardware buffer to the system
`memory;
`
`
`
`7
`
`
`
`IPR2018-01334
`Patent 8,838,949 B2
`
`
`a primary processor coupled with a memory, the memory
`storing the executable software image for the secondary
`processor; and
`the primary
`an interface communicatively coupling
`processor and the secondary processor, the executable software
`image being received by the secondary processor via the
`interface.
`
`10. A method comprising:
`receiving at a secondary processor, from a primary
`processor via an inter-chip communication bus, an image header
`for an executable software image for the secondary processor
`that is stored in memory coupled to the primary processor, the
`executable software image comprising the image header and at
`least one data segment, the image header and each data segment
`being received separately;
`processing, by the secondary processor, the image header
`to determine at least one location within system memory to
`which the secondary processor is coupled to store each data
`segment;
`receiving at the secondary processor, from the primary
`processor via the inter-chip communication bus, each data
`segment; and
`scatter loading, by the secondary processor, each data
`segment [directly9] to the determined at least one location within
`the system memory, and each data segment being scatter loaded
`based at least in part on the processed image header.
`
`12. The method of claim 10 further comprising loading the
`executable software image directly from a hardware buffer to the
`system memory of the secondary processor without copying data
`between system memory locations.
`
`
`
`9 The issued patent recites “reedy,” which appears to be a printing error.
`The April 30, 2014 claim listing submitted by the applicants during
`prosecution states “directly.”
`
`
`
`8
`
`
`
`IPR2018-01334
`Patent 8,838,949 B2
`
`
`16. An apparatus comprising:
`means for receiving at a secondary processor, from a
`primary processor via an inter-chip communication bus, an
`image header for an executable software image for the secondary
`processor that is stored in memory coupled to the primary
`processor, the executable software image comprising the image
`header and at least one data segment, the image header and each
`data segment being received separately;
`means for processing, by the secondary processor, the
`image header to determine at least one location within system
`memory to which the secondary processor is coupled to store
`each data segment;
`means for receiving at the secondary processor, from the
`primary processor via the inter-chip communication bus, each
`data segment; and
`means for scatter loading, by the secondary processor,
`each data segment directly to the determined at least one location
`within the system memory, and each data segment being scatter
`loaded based at least in part on the processed image header.
`
`II. ANALYSIS
`
`A. Level of Ordinary Skill in the Art
`
`We apply the following level of ordinary skill in the art: “a Master’s
`
`degree in Electrical Engineering, Computer Engineering, or Computer
`
`Science plus two years of experience in mobile device architecture and
`
`multi-processor systems, or a Bachelor’s degree in one of those fields plus
`
`four years of experience in mobile device architecture and multiprocessor
`
`systems.” See Final Dec. 8.
`
`B. Claim Interpretation
`
`In this proceeding, we give the claims the broadest reasonable
`
`construction in light of the Specification of the ’949 patent.
`
`37 C.F.R. § 42.100(b) (2018); see Changes to the Claim Construction
`
`Standard for Interpreting Claims in Trial Proceedings Before the Patent Trial
`
`
`
`9
`
`
`
`IPR2018-01334
`Patent 8,838,949 B2
`
`and Appeal Board, 83 Fed. Reg. 51,340 (Oct. 11, 2018) (amending
`
`37 C.F.R. § 42.100(b) effective November 13, 2018) (now codified at
`
`37 C.F.R. § 42.100(b) (2019)); see also Intel, 21 F.4th at 808–09 (stating
`
`that the broadest reasonable interpretation standard applies).
`
`The claim construction issue on remand for claims 1–9 and 12
`
`concerns the scope of the term “hardware buffer.” See Intel, 21 F.4th at 810.
`
`For claims 16 and 17, constructions for the means-plus-function limitations
`
`are at issue. See Intel, 21 F.4th at 812–14.
`
`1. Hardware Buffer
`
`a. Pre-Appeal Final Written Decision
`
`The term “hardware buffer” appears in independent claim 1, and
`
`claims 2 and 8, which depend from claim 1, and in claim 12, which depends
`
`from independent claim 10. Claim 1 recites, in part, “a secondary processor
`
`comprising: system memory and a hardware buffer for receiving an image
`
`header and at least one data segment of an executable software image” and
`
`“a scatter loader controller configured: to load the image header; and to
`
`scatter load each received data segment based at least in part on the loaded
`
`image header, directly from the hardware buffer to the system memory.”
`
`Claim 12 recites, “The method of claim 10 further comprising loading the
`
`executable software image directly from a hardware buffer to the system
`
`memory of the secondary processor without copying data between system
`
`memory locations.”
`
`In the Final Decision, we analyzed the intrinsic evidence and
`
`determined that “the ‘hardware buffer’ limitations of independent claim 1
`
`and its dependent claims (2–9) and dependent claim 12 ‘should not be read
`
`so broadly as to encompass’ the use of a temporary buffer.” Final
`
`
`
`10
`
`
`
`IPR2018-01334
`Patent 8,838,949 B2
`
`Dec. 10–17 (quoting SciMed Life Systems, Inc. v. Advanced Cardiovascular
`
`Systems, Inc., 242 F.3d 1337, 1343 (Fed. Cir. 2001)). Applying that
`
`interpretation, we determined that Petitioner had not proven unpatentability
`
`of claims 1–9 and 12. Final Dec. 55–56.
`
`Petitioner appealed our determination as to claims 1–9 and 12. See
`
`Intel, 21 F.4th at 808–12.
`
`b. Federal Circuit’s Decision
`
`The Federal Circuit found our construction “wanting” and
`
`“inadequate” and vacated our determination as to claims 1–9 and 12. Intel,
`
`21 F.4th at 808–12. The Federal Circuit stated that “it is clear from the
`
`claim language that the claim term [‘hardware buffer’] has meaning, but it is
`
`unclear what that meaning is. There is no definition to be found in the
`
`intrinsic evidence.” Id. at 809. Furthermore, “the determination of that
`
`meaning (or range of reasonable meanings) depends on understanding what
`
`the intrinsic evidence makes clear is the substance of the invention—what
`
`the inventor ‘intended to envelop,’” which “in some cases is usefully
`
`clarified by expert testimony (as long as that testimony is consistent with the
`
`intrinsic evidence).” Id. (quoting Phillips v. AWH Corp., 415 F.3d 1303,
`
`1316 (Fed. Cir. 2005) (en banc)). The Federal Circuit concluded that we
`
`“did not do enough to reach and articulate that understanding.” Id. Below,
`
`we address the Federal Circuit’s decision in more detail in light of the
`
`parties’ arguments on remand.
`
`c. Determination on Remand
`
`On remand, the parties provide additional briefing and evidence on
`
`the proper interpretation of the term “hardware buffer.” Pet. Remand Br.
`
`5–13; PO Remand Br. 3–15. Petitioner argues that the broadest reasonable
`
`
`
`11
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`
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`IPR2018-01334
`Patent 8,838,949 B2
`
`interpretation of the term “hardware buffer” is “memory that is physically
`
`separate from the memory into which the software image is loaded for
`
`execution.” Pet. Remand Br. 5. Patent Owner counters that the proper
`
`interpretation of this term is “a permanent, dedicated buffer that is distinct
`
`from system memory.” PO Remand Br. 3. For the reasons explained below,
`
`we determine that Patent Owner’s temporal restriction on the buffer
`
`(“permanent”) is not required of the broadest reasonable interpretation.
`
`As discussed above, the Federal Circuit stated that the proper
`
`construction “depends on understanding what the intrinsic evidence makes
`
`clear is the substance of the invention—what the inventor ‘intended to
`
`envelop.’” Intel, 21 F.4th at 809 (quoting Phillips, 415 F.3d at 1316). More
`
`particularly, the court stated that we should provide “a more
`
`substance-focused analysis . . . of what the intrinsic evidence shows the
`
`asserted advance to be and how, concretely, the ‘hardware buffer’ relates to
`
`that advance.” Id. at 811. Below, we address the claims, the Specification,
`
`and the prosecution history, as well as additional evidence that informs the
`
`meaning of the term “hardware buffer.”
`
`i. Claim Language
`
`Turning to the claim language first, the Federal Circuit noted that “it
`
`is clear from the claim language that the claim term at issue [(‘hardware
`
`buffer’)] has meaning, but it is unclear what that meaning is” and that
`
`“[t]here is no definition to be found in the intrinsic evidence.” Intel, 21
`
`F.4th at 809. The Federal Circuit, nevertheless, “reach[ed] three conclusions
`
`from the claim language.” Id. “First,” the Federal Circuit stated, “because
`
`every buffer in our (physical) world is ultimately implemented on a physical
`
`device (i.e., hardware), a ‘hardware buffer’ must mean something more than
`
`
`
`12
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`
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`IPR2018-01334
`Patent 8,838,949 B2
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`just a ‘buffer implemented in hardware,’ as [Petitioner] urges, or else the
`
`word ‘hardware’ would be erased from the claims.” Id. “Second, because
`
`claim 1 requires both a ‘system memory’ and a ‘hardware buffer,’ there must
`
`be some distinction between those two concepts.” Id. at 810.
`
`Third, because claim 2 requires loading the executable software
`image “directly from the hardware buffer to the system memory
`of the secondary processor without copying data between
`system memory locations on the secondary processor,” the
`meaning of “hardware buffer” relates to the ability to move the
`software image “directly” to the second processor’s system
`memory and to avoid “copying data between system memory
`locations.”
`
`Id.
`
`The Federal Circuit then noted that these “conclusions from the claim
`
`language advance the claim-construction inquiry only so far” but “do not, on
`
`their own, provide a concrete basis for a clarifying definition of ‘hardware
`
`buffer.’” Intel, 21 F.4th at 810. The court stated that “an analysis of the
`
`specification” is needed “to arrive at an understanding of what it teaches
`
`about what a ‘hardware buffer’ is, based on both how it uses relevant words
`
`and its substantive explanations.” Id. The Federal Circuit further stated that
`
`“[w]hat is needed in this case is a more substance-focused analysis than is
`
`yet present, in the Board’s opinion or in the present record . . ., of what the
`
`intrinsic evidence shows the asserted advance to be and how, concretely, the
`
`‘hardware buffer’ relates to that advance.” Id. at 811.
`
`With this guidance in mind, we turn next to the Specification of the
`
`’949 patent.
`
`ii. Specification
`
`The written description of the ’949 patent uses the term “hardware
`
`buffer” only three times, and Figure 3 includes the label “Hardware Buffer”
`
`
`
`13
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`IPR2018-01334
`Patent 8,838,949 B2
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`in each of the primary processor and the secondary processor. Ex. 1001,
`
`2:58–63, 9:37–41, Fig. 3. The first two instances of the term “hardware
`
`buffer” are in the following passage: “The system includes a secondary
`
`processor having a system memory and a hardware buffer for receiving at a
`
`least a portion of an executable software image. The secondary processor
`
`includes a scatter loader controller for loading the executable software image
`
`directly from the hardware buffer to the system memory.” Ex. 1001,
`
`2:58–63. This passage mirrors the claim language and, thus, does not
`
`advance the inquiry any further than the claims themselves. The other
`
`passage mentioning “hardware buffer” states the following in reference to
`
`Figure 3: “In one aspect, the executable software image is loaded into the
`
`system memory of the secondary processor without an entire executable
`
`software image being stored in the hardware buffer of the secondary
`
`processor.” Ex. 1001, 9:37–41. This passage sheds some light on a different
`
`aspect of the disclosure of the ’949 patent, namely, not having to load the
`
`entire image to a buffer first before loading the image to its ultimate
`
`destination, but the passage does not itself help define the term “hardware
`
`buffer.”
`
`In the Final Decision, we focused on the ’949 patent Specification’s
`
`apparent differentiation between its “hardware buffer” and the use of a
`
`temporary buffer in the prior art, and we concluded that the “hardware
`
`buffer” limitations should not be read to encompass the use of a temporary
`
`buffer. Final Dec. 15–17 (citing Ex. 1001, 2:23–34, 4:43–47, 5:31–35).
`
`The Federal Circuit stated that, “[a]lthough the Board correctly noted
`
`that the specification describes prior art teaching of use of ‘temporary’
`
`buffers, it did not explain precisely what ‘temporary’ means or how the
`
`
`
`14
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`IPR2018-01334
`Patent 8,838,949 B2
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`patent-described prior-art use relates to the alleged invention.” Intel, 21
`
`F.4th at 810. The court further stated that “the Board did not analyze exactly
`
`how the use of a hardware buffer, as claimed by Qualcomm, would address
`
`the concerns about the prior-art temporary buffers raised in” three passages
`
`in the Specification. Id. at 810–11 (citing Ex. 1001, 2:23–34, 4:43–47,
`
`5:31–35). We now provide such analysis in light of the parties’ arguments
`
`on this issue.
`
`Petitioner argues that the Specification of the ’949 patent
`
`distinguishes other aspects of the prior art rather than the use of temporary
`
`buffers per se. Pet. Remand Br. 7–11. For example, the Background section
`
`of the ’949 patent states the following:
`
`In a system in [w]hich the software image is loaded onto
`a target “secondary” processor from a first “primary” processor,
`one way of performing such loading is to allocate a temporary
`buffer into which each packet is received, and each packet
`would have an associated packet header information along with
`the payload. The payload in this case would be the actual
`image data. From the temporary buffer, some of the processing
`may be done over the payload, and then the payload would get
`copied over to the final destination. The temporary buffer
`would be some place in system memory, such as in internal
`random-access-memory (RAM) or double data rate (DDR)
`memory, for example.
`
`Ex. 1001, 2:23–34 (emphasis added). Petitioner argues that this passage is
`
`distinguishing between a situation in which each packet has its own header
`
`and payload and the situation in the claims requiring that the header and data
`
`segments are received separately, rather than distinguishing the use of a
`
`temporary buffer. Pet. Remand Br. 10.
`
`Another passage from the ’949 patent provides the following:
`
`
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`IPR2018-01334
`Patent 8,838,949 B2
`
`
`In one exemplary aspect a direct scatter load technique is
`disclosed for loading a segmented image from a primary
`processor’s non-volatile memory to a secondary processor’s
`volatile memory. As discussed further below, the direct scatter
`load technique avoids use of a temporary buffer. For instance,
`in one aspect, rather than employing a packet-based
`communication in which the image is communicated via
`packets that each include a respective header, the raw image
`data is loaded from the primary processor to the secondary
`processor.
`
`Ex. 1001, 4:43–52 (emphasis added). Petitioner argues that this passage also
`
`shows a distinction between receiving header and data together, as in the
`
`’949 patent’s characterization of the prior art, and receiving the header and
`
`data segments separately, as in the claims. Pet. Remand Br. 10–11.
`
`The ’949 patent also mentions the use of a temporary buffer in the
`
`following passage:
`
`Thus, conventional techniques employing a temporary buffer
`for the entire image, and the packet header handling, etc., are
`bypassed in favor of a more efficient direct loading process.
`Thus, the exemplary load process of FIG. 3 does not require the
`intermediate buffer operations traditionally required for loading
`a software image from a primary processor to a secondary
`processor. Instead of scatter loading from a temporary buffer
`holding the entire image, the exemplary load process of FIG. 3
`allows for direct scatter load the image segments to their
`respective target destinations directly from the hardware to the
`system memory.
`
`Ex. 1001, 9:43–54 (emphasis added). Petitioner argues that this passage
`
`“distinguishes systems in which the entire executable software image is
`
`copied into a temporary buffer.” Pet. Remand Br. 9.
`
`We agree with Petitioner that these passages provide additional
`
`context to show that the ’949 patent does not necessarily distinguish its
`
`invention from the use of a temporary buffer, per se.
`
`
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`IPR2018-01334
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`
`The ’949 patent also discusses how its data transfer methodology
`
`avoids extra memory copy operations, a point the Federal Circuit noted. See
`
`Intel, 21 F.4th at 811 (noting “other specification passages that support an
`
`understanding that use of a ‘hardware buffer’ relates to one of the key
`
`claimed advances of the invention—the elimination of ‘extra memory copy
`
`operations’” (citing Ex. 1001, 7:16, 7:27–30, 9:42–46)). As mentioned in
`
`the preceding section, the Federal Circuit stated that “the meaning of
`
`‘hardware buffer’ relates to the ability to move the software image ‘directly’
`
`to the second processor’s system memory and to avoid ‘copying data
`
`between system memory locations,’” as recited in claim 2. Intel, 21 F.4th
`
`at 810.
`
`There is no question that a focus of the ’949 patent is on eliminating
`
`extra memory copy operations, but more precisely on extra memory copy
`
`operations performed by the secondary processor. For example, claim 2
`
`recites, “The multi-processor system of claim 1 in which the scatter loader
`
`controller is configured to load the executable software image directly from
`
`the hardware buffer to the system memory of the secondary processor
`
`without copying data between system memory locations on the secondary
`
`processor.” Claim 1 provides that the scatter loader controller is part of the
`
`secondary processor. Similarly, the ’949 patent states that “no extra memory
`
`copy operations occur in the secondary processor in the above aspect,”
`
`referring to the operation described with respect to Figure 3. Ex. 1001,
`
`9:42–43; see also PO Remand Br. 6 (“Specifically, the ’949 patent states
`
`that in performing the direct transfer using the hardware buffer, ‘no extra
`
`memory copy operations occur in the secondary processor.’” (quoting
`
`Ex. 1001, 9:42–43)). To the extent this particular aspect of the ’949 patent’s
`
`
`
`17
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`IPR2018-01334
`Patent 8,838,949 B2
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`disclosure informs the proper meaning of the term “hardware buffer,” we do
`
`not see a relevant distinction between the operation of the ’949 patent and
`
`the asserted prior art. As explained more fully below, both the ’949 patent
`
`and the asserted prior art describe that the primary processor performs a
`
`memory copy operation, followed by a memory copy operation by the
`
`secondary processor.
`
`Based on the foregoing, we do not view the Specification as imposing
`
`a temporal restriction on the nature of the “hardware buffer.” As to “what
`
`the intrinsic evidence shows the asserted advance to be and how, concretely,
`
`the ‘hardware buffer’ relates to that advance,” Intel, 21 F.4th at 811, the
`
`prosecution history provides particular insight.
`
`iii. Prosecution History
`
`Petitioner argues that the prosecution history shows that certain
`
`language added by amendment, such as the separate receipt of the header
`
`and data, reflects the “asserted advance” of the ’949 patent. Pet. Remand
`
`Br. 11–13. In particular, during prosecution of the ’949 patent, the
`
`Examiner rejected all then-pending claims as anticipated by International
`
`Publication WO 2006/077068 A2 (Ex. 1003), which is the Patent
`
`Cooperation Treaty (PCT) application publication that claims priority to
`
`Svensson. Ex. 1004 (July 19, 2013 Non-Final Rejection 2–4); see Ex. 1003
`
`(“Svensson PCT”), code (30). In rejecting the pending claims, the Examiner
`
`found that Svensson PCT’s intermediate storage area (ISA) defined within
`
`memory 108 describes the recited “hardware buffer.” Ex. 1004 at 2; see Pet.
`
`Remand Br. 11–12. This is the same ISA of Svensson and Bauer that
`
`Petitioner contends is a “hardware buffer.” See Pet. Remand Br. 11–12. As
`
`Petitioner notes (Pet. Remand Br. 12), the applicants responded to this
`
`
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`IPR2018-01334
`Patent 8,838,949 B2
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`rejection by amending claim 1 to recite “the image header and each data
`
`segment being received separately” and a scatter loader controller
`
`configured “to load the image header” and “to scatter load each received
`
`data segment based at least in part on the loaded image header.” Ex. 1005
`
`at 2.
`
`The applicants then provided arguments distinguishing the disclosure
`
`of Svensson PCT. According to the applicants, “FIG. 3 of Svensson [PCT]
`
`arguably discloses that the software includes a header and a data segment.
`
`As disclosed in col. 8 lines 10-19 of Svensson [PCT], each code and/or data
`
`to be transferred includes a header.” Ex. 1005 at 8. Svensson PCT does not
`
`have dual-column pages like issued patents, so we understand the applicants
`
`to be referring to page 8, lines 10–19 of Svensson PCT, which is the same as
`
`column 6, lines 13–25 of Svensson. The applicants continued, stating the
`
`following:
`
`In contrast to Svensson [PCT], claim 1 recites that the
`image header and each data segment are received separately.
`Applicants submit that separately receiving the image header
`and each data segment, as recited in claim 1, is patentably
`distinguishable from receiving the data and the associated
`header, as disclosed in Svensson [PCT]. Therefore, because
`Svensson [PCT] expressly discloses that each code and/or data
`to be transferred includes a header and fails to disclose that the
`image header and each data segment are received separately,
`applicants submit that Svensson [PCT] cannot teach or suggest
`“the image header and each data segment are received
`separately,” as recited in claim 1.
`
`Ex. 1005 at 8–9. Here, the applicants rely on the separate receipt of the
`
`image header and the data as a distinguishing feature.
`
`Furthermore, the applicants stated the following:
`
`
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`IPR2018-01334
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`
`Moreover, the cited portions of Svensson [PCT] disclose
`that several blocks (e.g., data blocks with headers) are
`concatenated in the intermediate storage a
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