UNITED STATES PATENT AND TRADEMARK OFFICE
`____________________________________________
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________________________________________
`Intel Corporation
`Petitioner
`v.
`Qualcomm Incorporated
`Patent Owner of U.S. Patent No. 8,838,949
`
`____________________________________________
`Trial No. IPR2018-013341
`____________________________________________
`REMAND DECLARATION OF BILL LIN, PH.D.
`ON BEHALF OF PETITIONER
`
`1 IPR2018-01335 and IPR2018-01336 have been consolidated with the instant
`
`proceeding.
`
`IPR2018-01334
`Intel v. Qualcomm
`INTEL 1026
`
`
`____________________________________________
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________________________________________
`Intel Corporation
`Petitioner
`v.
`Qualcomm Incorporated
`Patent Owner of U.S. Patent No. 8,838,949
`
`____________________________________________
`Trial No. IPR2018-013341
`____________________________________________
`REMAND DECLARATION OF BILL LIN, PH.D.
`ON BEHALF OF PETITIONER
`
`1 IPR2018-01335 and IPR2018-01336 have been consolidated with the instant
`
`proceeding.
`
`IPR2018-01334
`Intel v. Qualcomm
`INTEL 1026
`
`
`
`U.S. Patent No. 8,838,949
`Remand Declaration of Bill Lin, Ph.D.
`
`TABLE OF CONTENTS
`INTRODUCTION ........................................................................................... 1
`I.
`QUALIFICATIONS ........................................................................................ 2
`II.
`III. RELEVANT LAW .......................................................................................... 2
`IV. CLAIMS 1-9, 12 AND 16-17 ARE OBVIOUS .............................................. 2
`A.
`Construction of “Hardware Buffer” ...................................................... 4
`1.
`The “hardware buffer” is physically separate from
`the claimed system memory. ...................................................... 6
`The “hardware buffer” can be located within
`another system memory or any other location
`separate from the claimed “system memory”. .......................... 10
`The “hardware buffer” can be a temporary buffer. ................... 13
`The prosecution history supports my construction
`of “hardware buffer”. ................................................................ 20
`The Intermediate Storage Area of Bauer and Svensson Is
`a “Hardware Buffer” ........................................................................... 22
`1.
`The intermediate storage area is separate from the
`system memory set forth in Bauer and Svensson. .................... 25
`The intermediate storage area would meet the
`“hardware buffer” limitation even under a
`narrower construction. .............................................................. 31
`Structure for Means-Plus-Function Limitations of Claims
`16 and 17 ............................................................................................. 33
`CONCLUSION ............................................................................................. 34
`V.
`VI. AVAILABILITY FOR CROSS-EXAMINATION ...................................... 34
`
`B.
`
`C.
`
`2.
`
`3.
`4.
`
`2.
`
`
`
`i
`
`
`
`U.S. Patent No. 8,838,949
`Remand Declaration of Bill Lin, Ph.D.
`
`VII. RIGHT TO SUPPLEMENT .......................................................................... 35
`VIII. JURAT ........................................................................................................... 35
`
`
`
`
`ii
`
`
`
`U.S. Patent No. 8,838,949
`Remand Declaration of Bill Lin, Ph.D.
`
`1.
`
`I, Bill Lin, Ph.D. declare as follows:
`
`I.
`
`INTRODUCTION
`2.
`I have been retained by Intel Corporation (“Intel” or “Petitioner”) as
`
`an independent expert consultant in this proceeding before the United States Patent
`
`and Trademark Office. I previously prepared and submitted my Opening
`
`Declarations in support of the Petitions in IPR2018-01334, IPR2018-01335, and
`
`IPR2018-01336, dated July 2, 2018 and July 3, 2018 (Exs. 1002, 1020, and 1021).
`
`I also submitted my Reply Declaration in IPR2018-013342, which has been
`
`consolidated with IPR2018-01335 and IPR2018-01336, on September 27, 2019. I
`
`submit this Declaration in support of Petitioner’s Opening Brief on Remand.
`
`3.
`
`Since preparing my Opening and Reply Declarations, I have also
`
`reviewed the following materials:
`
`• Petitioner’s Sur-Reply (Paper 25);
`
`• Final Written Decision (Paper 30);
`
`
`2 Because IPR2018-01335 and IPR2018-01336 have been consolidated with
`
`IPR2018-01334, I have cited to exhibits from IPR2018-01334 throughout, unless
`
`noted otherwise.
`
`
`
`
`1
`
`
`
`U.S. Patent No. 8,838,949
`Remand Declaration of Bill Lin, Ph.D.
`
`• Federal Circuit Opinion (Intel Corp. v. Qualcomm Inc., 21 F.4th 801
`
`(Fed. Cir. 2021));
`
`• Scheduling Order on Remand (Paper 34); and
`
`• Any other document cited in this Declaration.
`
`4.
`
`I am being compensated for my work on this matter, but my opinions
`
`are based on my own views of the patent and the prior art. My compensation in no
`
`way depends on the outcome of this proceeding or the content of my testimony.
`
`II. QUALIFICATIONS
`5.
`I described my qualifications in my Opening Declarations. Ex. 1002
`
`(Lin Op. Decl.) at ¶¶ 1-12; Ex. 1020 (Lin Op. Decl. in IPR2018-01335) at ¶¶ 1-11.
`
`III. RELEVANT LAW
`6.
`In my first Declarations, I set forth the applicable principles of patent
`
`law that were provided to me by counsel. Ex. 1002 (Lin Op. Decl.) at ¶¶ 16-27;
`
`Ex. 1020 (Lin Op. Decl. in IPR2018-01335) at ¶¶ 15-26. As appropriate, I have
`
`continued to apply those principles in providing my opinions in this Declaration.
`
`IV. CLAIMS 1-9, 12 AND 16-17 ARE OBVIOUS
`7.
`In its Final Written Decision, the Board found unpatentable claims 10,
`
`11, 13-15, and 18-23 of the ’949 patent, but did not find unpatentable claims 1-9,
`
`2
`
`
`
`
`
`
`U.S. Patent No. 8,838,949
`Remand Declaration of Bill Lin, Ph.D.
`
`12, 16, and 17. For claims 1-9 and 12, the Board construed “hardware buffer” as
`
`excluding temporary buffers and found that, because the disclosed structure in
`
`Bauer and Svensson, the intermediate storage area, is supposedly a temporary
`
`buffer, it did not satisfy the “hardware buffer” limitation of the ’949 patent. FWD
`
`(Paper 30) at 17, 56. The Board also found that Petitioner failed to identify an
`
`adequate corresponding structure for certain means-plus-function terms of claims
`
`16 and 17. Id. at 18.
`
`8.
`
`I understand that in its decision on appeal, the Federal Circuit rejected
`
`the Board’s construction of the term “hardware buffer.” See Intel Corp. v.
`
`Qualcomm Inc., 21 F.4th 801, 812 (Fed. Cir. 2021). I also understand that the
`
`Federal Circuit remanded this IPR to the Board, instructing the Board to properly
`
`construe the claim term “hardware buffer,” determine whether claims 1-9 and 12 of
`
`the ’949 patent are obvious under the construction of “hardware buffer,” and
`
`determine whether the Board can resolve the prior art challenge to the patentability
`
`of claims 16 and 17 despite the potential indefiniteness of the means-plus-function
`
`terms or whether the terms are indefinite and it is logically impossible to adjudicate
`
`the prior art challenge on its merits. Id. at 813-814.
`
`3
`
`
`
`
`
`
`U.S. Patent No. 8,838,949
`Remand Declaration of Bill Lin, Ph.D.
`
`9.
`
`As discussed below, it is my opinion that “hardware buffer” should be
`
`construed as “memory that is physically separate from the memory into which the
`
`software image is loaded for execution”. Under this construction, the intermediate
`
`storage area of Bauer and Svensson satisfies the “hardware buffer” limitation.
`
`10. With respect to the means-plus-function limitations of claims 16 and
`
`17, it is my opinion that the structure I had identified in my previous Declaration is
`
`the only structure for these means-plus-function limitations set forth in the ’949
`
`specification. I have set forth my analysis for claims 16 and 17 for this structure,
`
`including how claims 16 and 17 are obvious in light of the prior art, in my initial
`
`Declaration in IPR2018-01335. Ex. 1020 (Lin Op. Decl. in IPR2018-01335) at ¶¶
`
`83, 87.
`
`A. Construction of “Hardware Buffer”
`11.
`“Hardware buffer” should be construed as “memory that is physically
`
`separate from the memory into which the software image is loaded for execution.”
`
`This is consistent with the Federal Circuit’s opinion, the claim language and
`
`specification as understood by a person of ordinary skill in the art (“POSITA”),
`
`and the prosecution history.
`
`4
`
`
`
`
`
`
`U.S. Patent No. 8,838,949
`Remand Declaration of Bill Lin, Ph.D.
`
`12. While I had previously opined that “hardware buffer” should broadly
`
`be understood as a “buffer implemented in hardware” (see Ex. 1023 (Lin Reply
`
`Decl.) at ¶¶ 20-25), the Board and the Federal Circuit did not adopt this
`
`construction. My proposed construction set forth herein, however, is consistent
`
`with the Federal Circuit’s guidance on the scope of the term “hardware buffer”.
`
`First, my proposed construction provides more meaning for the term “hardware
`
`buffer” than “just a ‘buffer implemented in hardware,’” which the Federal Circuit
`
`did not adopt. Intel, 21 F.4th at 809-810. Second, my construction reflects the
`
`Federal Circuit’s finding that “[b]ecause claim 1 requires both a ‘system memory’
`
`and a ‘hardware buffer,’” “there must be some distinction between those two
`
`concepts,” id. at 810; see also infra Section IV.A.1. In particular, my construction
`
`is consistent with the Federal Circuit’s guidance in that the “hardware buffer” is
`
`physically separate from the claimed “system memory.” Third, consistent with the
`
`Federal Circuit’s findings, my construction allows the executable software image
`
`to be loaded directly from the hardware buffer to the final location in the claimed
`
`system memory, “without copying data between system memory locations”, as set
`
`forth in claim 2. See Intel, 21 F.4th at 810. However, as I discuss further below,
`
`see infra Section IV.A.2, a POSITA would not understand the language of claim 2
`
`5
`
`
`
`
`
`
`U.S. Patent No. 8,838,949
`Remand Declaration of Bill Lin, Ph.D.
`
`or the specification as precluding the loading of the executable image from a
`
`system memory that is physically separate from the claimed “system memory”.
`
`1.
`
`The “hardware buffer” is physically separate from the
`claimed system memory.
`In light of the Board’s and Federal Circuit’s findings that “hardware
`
`13.
`
`buffer” should be more than a “buffer implemented in buffer” and should be
`
`distinguished from system memory, Intel, 21 F.4th at 809-810, “hardware buffer”
`
`means “memory that is physically separate from the memory into which the
`
`software image is loaded for execution.” This construction is supported by both
`
`the claim language and specification, despite the sparse discussion of the
`
`“hardware buffer” in the ’949 patent.
`
`14. As the Board noted in its Final Written Decision, the claim language
`
`and the specification of the ’949 patent do not specifically define or “provide
`
`much, if any, guidance on what a ‘hardware buffer’ must be.” FWD (Paper 30) at
`
`15. In fact, the term is only discussed three times in the specification. Ex. 1001
`
`(’949 patent) at 2:58-63, 9:37-41; see also id. at Fig. 3. Analysis of the discussion
`
`of “hardware buffer” clarifies only two aspects of this limitation, as discussed
`
`further below: (1) that the “hardware buffer” should be physically separate from
`
`the claimed “system memory” and (2) that the “hardware buffer” temporarily
`6
`
`
`
`
`
`
`U.S. Patent No. 8,838,949
`Remand Declaration of Bill Lin, Ph.D.
`
`stores data segments of the executable software image before the data segments are
`
`loaded to their final destination in “system memory”.
`
`15.
`
`Independent claim 1 of the ’949 patent requires: “system memory and
`
`a hardware buffer for receiving an image header and at least one data segment of
`
`an executable software image” and a scatter load controller “to scatter load each
`
`received data segment … directly from the hardware buffer to the system
`
`memory.” Similarly, the specification states that the “hardware buffer” receives
`
`“at least a portion of an executable software image,” which is loaded from the
`
`“hardware buffer” to the “system memory.” Ex. 1001 (’949 patent) at 2:58-63; see
`
`also id. at 9:37-41 (in one embodiment, “an entire executable software image” is
`
`not stored in the “hardware buffer”). From these disclosures, it is only clear that
`
`the “hardware buffer” receives data for temporary storage and is physically
`
`separate from the claimed “system memory” to which it loads the executable
`
`software image. This is also depicted below in the exemplary embodiment of
`
`Figure 3 in the ’949 patent:
`
`7
`
`
`
`
`
`
`U.S. Patent No. 8,838,949
`Remand Declaration of Bill Lin, Ph.D.
`
`
`
`8
`
`Id. at Fig. 3.
`
`
`
`
`
`
`U.S. Patent No. 8,838,949
`Remand Declaration of Bill Lin, Ph.D.
`
`16. As set forth in my Reply Declaration (see Ex. 1023 at ¶¶ 9-14), the
`
`claimed system memory, on the other hand, would be understood by a POSITA as
`
`“memory where an executable software image can be loaded and executed”. This
`
`is the same meaning used in the ’949 patent, which consistently describes the
`
`claimed system memory as the memory where data segments—in this case the data
`
`segments of the executable software image—can be loaded and executed. See Ex.
`
`1001 (’949 patent) at 2:61-63 (describing “loading the executable software image
`
`directly from the hardware buffer to the system memory”); id. at 5:31-35 (referring
`
`to loading executable image into RAM 112); id. at 5:48-51 (“The modem Boot
`
`ROM code 126 may then jump into that modem executable image 132 and start
`
`executing the main modem program from the modem processor RAM 112 [i.e.,
`
`system memory]”); id. at 8:18-21 (referring to “where the modem image
`
`executable data is to be eventually placed into the system memory of the
`
`secondary processor 305”); id. at 9:37-41 (“[T]he executable software image is
`
`loaded into the system memory of the secondary processor ….”); id. at claim 22
`
`(requiring “scatter load[ing] each received data segment directly to a system
`
`memory of the secondary processor; and executing, at the secondary processor, the
`
`executable software image”). It is clear from nearly every disclosure of the
`
`9
`
`
`
`
`
`
`U.S. Patent No. 8,838,949
`Remand Declaration of Bill Lin, Ph.D.
`
`claimed “system memory” (i.e., “modem processor RAM 112”) in the ’949 patent
`
`that the purpose of loading an executable image into the target locations of the
`
`“system memory” is so that it can be executed.
`
`17. Given that the ’949 patent’s guidance on the meaning of “hardware
`
`buffer” is that it must receive and store at least a portion of the executable software
`
`image and be separate from the claimed “system memory”, and the meaning of
`
`“system memory” in both the ’949 patent and prior art, there is no basis for
`
`interpreting “hardware buffer” any narrower than “memory that is physically
`
`separate from the memory into which the software image is loaded for execution.”
`
`2.
`
`The “hardware buffer” can be located within another
`system memory or any other location separate from the
`claimed “system memory”.
`18. While the “hardware buffer” must be physically separate from the
`
`claimed “system memory” (i.e., the “hardware buffer” is separate from the
`
`“modem processor RAM 112” in the ’949 specification), this does not mean the
`
`“hardware buffer” cannot be located within some other system memory of the
`
`secondary processor. In its Final Written Decision, the Board specifically found
`
`that the “recitation of a separate system memory, by itself, does not foreclose the
`
`possibility of implementing a [hardware] buffer in some other system memory.”
`
`10
`
`
`
`
`
`
`U.S. Patent No. 8,838,949
`Remand Declaration of Bill Lin, Ph.D.
`
`FWD (Paper 30) at 13. I agree with this finding by the Board because the
`
`specification of the ’949 patent does not limit the location of the “hardware
`
`buffer”. That claim 1 requires “each received data segment” to be scatter loaded
`
`“directly from the hardware buffer to the system memory” does not mean that the
`
`data segment could not have originated in some other system memory that is
`
`physically separate from the claimed system memory. Instead, under this claim
`
`limitation, the data segment may be moved directly from a hardware buffer located
`
`in one system memory into its final location in the claimed “system memory” from
`
`which it is executed by the processor.
`
`19. Dependent claim 2 covers the multi-processor system of claim 1 in
`
`which the “scatter loader controller … loads the executable software image . . .
`
`without copying data between system memory locations on the secondary
`
`processor.” Claim 1 is not similarly limited by the phrase that the executable
`
`software image cannot be copied between system memory locations in the
`
`secondary processor. This further limiting of claim 1 by dependent claim 2
`
`confirms that claim 1 and its “hardware buffer” allows for the possibility of
`
`copying data between system memory locations. When Patent Owner wanted to
`
`narrow the claims, it drafted claims to include the narrow features, such as for
`
`11
`
`
`
`
`
`
`U.S. Patent No. 8,838,949
`Remand Declaration of Bill Lin, Ph.D.
`
`dependent claim 2. In addition, the point of claim 2 is that this claim does not
`
`cover copying data between locations within the claimed system memory, not that
`
`the claim does not cover copying data from a physically separate system memory
`
`to the claimed system memory.
`
`20. Similarly, the “hardware buffer” does not have to reside within the
`
`“hardware transport mechanism”, as Patent Owner had previously argued (see
`
`POR (Paper 16) at 14-15), for the reasons explained in my Reply Declaration (see
`
`Ex. 1023 (Lin Reply Decl.) at ¶¶ 20-25). Patent Owner’s only basis for asserting
`
`this was an exemplary embodiment described in Figure 3 of the ’949 patent. See
`
`POR (Paper 16) at 14-15; Ex. 1023 (Lin Reply Decl.) at ¶ 24. But this alone does
`
`not suggest that the “hardware buffer” could not be outside the “hardware transport
`
`mechanism”. Patent Owner’s proposal is unjustified because the language of claim
`
`1 merely requires the “hardware buffer” to be part of the “secondary processor”,
`
`not any specific place within that processor other than separate from the claimed
`
`“system memory”. Ex. 1001 (’949 patent) at claim 1 (“a secondary processor
`
`comprising … a hardware buffer”).
`
`12
`
`
`
`
`
`
`U.S. Patent No. 8,838,949
`Remand Declaration of Bill Lin, Ph.D.
`
`3.
`The “hardware buffer” can be a temporary buffer.
`In its Final Written Decision, the Board “agreed with Patent Owner
`
`21.
`
`that the ’949 patent distinguishes over prior art techniques that use a temporary
`
`buffer, based on the passages discussed above”. FWD (Paper 30) at 16
`
`(referencing ’949 patent passages at 2:23–34, 4:43–47, 5:31–35). The Board
`
`concluded that claims 1-9 and 12 have “affirmatively recited a distinct term—
`
`‘hardware buffer’—to differentiate from prior art techniques described in the ’949
`
`patent that use a ‘temporary buffer.’” Id. Similarly, the Federal Circuit also noted
`
`these passages and a number of “other specification passages that support an
`
`understanding that use of a ‘hardware buffer’ relates to one of the key claimed
`
`advances of the invention”. See Intel, 21 F.4th at 811 (noting ’949 patent passages
`
`at 7:16, 7:27-30, and 9:42-46).
`
`22. After reviewing these cited passages from the ’949 specification,
`
`which I will discuss in turn below, it is my opinion that these passages do not teach
`
`against all uses of a temporary buffer or suggest that the “hardware buffer” is one
`
`of the asserted “advances” of the claimed invention. Instead, the ’949 specification
`
`teaches against other narrower ideas that were well-known in the field at the time
`
`and do not affect Petitioner’s proposed construction of “hardware buffer”.
`
`13
`
`
`
`
`
`
`U.S. Patent No. 8,838,949
`Remand Declaration of Bill Lin, Ph.D.
`
`23. First, the passages at column 9, lines 37 to 54 distinguish the claimed
`
`invention from techniques that transfer the entire executable software image to a
`
`temporary buffer. When intermediate or temporary buffers are discussed in these
`
`passages, I understand the discussion as teaching against the use of temporary
`
`buffers storing the “entire executable software image,” not temporary buffers
`
`themselves.
`
`• “In one aspect, the executable software image is loaded into the system
`
`memory of the secondary processor without an entire executable software
`
`image being stored in the hardware buffer of the secondary processor.” Ex.
`
`1001 (’949 patent) at 9:37-41.
`
`• “Accordingly, no extra memory copy operations occur in the secondary
`
`processor in the above aspect. Thus, conventional techniques employing a
`
`temporary buffer for the entire image and the packet header handling, etc.,
`
`are bypassed in favor of a more efficient direct loading process.” Id. at
`
`9:42-46.
`
`• “Thus, the exemplary load process of FIG. 3 does not require the
`
`intermediate buffer operations traditionally required for loading a
`
`software image from a primary processor to a secondary processor. Instead
`
`14
`
`
`
`
`
`
`U.S. Patent No. 8,838,949
`Remand Declaration of Bill Lin, Ph.D.
`
`of scatter loading from a temporary buffer holding the entire image, the
`
`exemplary load process of FIG. 3 allows for direct scatter load [sic] the
`
`image segments to their respective target destinations directly from the
`
`hardware to the system memory.” Id. at 9:46-54.
`
`24. The passage at column 9, lines 37 to 46 (quoted above)—which is the
`
`only ’949 specification passage that uses “hardware buffer” and “temporary
`
`buffer” near each other—when taken in the context of the surrounding
`
`specification statements merely discloses that the claimed invention utilizes a
`
`loading technique that can be used “without an entire executable software image
`
`stored in the hardware buffer”. See Ex. 1001 (’949 patent) at 9:39-41.
`
`Consequently, prior art “conventional techniques employing a temporary buffer for
`
`the entire image” are bypassed. Id. at 9:43-46.
`
`25. Second, whereas claim 1 requires that “the image header and each
`
`data segment be[] received separately,” column 2, lines 14 to 54 in the
`
`specification’s background distinguish techniques that copy data packets
`
`containing both the actual data segments (i.e., payload) and an accompanying
`
`header that directs where the data must ultimately be loaded.
`
`15
`
`
`
`
`
`
`U.S. Patent No. 8,838,949
`Remand Declaration of Bill Lin, Ph.D.
`
`• “Often, the software image to be loaded is a binary multi-segmented image.
`
`For instance, the software image may include a header followed by multiple
`
`segments of code. When software images are loaded, from an external
`
`device (e.g., from another processor) onto a target device (e.g., a target
`
`processor) there may be an intermediate step where the binary multi-
`
`segmented image is transferred into the system memory and then later
`
`transferred into target locations by the boot loader.” Ex. 1001 (’949 patent)
`
`at 2:14-22.
`
`• “In a system in which the software image is loaded onto a target “secondary
`
`processor from a first “primary” processor, one way of performing such
`
`loading is to allocate a temporary buffer into which each packet is received,
`
`and each packet would have an associated packet header information along
`
`with the payload.” Id. at 2:23-28.
`
`• “Thus, in order to transfer the data from the primary processor's non-volatile
`
`memory to the secondary processor (e.g., to the secondary processor's
`
`volatile memory), a packet-based communication may be employed,
`
`wherein a packet header is included in each packet communicated to the
`
`secondary processor. The packets are stored in an intermediate buffer, and
`
`16
`
`
`
`
`
`
`U.S. Patent No. 8,838,949
`Remand Declaration of Bill Lin, Ph.D.
`
`some processing of the received packets is then required for that data to be
`
`stored where it needs to go (e.g., within the secondary processor's volatile
`
`memory).” Id. at 2:45-54.
`
`26. An examination of these passages makes clear that the focus is on
`
`distinguishing systems that transfer packets that include both data segments and
`
`headers, not distinguishing the use of temporary buffers. This distinction also
`
`directly corresponds with the language of the ’949 claims, which require an image
`
`header that is separately received from data segments (not receiving a packet that
`
`includes both data segments and a header). See Ex. 1001 (’949 patent) at claim 1
`
`(“the image header and each data segment being received separately”).
`
`27.
`
`In addition to the above passages from the background section, the
`
`Board also focused on the bolded portion of the passage at column 4, lines 43-47
`
`of the ’949 specification to support excluding temporary buffers:
`
`In one exemplary aspect a direct scatter load technique is
`disclosed for loading a segmented image from a primary
`processor's non-volatile memory to a secondary processor's
`volatile memory. As discussed further below, the direct scatter
`load technique avoids use of a temporary buffer.
`
`
`17
`
`
`
`
`
`
`U.S. Patent No. 8,838,949
`Remand Declaration of Bill Lin, Ph.D.
`
`This passage should, however, be read in the context of surrounding statements
`
`and the background section. The bolded portion of the passage begins with, “as
`
`discussed further below” (and the quote begins with “[i]n one exemplary aspect”)
`
`and the text that follows states:
`
`For instance, in one aspect, rather than employing a packet-
`based communication in which the image is communicated
`via packets that each include a respective header, the raw
`image data is loaded from the primary processor to the
`secondary processor. In another aspect, headers are used which
`include information used to determine the target location
`information for the data.
`
`Ex. 1001 (’949 patent) at 4:47-52. This indicates that a temporary buffer is only
`
`excluded if it receives “packet-based communication … via packets that each
`
`include a respective header”. I understand these passages as teaching against a
`
`temporary buffer receiving a packet that includes both a header and data
`
`segments over the buffer receiving the header and data segments separately, as
`
`claimed in claim 1.
`
`18
`
`
`
`
`
`
`U.S. Patent No. 8,838,949
`Remand Declaration of Bill Lin, Ph.D.
`
`28. Finally, the passage at column 5, lines 31-35 of the ’949 specification
`
`does not preclude the “hardware buffer” from being a temporary buffer. The
`
`passage here states:
`
`The modem processor 110 stores the modem executable image
`132 directly into the modem processor RAM (Random Access
`Memory) 112 to the final destination without copying the data
`into a temporary buffer in the modem processor RAM 112.
`
`Ex. 1001 (’949 patent) at 5:31-35. This portion of the specification does not teach
`
`against the use of all temporary buffers, but instead only temporary buffers that
`
`reside in the same physical “system memory” (i.e., RAM 112) as claimed into
`
`which the executable image is loaded for execution. Moreover, this passage is
`
`consistent with the specification passages demonstrating that the “hardware buffer”
`
`is physically separate from the claimed “system memory” that receives the
`
`“executable software image” for execution. See supra Section IV.A.1.
`
`29. Even if the passages discussed above are incorrectly understood as
`
`teaching against the use of a “temporary buffer”, the specification as a whole does
`
`not. The specification states that these passages merely disclose exemplary
`
`embodiments or exemplary prior art techniques. See, e.g., Ex. 1001 (’949 patent)
`
`at 4:43-36 (“In one exemplary aspect a direct scatter load technique is
`19
`
`
`
`
`
`
`U.S. Patent No. 8,838,949
`Remand Declaration of Bill Lin, Ph.D.
`
`disclosed…”); id. at 9:46-54 (“the exemplary load process of FIG. 3”); id.
`
`(discussing passage at 5:31-35 in context of Figure 1, an “Exemplary Multi-
`
`Processor”). The specification also broadly states that the “The word ‘exemplary’
`
`is used herein to mean ‘serving as an example, instance, or illustration.’ Any aspect
`
`described herein as ‘exemplary’ is not necessarily to be construed as preferred or
`
`advantageous over other aspects.” Id. at 4:22-25. Thus, I do not understand these
`
`passages as limiting the scope of the term “hardware buffer” to exclude the use of
`
`all temporary or intermediate buffers.
`
`4.
`
`The prosecution history supports my construction of
`“hardware buffer”.
`30. The prosecution history of the ’949 patent offers further insight on the
`
`meaning of the term “hardware buffer”.
`
`31. During prosecution, the pending ’949 patent claims were initially
`
`rejected by the Patent Office as anticipated by Svensson. In the Office Action, the
`
`Examiner specifically explained how the various limitations of the pending claims
`
`of the application were met by disclosures in Svensson. In particular, the
`
`Examiner identified the intermediate storage area disclosed in Svensson as the
`
`“hardware buffer” of the ’949 patent. See Ex. 1004 (7/19/13 Office Action) at 2
`
`(“Svensson teaches a secondary processor [client processor 104] comprising
`20
`
`
`
`
`
`
`U.S. Patent No. 8,838,949
`Remand Declaration of Bill Lin, Ph.D.
`
`system memory [DSP XRAM 110] and a hardware buffer [An intermediate storage
`
`area is defined within the memory 108] for receiving at a [sic] least a portion of an
`
`executable software image.”).
`
`32. Rather than argue that Svensson does not disclose a “hardware
`
`buffer”, Patent Owner amended the claims to overcome the rejection by adding
`
`new limitations relating to image headers and data segments. See Ex. 1005
`
`(10/17/13 Response) at 2 (Patent Owner amending claim 1 to require “the image
`
`header and each data segment being received separately” and a scatter loader
`
`controller configured “to load the image header” and “to scatter load each received
`
`data segment based at least in part on the loaded image header.”). Patent Owner
`
`relied on these new limitations in arguing to distinguish Svensson:
`
`In contrast to Svensson, claim 1 recites that the image header
`and each data segment are received separately. . . [and this] is
`patentably distinguishable from receiving the data and the
`associated header, as disclosed in Svensson.”
`
`The individual data segments of claim 1 are not concatenated
`with the header files . . . [and] loading each data segment
`directly from the hardware buffer to the system memory, as
`recited in claim 1, is patentably distinguishable from
`
`21
`
`
`
`
`
`
`
`
`U.S. Patent No. 8,838,949
`Remand Declaration of Bill Lin, Ph.D.
`
`concatenating the data blocks and headers in the intermediate
`storage area and then transferring the concatenated data to the
`memory, as recited in Svensson.
`
`Id. at 8-9.
`33. These arguments track the distinctions made in the patent background
`
`and offer helpful guidance on the elements of the claimed invention that Patent
`
`Owner understood as being novel. These prosecution amendments and arguments
`
`make clear that the “asserted advance” of the ’949 patent, see Intel, 21 F.4th at
`
`811, was not the “hardware buffer,” since it existed in the prior art and Patent
`
`Owner did not argue to the contrary. Instead, the purported advance relates to the
`
`very elements added by amendment during prosecution, including the separate
`
`receipt of the header and data segments. These are the same features that the
`
`specification uses to distinguish the prior art. See supra ¶¶ 23-29.
`
`B.
`
`The Intermediate Storage Area of Bauer and Svensson Is a
`“Hardware Buffer”
`34. Bauer and Svensson combined disclose an intermediate storage area
`
`that is a “hardware buffer” under my proposed construction.
`
`35. As discussed in the IPR petitions and in my prior Declarations, Bauer
`
`and Svensson disclose a multi-processor system with a secondary processor
`
`comprising a system memory and a hardware buffer. See Ex. 1023 (Lin Reply
`22
`
`
`
`
`
`
`U.S. Patent No. 8,838,949
`Remand Declaration of Bill Lin, Ph.D.
`
`Decl.) at ¶ 62; Ex. 1002 (Lin Op. Decl.) at ¶ 110; Petitioner (Paper 3) at 26-27. For
`
`example, Bauer discloses in Figure 2 (inserted below) that its secondary processor
`
`(DSP device) includes a “hardware buffer” (intermediate storage area (Int. Store
`
`Area) within the DSP SARAM & DARAM memory 208), and a separate “system
`
`memory” (DSP XRAM 210).
`
`Ex. 1009 (Bauer) at Fig 2; Ex. 1010 (Svensson) at Fig. 1; see also Ex. 1009 at ¶¶
`
`35-36; Ex. 1010 at 3:54-58, 3:64-4:5.3
`
`
`
`
`3 Bauer’s Figure 2 is the same as Svensson’s Figure 1, although the numerals
`
`differ. Specifically, DSP SARAM & DARAM is numeral 108 in Svensson and
`
`23
`
`
`
`
`
`
`U.S. Patent No. 8,838,949
`Remand Declaration of Bill Lin, Ph.D.
`
`36.
`
`In Svensson, while the intermediate storage area (the claimed
`
`“hardware buffer”) is responsible for temporarily storing the software image,
Accessing this document will incur an additional charge of $.
After purchase, you can access this document again without charge.
Accept $ Charge
Still Working On It
This document is taking longer than usual to download. This can happen if we need to contact the court directly to obtain the document and their servers are running slowly.
Give it another minute or two to complete, and then try the refresh button.
A few More Minutes ... Still Working
It can take up to 5 minutes for us to download a document if the court servers are running slowly.
Thank you for your continued patience.
This document could not be displayed.
We could not find this document within its docket. Please go back to the docket page and check the link. If that does not work, go back to the docket and refresh it to pull the newest information.
Your account does not support viewing this document.
You need a Paid Account to view this document. Click here to change your account type.
Your account does not support viewing this document.
Set your membership
status to view this document.
With a Docket Alarm membership, you'll
get a whole lot more, including:
- Up-to-date information for this case.
- Email alerts whenever there is an update.
- Full text search for other cases.
- Get email alerts whenever a new case matches your search.
One Moment Please
The filing “” is large (MB) and is being downloaded.
Please refresh this page in a few minutes to see if the filing has been downloaded. The filing will also be emailed to you when the download completes.
Your document is on its way!
If you do not receive the document in five minutes, contact support at support@docketalarm.com.
Sealed Document
We are unable to display this document, it may be under a court ordered seal.
If you have proper credentials to access the file, you may proceed directly to the court's system using your government issued username and password.
Access Government Site
