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`UNITED STATES PATENT AND TRADEMARK OFFICE
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`____________________________________________
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`____________________________________________
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`Intel Corporation
`Petitioner
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`
`
`v.
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`Qualcomm Incorporated
`Patent Owner of U.S. Patent No. 8,838,949
`Claims 18-21
`____________________________________________
`
`Trial No. IPR2018-01336
`____________________________________________
`
`
`
`DECLARATION OF BILL LIN, PH.D.
`ON BEHALF OF PETITIONER
`
`IPR2018-01334
`Intel v. Qualcomm
`INTEL 1021
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`
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`U.S. Patent No. 8,838,949
`Declaration of Bill Lin, Ph.D.
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`TABLE OF CONTENTS
`I.
`BACKGROUND ............................................................................................. 1
`II. MATERIALS CONSIDERED ........................................................................ 4
`III. LEGAL PRINCIPLES ..................................................................................... 5
`A.
`Claim Construction ............................................................................... 5
`B.
`Anticipation ........................................................................................... 6
`C.
`Obviousness .......................................................................................... 7
`IV. SUMMARY OF OPINIONS ......................................................................... 10
`V.
`BRIEF DESCRIPTION OF THE TECHNOLOGY ..................................... 10
`A. Multi-Processor Systems ..................................................................... 10
`1.
`Processor-To-Processor Communications ................................ 10
`2.
`Processor Software Code .......................................................... 14
`3.
`Characteristics of Memory ........................................................ 15
`Storing, Loading, and Executing Processor Software
`Code ..................................................................................................... 16
`1.
`Storing the Processor Software Code in Memory .................... 16
`2.
`Loading and Executing Multi-Segmented Software
`Images ....................................................................................... 17
`Sharing Memory in Multi-Processor Systems .......................... 19
`3.
`Boot Loading ....................................................................................... 20
`C.
`VI. OVERVIEW OF THE ʼ949 PATENT .......................................................... 22
`A. Alleged Problem of the Prior Art ........................................................ 22
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`B.
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`Declaration of Bill Lin, Ph.D.
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`X.
`
`B.
`Purported Solution of the ’949 Patent ................................................. 23
`Prosecution History of the ’949 Patent ............................................... 30
`C.
`VII. LEVEL OF ORDINARY SKILL IN THE ART ........................................... 33
`VIII. CLAIM CONSTRUCTION .......................................................................... 34
`A.
`“image header” (claims 18 and 20) ..................................................... 34
`IX. OVERVIEW OF PRINCIPAL PRIOR ART REFERENCES ...................... 35
`A.
`Svensson (Ex-1210) ............................................................................ 35
`B.
`Bauer (Ex-1209) .................................................................................. 39
`C.
`Kim (Ex-1211) (Including English Translation (Ex-
`1212)) .................................................................................................. 43
`Lim (Ex-1214) ..................................................................................... 46
`D.
`SPECIFIC GROUNDS FOR CHALLENGE ................................................ 49
`A. Ground 1: Claims 18-21 Are Rendered Obvious By The
`Combination Of Bauer, Svensson, Kim, And Lim ............................. 49
`1.
`Reference to “Bauer and Svensson Combined” ....................... 49
`2.
`Claim 18 .................................................................................... 51
`3.
`Claim 19: “The multi-processor system of claim
`18 integrated into at least one of a mobile phone …
`a computer, a hand-held personal communication
`systems (PCS) unit, a portable data unit….” ............................ 91
`Claim 20 .................................................................................... 93
`Claim 21: “The multi-processor system of claim
`20 integrated into at least one of a mobile phone, a
`set top box, a music player, a video player, an
`entertainment unit, a navigation device, a
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`4.
`5.
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`computer, a hand-held personal communication
`systems (PCS) unit, a portable data unit, and a
`fixed location data unit.” ......................................................... 100
`XI. AVAILABILITY FOR CROSS-EXAMINATION .................................... 175
`XII. RIGHT TO SUPPLEMENT ........................................................................ 175
`XIII. JURAT ......................................................................................................... 176
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`U.S. Patent No. 8,838,949
`Declaration of Bill Lin, Ph.D.
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`1.
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`I, Bill Lin, Ph.D. declare as follows:
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`BACKGROUND
`2.
`I am currently Professor and Vice Chair of Electrical and Computer
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`
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`I.
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`Engineering at the University of California, San Diego (UCSD). I am also Adjunct
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`Professor of Computer Science and Engineering at UCSD.
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`3. My Curriculum Vitae, which states my qualifications more fully, is
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`attached as Appendix A. A list of all cases in which I have testified as an expert at
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`trial or by deposition in the last four years is also included in Appendix A.
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`4.
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`I received a Bachelor’s of Science degree in 1985, a Master’s of
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`Science degree in 1988, and a Ph.D. in 1991, all in Electrical Engineering and
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`Computer Sciences from the University of California, Berkeley.
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`5.
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`I joined UCSD in 1997, and I have been a tenured professor since
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`1999. My teaching and research has focused on computer architecture and
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`computer network problems, including the design of multiprocessor and multi-core
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`processor architectures, multiprocessor and multi-core processor interconnection
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`buses and networks, network processors, systems-on-chips, and data networks. I
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`regularly teach a senior-level design course on the design of advanced processors,
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`and I have taught graduate courses in hardware/software co-design and advanced
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`special topics in computer architecture.
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`6.
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`At UCSD, I am a Principal Investigator in the UCSD Center for
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`
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`Networked Systems (CNS). CNS brings together researchers to work on a range
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`of challenges in the design of future networked systems. My contribution to CNS
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`has been expertise in the design of computer architecture solutions for packet
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`processing and computer networking. I am also a Principal Investigator in the
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`UCSD Center for Wireless Communications (CWC). CWC brings together
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`researchers to work on a range of challenges in the design of future wireless
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`communications systems. My contribution to CWC has been expertise in the
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`design of multi-core processor architectures for wireless communications and
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`mobile computing.
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`7.
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`Prior to joining UCSD, I was the Head of the Systems and
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`Communications Group at IMEC in Leuven, Belgium, where I led a team of
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`researchers who worked on a range of computer design problems, including
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`hardware/software co-design, processor interfaces, multiprocessor and multi-core
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`processor design methodologies, and specialized processors for wireless
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`communications and computer networking.
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`8.
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`During my career, I have received or worked on research efforts that
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`received millions of dollars in research funding from both government agencies
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`and industry, including funding for research in multi-core processor design,
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`system-on-chips, hardware/software co-design, packet processing, and computer
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`networks.
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`9.
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`I have served as an Associate or Guest Editor for several journals
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`published by the Association for Computing Machinery (“ACM”) and the Institute
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`of Electrical and Electronics Engineers (“IEEE”). I have also served as General
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`Chair of several ACM/IEEE conferences, and on the Organizing or Steering
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`Committees of many ACM/IEEE conferences, and I have served on the Technical
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`Program Committees of numerous ACM/IEEE conferences. I am the author of
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`over 170 peer-reviewed publications in the field of computer engineering dating to
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`the 1980s, including journal articles, conference papers, book chapters, technical
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`reports, and invited papers. A number of these publications have received best
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`paper awards or distinguished paper citations. I have also given numerous invited
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`and keynote talks around the world. A list of my publications within the last ten
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`years is included in my CV.
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`10.
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`I am the inventor of five patents: U.S. Patent Nos. 8,443,444,
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`7,860,004, 7,672,005, 5,870,588, and 5,748,487.
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`11.
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`I have been retained by counsel for Intel Corporation (“Petitioner”) as
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`an independent expert witness for the above captioned Petition for Inter Partes
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`Review of U.S. Patent No. 8,838,949 (the “’949 patent”) (Ex-1201). I am being
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`compensated at my normal hourly consulting rate of $550 for my work. My
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`Declaration of Bill Lin, Ph.D.
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`compensation is not dependent on and in no way affects the substance of my
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`statements in this Declaration.
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`12.
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`I have no financial interest in the Petitioner. I similarly have no
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`financial interest in the ’949 patent, and have had no contact with the named
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`inventors of the ’949 patent.
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`II. MATERIALS CONSIDERED
`13.
`I have reviewed the specification, claims, and file history of the ’949
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`patent. I understand that the ’949 patent claims priority to U.S. Provisional
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`Application No. 61/324,035, filed April 14, 2010, U.S. Provisional Application
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`No. 61/316,369, filed March 22, 2010, U.S. Provisional Application No.
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`61/324,122, filed April 14, 2010, and U.S. Provisional Application No.
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`61/325,519, filed April 19, 2010.
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`14.
`
`I have also reviewed the following references, all of which I
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`understand to be prior art to the ’949 patent:
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`U.S. Patent Application Publication No. US2006/0288019A1 to
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`Bauer et al. (“Bauer”) (Ex-1209)
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`U.S. Patent No. 7,356,680 to Svensson et al. (“Svensson”) (Ex-
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`1210).
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`Korean Patent Application Publication No. 10-2002-0036354 to
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`Kim (“Kim”) (Ex-1211) (English language translation – Ex-
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`1212).
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`U.S. Patent No. 7,203,829 to Lim (“Lim”) (Ex-1214)
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`15.
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`In addition to the documents listed above, I have also reviewed the
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`file history of the ’949 patent, all of the documents listed in Petitioner’s List of
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`Exhibits in the accompanying petition and all other documents cited in this
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`declaration.
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`III. LEGAL PRINCIPLES
`16.
`I am not an attorney. For the purposes of this declaration, I have been
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`informed about certain aspects of the law that are relevant to my opinions. My
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`understanding of the law is as follows:
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`A. Claim Construction
`17.
`I have been informed that claim construction is a matter of law and
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`that the final claim construction will ultimately be determined by the Board. For
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`the purposes of my analysis in this proceeding and with respect to the prior art, I
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`have been informed that patents are currently reviewed in an inter partes review
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`(IPR) proceeding under the “broadest reasonable interpretation” standard
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`(hereinafter “BRI standard”). I also have been informed that IPRs may soon be
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`reviewed under what is known as “the Phillips standard.”
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`18.
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`I have been informed that the BRI standard refers to the broadest
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`reasonable interpretation that a person of ordinary skill in the art would give to a
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`claim term in light of the specification.
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`19.
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`I have been informed that under the Phillips standard, claim terms are
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`generally given their plain and ordinary meaning as understood by a person of
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`ordinary skill in the art at the time of the invention, with the claim term read not
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`only in the context of the particular claim in which the disputed term appears, but
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`also in the context of the entire patent, including the specification.
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`20.
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`I have been informed that the patentee can serve as his or her own
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`lexicographer. As such, if a claim term is provided with a specific definition in the
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`specification, that claim term should be interpreted in light of the particular
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`definition provided by the patentee.
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`B. Anticipation
`21.
`I have been informed and understand that a patent claim is invalid if it
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`is “anticipated” by prior art. For the claim to be invalid because it is anticipated,
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`all of its requirements must have existed in a single device or method that predates
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`the claimed invention, or must have been described in a single publication or
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`patent that predates the claimed invention. A patent claim may be “anticipated” if
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`each element of that claim is present either explicitly, implicitly, or inherently in a
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`single prior art reference. I have also been informed that, to be an inherent
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`disclosure, the prior art reference must necessarily disclose the limitation, and the
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`fact that the reference might possibly practice or contain a claimed limitation is
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`insufficient to establish that the reference inherently teaches the limitation.
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`C. Obviousness
`22.
`I have been informed and understand that a patent claim is invalid if
`
`the claimed invention would have been obvious to a person of ordinary skill in the
`
`art at the time the application was filed. This means that, even if all of the
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`requirements of a claim are not found in a single prior art reference, the claim is
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`not patentable if the differences between the subject matter in the prior art and the
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`subject matter in the claim would have been obvious to a person of ordinary skill in
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`the art at the time the application was filed.
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`23.
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`I have been informed and understand that a determination of whether
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`a claim would have been obvious should be based upon several factors, including,
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`among others:
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`
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`the level of ordinary skill in the art at the time the application
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`was filed;
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`the scope and content of the prior art; and
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`what differences, if any, existed between the claimed invention
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`and the prior art.
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`24.
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`I have been informed and understand that the teachings of two or
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`more references may be combined in the same way as disclosed in the claims, if
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`such a combination would have been obvious to one having ordinary skill in the
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`art. In determining whether a combination based on either a single reference or
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`multiple references would have been obvious, it is appropriate to consider, among
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`other factors:
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`whether the teachings of the prior art references disclose known
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`concepts combined in familiar ways, which, when combined,
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`would yield predictable results;
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`whether a person of ordinary skill in the art could implement a
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`predictable variation, and would see the benefit of doing so;
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`whether the claimed elements represent one of a limited number
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`of known design choices, and would have a reasonable
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`expectation of success by those skilled in the art;
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`Declaration of Bill Lin, Ph.D.
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`whether a person of ordinary skill would have recognized a
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`reason to combine known elements in the manner described in
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`the claim;
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`whether there is some teaching or suggestion in the prior art to
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`make the modification or combination of elements claimed in
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`the patent; and
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`whether the innovation applies a known technique that had been
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`used to improve a similar device or method in a similar way.
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`25.
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`I understand that one of ordinary skill in the art has ordinary
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`creativity, and is not an automaton.
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`26.
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`I understand that in considering obviousness, it is important not to
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`determine obviousness using the benefit of hindsight derived from the patent being
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`considered.
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`27.
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`I have been informed and understand that a single reference alone can
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`render a patent claim obvious, if any differences between that reference and the
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`claims would have been obvious to a person of ordinary skill in the art at the time
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`of the alleged invention—that is, if the person of ordinary skill could readily adapt
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`the reference to meet the claims of the patent, by applying known concepts to
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`achieve expected results in the adaptation of the reference.
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`Declaration of Bill Lin, Ph.D.
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`IV. SUMMARY OF OPINIONS
`28.
`It is my opinion that every limitation of claims 18-21 of the ’949
`
`patent is disclosed by the prior art, and that claims 18-21 are rendered obvious by
`
`the prior art cited in this declaration.
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`V. BRIEF DESCRIPTION OF THE TECHNOLOGY
`A. Multi-Processor Systems
`1.
`Processor-To-Processor Communications
`29. The ’949 patent generally relates to communications between
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`processors. Processors are common components in electrical devices that perform
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`various functions to make the devices operate. Electrical devices may have
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`multiple processors to handle different responsibilities. For example, a mobile
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`telephone may include a “baseband” processor—which the ’949 patent calls a
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`“modem” processor—and an “application” processor. Ex-1201, 1:41-44.
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`30. The baseband/modem processor typically performs tasks relating to
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`the transmission and reception of data to/from other devices over a network such as
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`a wireless communication network. For example, Figure 5 of the ’949 patent
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`shows a mobile telephone 520 communicating with base stations 540 in a wireless
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`communication system 500.
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`Declaration of Bill Lin, Ph.D.
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`Ex-1201, Fig. 5.
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`31. The baseband/modem processor in the mobile telephone 520 is
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`responsible for sending data to and receiving data from base stations 540. The
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`base stations 540 facilitate communication between the mobile telephone 520 and
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`other devices, such as a portable computer 530, in the wireless communication
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`system 500. Ex-1201, 11:25-39, Fig. 5.
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`32. The application processor typically runs applications and other
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`computer programs on the mobile telephone—e.g., email applications, video chat,
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`text messaging, phone applications, GPS applications, etc.
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`33. The baseband/modem and application processors need to
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`communicate with each other. For example, when a user of a mobile telephone
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`composes an email or text message using an application running on the application
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`processor, the application processor must send the message to the
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`baseband/modem processor so that the baseband/modem processor can transmit the
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`message to the base station. Similarly, when a mobile telephone receives data
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`from the base station, the baseband/modem processor receives the data and then
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`transfers it to the application processor so that the user can view the data in an
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`email or other application.
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`34. The baseband/modem and application processors typically
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`communicate with each other by sending pieces of data over a “bus.” A bus,
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`sometimes referred to as an “interface,” is typically a set of wires over which
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`processors send electrical signals to each other. For example, Figure 2 of the ’949
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`patent shows two processors (Application Processor 204 and Modem Processor
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`210) connected by Inter-Chip Communication Bus 234.
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`Ex-1201, Fig. 2.
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`35. Many different types of buses were known prior to the alleged
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`invention of the ’949 patent. To enable compatibility between processors of
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`different manufacturers, buses usually operate according to one of a number of
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`well-known standards. Standardized buses that were commonly used in mobile
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`telephones and other multi-processor devices include High Speed Synchronous
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`Interface (HSI), Universal Serial Bus (USB), USB High Speed Inter-Chip (HSIC),
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`Mobile Industry Processor Interface (MIPI), Secure Digital Input/Output (SDIO),
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`Universal Asynchronous Receiver-Transmitter (UART), Serial Peripheral Interface
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`(SPI) and Inter-Integrated Ciruit (I2C). See, e.g., Ex-1201, 5:35-43; see also Ex-
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`1213, ¶32, Fig. 5 (disclosing interfaces such as “one or more universal serial bus
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`(USB) interfaces, micro-USB interfaces, universal asynchronous receiver-
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`transmitter (UART) interfaces, general purpose input/output (GPIO) interfaces,
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`control/status lines, control/data lines, shared memory, and so forth”).
`
`2.
`Processor Software Code
`36. A processor operates by executing software code that instructs the
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`processor to perform specific operations. There are different types of software
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`code for performing different types of operations. For example, when a processor
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`is initially powered up, it typically executes “boot code” that instructs the
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`processor to perform certain initialization operations. Such initialization
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`operations may include determining what other devices may be connected to the
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`processor and where such other devices may be located. For example, the boot
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`code may instruct the processor to determine addresses associated with hardware
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`peripherals, such as a keypad, a visual display, and memory.
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`37. After the processor executes its boot code, it typically executes
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`“program code” that instructs the processor to perform various operations that the
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`processor has been designated to perform. For example, in the case of the above-
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`described baseband/modem processor, the program code may instruct the
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`baseband/modem processor to transfer received data to the application processor so
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`that a user can view the data in an email or other application. In the case of the
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`above-described application processor, the program code may instruct the
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`application processor to send a message to the baseband/modem processor so that
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`the baseband/modem processor can transmit the message to the base station.
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`3.
`Characteristics of Memory
`38. To be executed, software code must be stored in memory that is
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`accessible to the processor. The processor reads the code from the memory and
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`then executes the code. There are basically two types of memory—non-volatile
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`memory and volatile memory. Non-volatile (or persistent) memory is designed to
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`store code and other data regardless of whether power is being applied to the
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`memory. In contrast, volatile memory can only store code and other data when
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`power is being applied to the memory. That is, once power is removed from
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`volatile memory, all code and other data previously stored in the memory will be
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`lost.
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`39. Examples of non-volatile memory include electrically erasable
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`programmable read-only memory (EEPROM) and flash memory. These types of
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`non-volatile memory, as well as others, have characteristics that make them
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`suitable for long-term persistent storage. For example, non-volatile memory can
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`store code and other data for long periods of time after they have been initially
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`programmed regardless of whether power is being applied to the memory.
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`However, non-volatile memory typically costs more, provides lower performance
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`(e.g., operates slower), and requires more space than volatile memory.
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`40. Examples of volatile memory include random access memory (RAM),
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`dynamic RAM (DRAM) and static RAM (SRAM). These types of volatile
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`memory, as well as others, have characteristics that make them suitable for short-
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`term storage. For example, code and other data can be quickly stored and retrieved
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`from volatile memory, thereby increasing system performance. But any code or
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`other data stored in volatile memory is lost after power is removed from the
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`memory, so using volatile memory for long-term storage is typically not feasible in
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`devices that may lose power (e.g., mobile telephones).
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`41. A data buffer is typically used as a temporary storage area that allows
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`data to be moved from one location to another. The data buffer is often some
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`portion of volatile memory.
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`B.
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`Storing, Loading, and Executing Processor Software Code
`1.
`Storing the Processor Software Code in Memory
`42. Software code is typically stored, at least initially, in non-volatile
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`memory. The code is often later transferred from non-volatile memory to volatile
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`memory, which is typically faster (and can be less expensive) than non-volatile
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`memory. It is common for system designers to have processors use a type of
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`volatile memory as a work space where the processor can execute software and
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`perform other processing functions. When coupled to a processor, engineers will
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`often refer to this type of volatile memory coupled to the processor as “system
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`memory.”
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`43. Software code is typically packaged and stored in memory as a
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`software file or program called an “executable image” or “executable software
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`image.” The ’949 patent makes clear that executable software images were known
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`in the prior art, including “multi-segmented” images that included (1) one or more
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`headers, tables, or other structures that contain information about the overall image
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`and/or its underlying data, and (2) one or more segments containing code or other
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`data used by the image, which the patent refers to as “data segments.”1 Ex-1201,
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`2:14-16, 4:34-42.
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`2.
`Loading and Executing Multi-Segmented Software Images
`44. Before a processor can execute a multi-segmented software image, the
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`processor usually must load the image into its system memory, from where it is
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`1 References to “data” include code and/or data, and references to “data segment”
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`include segments containing code and/or data.
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`17
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`then executed. Most multi-segmented executable software images are designed to
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`be loaded in multiple steps. In the first step, the processor reads information in the
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`one or more headers, tables, and/or other structures of the software image. That
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`information might identify the type of image (e.g., an image format such as
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`Executable and Linking Format (ELF)), the size of the image, the number and size
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`of any data segments in the image, the storage locations of the data segments, and
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`the locations in system memory where the data segments are to be loaded for
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`execution. In one or more other steps, the processor uses that information to load
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`the data segments into memory and execute the image.
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`45. When transferred into memory, the data segments of a software image
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`can be stored either in contiguous (i.e., continuous) memory locations or spread
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`across non-contiguous (i.e., non-continuous) memory locations. “Scatter loading”
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`is a well-known loading process in which one or more portions of a software image
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`are loaded (or “scattered”) into memory. When there are multiple portions of a
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`software image, the portions are loaded across either contiguous or non-contiguous
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`locations in memory. Given this aspect of scatter loading, a mapping mechanism
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`is typically needed to allow a processor (or other component loading the code or
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`other data) to know the destination locations where the various parts of the image
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`are to be stored in memory. Many prior art executable software image formats
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`(such as ELF) were designed for scatter loading—by including information in the
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`image about where segments of the image should be loaded in memory for later
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`execution.
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`3.
`Sharing Memory in Multi-Processor Systems
`In order to reduce costs and space requirements in a multi-processor
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`46.
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`system, such as a mobile telephone having a baseband/modem processor and an
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`application processor, program code for both processors may be stored in a single
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`non-volatile memory. For example, the application processor may have direct
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`access to non-volatile memory that stores program code for both the application
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`processor and the baseband/modem processor. The application processor may also
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`have direct access to volatile memory for storing its program code after power up.
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`47. The baseband/modem processor, on the other hand, may have direct
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`access to only volatile memory and not non-volatile memory. Upon power up,
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`therefore, the application processor may have to transfer program code from non-
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`volatile memory to volatile memory so that the baseband/modem processor can use
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`it. The application processor can transfer the baseband/modem processor’s
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`program code from the non-volatile memory connected to the application
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`processor to the baseband/modem processor, which may then store the program
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`code in the volatile memory connected to the baseband/modem processor.
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`48. The transfer of the program code is typically performed by
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`
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`transferring segments of code or other data over a bus, where it is then loaded into
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`memory. A large software image may be split into smaller data segments to
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`facilitate its transfer. Each segment of data is typically transferred with a header.
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`Each segment of data is typically received by a processor and stored in memory
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`temporarily while the processor reads the information in the header to determine
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`where the data payload should be later stored in the same or different memory.
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`Thereafter, the processor stores the data at the destination address in memory.
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`C. Boot Loading
`49. When a computing device is first powered on, one or more processors
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`in the device typically load and execute software (sometimes called “boot code” or
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`“boot software”) to enable the processor(s) to begin to operate. Because a
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`processor must execute its boot code each time it powers up, the boot code is often
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`stored in a non-volatile memory that is coupled to the processor. In this
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`arrangement, during boot up, the boot code is typically loaded and executed from
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`system memory that is coupled to the processor.
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`50.
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`In a multi-processor system, each processor can store its own boot
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`code, as the ’949 patent acknowledges is prior art. Ex-1201, 1:38-44 (“Processors
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`may require some software code, commonly referred to as boot code, to be
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`executed for [booting] up. In a multi-processor system, each processor may
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`require respective boot code for booting up. As an example, in a smartphone
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`device that includes an application processor and a modem processor, each of the
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`processors may have respective boot code for booting up.”), 1:51-56 (“For
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`instance, a processor’s boot code may be stored to the processor’s respective non-
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`volatile memory (e.g., Flash memory, read-only memory (ROM), etc.), and upon
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`power-up the boot code software is loaded for execution by the processor from its
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`respective non-volatile memory.”).
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`51. The boot-up of a processor often occurs in multiple stages. As the
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`first step, a primitive “boot loader” function usually loads and then executes a
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`relatively small amount of boot code stored in a local boot ROM that the processor
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`can access easily. This first stage enables the processor to begin performing basic
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`functions. In one or more later stages, the processor then typically loads additional
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`boot code (usually stored in a different, larger non-volatile memory), which
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`enables the processor to perform more sophi