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`UNITED STATES PATENT AND TRADEMARK OFFICE
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`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`
`INTEL CORPORATION,
`Petitioner
`
`v.
`
`QUALCOMM INCORPORATED,
`Patent Owner
`
`Patent No. 8,838,949
`
`
`
`
`Case IPR2018-01334
`
`PATENT OWNER’S RESPONSE BRIEF ON REMAND1
`
`
`1 IPR2018-01335 and IPR2018-01336 have been consolidated with IPR2018-
`01334, and Patent Owner will file this brief only in IPR2018-01334. All citations
`are to IPR2018-01334 unless otherwise noted.
`
`
`
`
`
`IPR2018-01334
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`B.
`
`C.
`D.
`
`TABLE OF CONTENTS
`TABLE OF AUTHORITIES ................................................................................... ii
`LIST OF PATENT OWNER EXHIBITS ............................................................... iii
`I.
`INTRODUCTION .......................................................................................... 1
`II.
`CLAIM CONSTRUCTION—“HARDWARE BUFFER” ............................ 3
`A.
`The ’949 Patent Describes Conventional Loading Processes
`That Use Temporary Buffers In System Memory ............................... 3
`The ’949 Invention’s Use Of A Dedicated, Permanent
`Hardware Buffer Enables More Efficient Loading .............................. 6
`Inventor Testimony Supports Qualcomm’s Construction ................... 8
`Intel’s Arguments Contrary To Qualcomm’s Construction Are
`Wrong ................................................................................................... 9
`Intel’s Proposed Construction Is Overly Broad And Does Not
`Capture The Scope Of The Actual Invention ..................................... 14
`III. CLAIMS 1-9 AND 12 ARE NOT UNPATENTABLE ............................... 15
`A.
`The ISA Is Not A Permanent Buffer .................................................. 16
`B.
`The ISA Is Not A Dedicated Buffer Distinct From System
`Memory .............................................................................................. 17
`IV. CLAIMS 16 AND 17 ................................................................................... 19
`V.
`CONCLUSION ............................................................................................. 20
`
`E.
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`TABLE OF AUTHORITIES
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`IPR2018-01334
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`Page
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`CASES
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`3M Innovative Props. Co. v. Avery Dennison Corp.,
`350 F.3d 1365 (Fed. Cir. 2003) .......................................................................... 15
`
`Fantasy Sports Props., Inc. v. Sportsline.com, Inc.,
`287 F.3d 1108 (Fed. Cir. 2002) .......................................................................... 10
`
`Intel Corp. v. Qualcomm Inc.,
`21 F.4th 801 (Fed. Cir. 2021) ......................................................................passim
`
`Laitram Corp. v. Rexnord, Inc.,
`939 F.2d 1533 (Fed. Cir. 1991) .......................................................................... 10
`
`Salazar v. Procter & Gamble Co.,
`414 F.3d 1342 (Fed. Cir. 2005) .......................................................................... 15
`
`
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`-ii-
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`IPR2018-01334
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`LIST OF PATENT OWNER EXHIBITS
`Transcript of the Deposition of Dr. Bill Lin
`Ex. 2001
`Ex. 2002 U.S. Provisional Patent Application No. 61/324,122
`Ex. 2003 Qualcomm v. Apple, Case No. 3:17-CV-1375-DMS-MDD, S.D. Cal.,
`Transcript of Jury Trial, Day 2, Volume 2-A
`Ex. 2004 Qualcomm v. Apple, Case No. 3:17-CV-1375-DMS-MDD, S.D. Cal.,
`Transcript of Jury Trial, Day 2, Volume 2-B
`Ex. 2005 Qualcomm v. Apple, Case No. 3:17-CV-1375-DMS-MDD, S.D. Cal.,
`Transcript of Jury Trial, Day 6, Volume 6-B
`Ex. 2006 Qualcomm v. Apple, Case No. 3:17-CV-1375-DMS-MDD, S.D. Cal.,
`Transcript of Jury Trial, Day 7, Volume 7-A
`Ex. 2007 Declaration of Dr. Martin Rinard
`Ex. 2008
`Transcript of Second Deposition of Dr. Bill Lin
`Ex. 2009
`Patent Owner’s Demonstratives
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`Ex. 2010
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`Ex. 2011 Oxford University Press, “A Dictionary of Computing” (6th ed.)
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`Ex. 2012
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`Lin Deposition Transcript (May 5, 2022)
`
`“Computer Architecture—A Quantitative Approach” by John L.
`Hennessy and David A. Patterson (5th ed.)
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`
`Ex. 2013
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`Ex. 2014
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`FIFO Architecture, Functions, and Applications (Texas Instruments,
`1999)
`
`“Computer Architecture—A Quantitative Approach” by John L.
`Hennessy and David A. Patterson (4th ed.)
`
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`Ex. 2015 Remand Declaration of Dr. Martin Rinard
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`I.
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`INTRODUCTION
`The primary issue before the Board on remand is the meaning of the claim
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`term “hardware buffer.” Claims 1-9 of the ’949 patent are directed to a multi-
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`processor system including “system memory and a hardware buffer for receiving an
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`image header and at least one data segment of an executable software image.” The
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`claimed multi-processor system also includes a scatter loader controller configured
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`“to scatter load each received data segment … directly from the hardware buffer to
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`the system memory.” Dependent claim 2 further recites that “the scatter loader
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`controller is configured to load the executable software image directly from the
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`hardware buffer to the system memory of the secondary processor without copying
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`data between system memory locations on the secondary processor.”
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`Analyzing this claim language, the Federal Circuit determined that “the
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`meaning of ‘hardware buffer’ relates to the ability to move the software image
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`‘directly’ to the second processor’s system memory and to avoid ‘copying data
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`between system memory locations.’” Intel Corp. v. Qualcomm Inc., 21 F.4th 801,
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`810 (Fed. Cir. 2021) (hereinafter, the “Opinion”). The court further found that
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`“because claim 1 requires both a ‘system memory’ and a ‘hardware buffer,’ there
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`must be some distinction between those two concepts.” Id.
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`The Federal Circuit determined, however, that these “conclusions from the
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`claim language advance the claim-construction inquiry only so far.” Id. “What is
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`needed, then is an analysis of the specification to arrive at an understanding of what
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`it teaches about what a ‘hardware buffer’ is.” Id.; see id. at 811 (“What is needed in
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`this case is a more substance-focused analysis than is yet present . . . .”). In this brief,
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`Qualcomm provides the “substance-focused analysis” that the Federal Circuit found
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`missing from the Board’s decision. In view of the claim language and the analysis
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`herein, the term “hardware buffer” should be construed as a permanent, dedicated
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`buffer that is distinct from system memory. This construction is consistent with the
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`Federal Circuit’s decision and captures what the inventors actually invented and
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`intended to envelop with the claim. See id. at 809.
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`Intel’s proposed construction, by contrast, is divorced from the invention
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`described and claimed in the ’949 patent. Intel now asserts that the claimed
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`“hardware buffer” can be located in system memory (Intel Br. at 6), but the Federal
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`Circuit has already rejected that argument. Opinion at 810-11. Moreover, a
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`hardware buffer formed in system memory would eviscerate the invention described
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`in the ’949 patent. As recognized by the Federal Circuit, the “use of a ‘hardware
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`buffer’ relates to one of the key claimed advances of the invention—the elimination
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`of ‘extra memory copy operations’” in system memory. Opinion at 811. Under
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`Intel’s construction, extra memory copy operations in system memory are not
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`eliminated, and the advantages of the ’949 invention are not realized. Intel’s
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`construction is wrong for these reasons and those detailed below.
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`Under Qualcomm’s correct construction of “hardware buffer,” claims 1-9
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`and 12 are not unpatentable over Bauer, Svensson, and Kim. Intel argues that the
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`intermediate storage area (“ISA”) of Bauer and Svensson discloses the claimed
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`“hardware buffer” (Intel Br. at 13), but the Board already found that the ISA in those
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`references is a temporary buffer—i.e., not permanent. The Federal Circuit did not
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`disturb this finding, and it should stand on remand. The ISA of Bauer and Svensson
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`also fails to satisfy Qualcomm’s construction because it is formed in general-purpose
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`system memory and therefore is not a dedicated buffer distinct from system memory.
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`As to claims 16 and 17, the Federal Circuit held that the Board must make its
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`own determination about whether there is sufficient structure in the specification to
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`support the means-plus-function (MPF) limitations of these claims. Opinion at 813-
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`14. Qualcomm accordingly rests on the prior briefing for this issue. If the Board
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`determines that the specification lacks sufficient structure, then the Board cannot
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`resolve the prior-art challenges to these claims, as detailed below.
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`II. CLAIM CONSTRUCTION—“HARDWARE BUFFER”
`The term “hardware buffer” should be construed as “a permanent, dedicated
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`buffer that is distinct from system memory.” Ex. 2015 at ¶¶16-61.
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`A. The ’949 Patent Describes Conventional Loading Processes That
`Use Temporary Buffers In System Memory
`The Background section of the ’949 patent describes prior-art systems in
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`which a software image is loaded onto a target, secondary processor from a primary
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`processor using “an intermediate step where the binary multi-segmented image is
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`transferred into the system memory and then later transferred into target locations
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`by the boot loader.” Ex. 1001 at 2:17-22; Ex. 2015 at ¶¶23-24. This loading is
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`performed by “allocat[ing] a temporary buffer into which each packet is received.”
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`Ex. 1001 at 2:25-26. The temporary buffer (also referred to as an “intermediate
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`buffer,” see id. at 2:35-54) is “some place in system memory, such as in internal
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`random-access-memory (RAM) or double data rate (DDR) memory, for example.”
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`Id. at 2:31-34.
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`The ’949 patent explains that the prior-art use of system memory for buffering
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`is inefficient because it requires “extra memory copy operations.” Ex. 1001 at 7:16-
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`30. Specifically, the approaches described in the Background section of the ’949
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`patent involve the intermediate step of copying image data from the temporary
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`buffer—which is formed in one portion of system memory, see id. at 2:31-34—to
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`its final location in system memory. Id. at 2:17-22, 2:29-31, 2:35-41, 7:20-26;
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`Ex. 2015 at ¶24. The ’949 patent states that the extra memory copy operations in
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`system memory result in reduced efficiency and increased time required to boot a
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`secondary processor in a multi-processor system. Ex. 1001 at 7:27-30.
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`As Dr. Rinard explains (Ex. 2015 at ¶¶25-26), the prior-art systems’ use of
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`system memory is inefficient also because it is general-purpose memory that is not
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`specifically configured for the task of buffering data in a multi-processor system.
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`System memory is general-purpose working memory of a processor, usable for a
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`variety of different tasks. Id. at ¶25. Under software control, the processor allocates
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`different regions of system memory for the various data and code storage tasks
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`required to execute the software. Id. The temporary buffer described in the
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`Background section of the ’949 patent is an example of a buffer that is allocated by
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`software in system memory, see Ex. 1001 at 2:23-28, and this buffer is “temporary”
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`because it only exists (conceptually) after it is allocated by the software. Ex. 2015
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`at ¶25.
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`Different software running on the processor can apply different configurations
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`to the system memory, and the system memory is therefore capable of supporting a
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`wide variety of different access patterns. Id. at ¶26. The ability to support different
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`access patterns provides flexibility, but the flexibility comes at the cost of speed and
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`efficiency. Id.; see also id. at ¶¶6-15. Because system memory—including the
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`system memory allocated for use as temporary buffers in the prior-art approaches,
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`see Ex. 1001 at 2:23-34—is able to support a wide range of software memory access
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`patterns, using system memory for buffering is less efficient than using dedicated
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`hardware components for this purpose. Ex. 2015 at ¶26. The hardware buffer of
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`the ’949 patent is an example of a dedicated hardware component, distinct from
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`system memory, that provides “improv[ed] performance” over the conventional
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`approaches, as explained below. Id.; Ex. 1001 at 7:27-30.
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`B.
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`The ’949 Invention’s Use Of A Dedicated, Permanent Hardware
`Buffer Enables More Efficient Loading
`The invention of the ’949 patent uses a hardware buffer to provide “a direct
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`scatter load technique” that eliminates “the intermediate step of buffering required
`
`in traditional loading processes,” to achieve increased efficiency. Ex. 1001 at 4:43-
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`47, 7:20-26; Ex. 2015 at ¶¶27-34. The ’949 patent refers to the direct scatter load
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`technique as a “Zero Copy Transport flow” (Ex. 1001 at 7:16), an example of which
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`is illustrated in Figure 3. In Figure 3, a scatter load controller 304 transfers image
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`segments “from the hardware buffer of the hardware transport mechanism 309
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`directly into their respective target locations in the … system memory 305.” Id.
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`at 9:21-27; see also Ex. 2015 at ¶¶27-28.
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`In transferring data directly from the hardware buffer to the target locations in
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`system memory, the invention of the ’949 patent eliminates the system memory to
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`system memory copying operations of the prior art. Ex. 2015 at ¶29. Specifically,
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`the ’949 patent states that in performing the direct transfer using the hardware buffer,
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`“no extra memory copy operations occur in the secondary processor.” Ex. 1001
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`at 9:42-43. The patent contrasts the invention with the “conventional techniques
`
`employing a temporary buffer,” stating that the conventional techniques “are
`
`bypassed in favor of a more efficient direct loading process.” Id. at 9:43-46. The
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`direct loading process “does not require the intermediate buffer operations
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`traditionally required for loading a software image from a primary processor to a
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`secondary processor.” Id. at 9:46-50.
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`In avoiding the extra memory copy operations of the prior art, the invention
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`provides a more efficient loading process. Ex. 2015 at ¶30. The ’949 patent states,
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`for instance, that the direct scatter load technique of the invention “reduce[s] the
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`time it takes to boot secondary processors in a multi-processor system where
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`secondary processor images are transferred from the primary processor. This
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`reduction is achieved by avoiding extra memory copy operations ….” Ex. 1001
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`at 11:17-24; see also id. at 2:23-55, 4:46-47, 5:31-35, 7:16-30, 9:9-11.
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`The hardware buffer of the ’949 patent also enables a more efficient loading
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`process because it is permanent and dedicated to the single task of loading data
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`segments directly to system memory. Ex. 2015 at ¶¶32-33. As explained above, the
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`conventional techniques distinguished in the ’949 patent use a temporary buffer that
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`is allocated by software in general-purpose system memory. The prior-art buffer is
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`temporary—i.e., not permanent—because it exists only after software allocates it,
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`and its general-purpose nature makes it flexible but relatively inefficient. Id. at ¶32.
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`By contrast, in the invention of the ’949 patent, the hardware buffer is permanently
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`assigned within the structure of the hardware to perform the single, specialized task
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`for which it was designed, i.e., the direct transfer of data from a primary processor
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`to the system memory of a secondary processor. Id.; see also id. at ¶¶6-15. The
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`permanent and dedicated nature of the hardware buffer—along with the elimination
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`of “extra memory copy operations”—enables the efficient direct scatter loading
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`technique described and claimed in the ’949 patent. Id. at ¶¶32-33.
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`For these reasons, the term “hardware buffer” should be construed as a
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`permanent, dedicated buffer that is distinct from system memory. Id. at ¶34.
`
`C.
`Inventor Testimony Supports Qualcomm’s Construction
`Steve Haehnichen, a named inventor on the ’949 patent, provided testimony
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`relevant to the meaning of the term “hardware buffer.” See generally Exs. 2003-
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`2004; see also Ex. 2015 at ¶¶35-40 (Dr. Rinard analyzing Mr. Haehnichen’s
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`testimony). Qualcomm agrees with the Federal Circuit that this testimony “would
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`benefit from attention on remand,” Opinion at 812, because it provides evidence of
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`what the inventors actually invented and intended to envelop with the claim.
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`Mr. Haehnichen testified that Qualcomm was seeking to design a modem
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`processor with a boot time of less than one second. Ex. 2003 at 213:22-214:2 (“Boot
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`time should be 1 second”), 214:1-12. To meet the one-second boot time requirement,
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`Qualcomm developed a new design (referred to as “Sahara”) that became the basis
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`for the ’949 patent. Id. at 215:20-216:15. Mr. Haehnichen testified that “[t]he single
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`biggest thing we did to speed it up was to avoid copying things around memory.”
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`Id. at 216:16-21; see also id. at 216:22-217:2. Mr. Haehnichen also contrasted the
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`Sahara design with Qualcomm’s previous “Gobi” design: “So if you look at Gobi, it
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`reads things into memory, figures out what they are, where they need to go, and it
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`copies them there; whereas in Sahara, we would receive the data directly from USB
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`and the only place it would go is right where it needs to be. So we compared to like
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`a nonstop flight. Instead of a flight with a stop in the middle and a long layover, you
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`just put it right where it needs to be at the end.” Ex. 2004 at 221:25-222:10.
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`Mr. Haehnichen’s testimony reflects the fact that the permanent hardware
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`buffer of the ’949 patent enables a more efficient, direct transfer that outperforms
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`less efficient techniques that involve “copying things around memory.” Ex. 2003
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`at 216:16-21; Ex. 2015 at ¶¶39-40. Further, the permanent, dedicated nature of the
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`hardware buffer enables it to be integrated into an efficient direct data transfer
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`mechanism, such as the USB controller described in the ’949 patent. Ex. 2003
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`at 216:22-217:2 (Mr. Haehnichen testifying that “USB speed is fast”).
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`D.
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`Intel’s Arguments Contrary To Qualcomm’s Construction Are
`Wrong
`Intel’s brief includes several arguments relevant to Qualcomm’s construction.
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`These arguments are wrong for the reasons detailed below. Ex. 2015 at ¶¶41-56.
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`Intel asserts that nothing in the ’949 patent precludes the hardware buffer from
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`being located in system memory (Intel Br. at 6), but the Federal Circuit has already
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`determined otherwise. The court recognized that “claim 1 requires both a ‘system
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`memory’ and a ‘hardware buffer,’” and therefore, “there must be some distinction
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`between those two concepts.” Opinion at 810; see also id. at 811. Moreover, Intel’s
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`argument is contrary to the “actual invention described in the specification” (id.
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`at 804), which eliminates copy operations in system memory to provide increased
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`efficiency and reduced boot times. See Section II.B above. If the hardware buffer
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`could be located in system memory (as Intel argues), then these advantages are not
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`realized, and the claims would read on the prior-art techniques distinguished in
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`the ’949 patent. Ex. 2015 at ¶¶42-43. That cannot be correct.
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`Intel makes a claim-differentiation argument, asserting that dependent claim 2
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`“confirms that neither claim 1 nor its ‘hardware buffer’ limitation precludes the
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`possibility of copying data between system memory locations.” Intel Br. at 7. For
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`several reasons, this is incorrect. As an initial matter, claim differentiation is a guide,
`
`not a rigid rule, Laitram Corp. v. Rexnord, Inc., 939 F.2d 1533, 1538 (Fed. Cir. 1991),
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`and claim differentiation cannot broaden claims beyond their correct scope. Fantasy
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`Sports Props., Inc. v. Sportsline.com, Inc., 287 F.3d 1108, 1115-16 (Fed. Cir. 2002).
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`Intel’s purported claim-differentiation argument fails because it would improperly
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`broaden claims 1 and 3-9 beyond their correct scope. Ex. 2015 at ¶44. As detailed
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`above and recognized by the Federal Circuit, the “use of a ‘hardware buffer’ relates
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`to one of the key claimed advances of the invention—the elimination of ‘extra
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`memory copy operations’” in system memory. Opinion at 811. Intel’s claim-
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`differentiation position—which, if adopted, would yield a claim that permits
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`“copying data between system memory locations,” see Intel Br. at 7—would
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`improperly broaden these claims beyond the scope of the invention described in the
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`specification. Ex. 2015 at ¶44.
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`Further, Intel’s purported claim-differentiation argument fails because claim
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`differentiation exists under Qualcomm’s construction of “hardware buffer.” Id.
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`at ¶45. With Qualcomm’s construction of “hardware buffer” inserted, claim 1
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`requires a scatter loader controller configured to “scatter load each received data
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`segment based at least in part on the loaded image header, directly from the
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`[permanent, dedicated buffer that is distinct from system memory] to the system
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`memory.” Claim 2 further limits the scatter loader controller element by adding
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`limitations on how it “directly” loads into system memory—specifically, expressly
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`excluding “copying data between system memory locations on the secondary
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`processor.” Thus, claims 1 and 2 have different respective scopes, and there is no
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`claim-differentiation issue.
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`Intel disagrees that the hardware buffer must be permanent, arguing that
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`the ’949 patent does not “distinguish … the use of temporary buffers per se.” Intel
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`Br. at 9. Rather, according to Intel, the specification “distinguishes systems in which
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`the entire executable image is copied into a temporary buffer.” Id. (boldface and
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`italics by Intel). That is incorrect. The ’949 patent also distinguishes prior-art
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`approaches in which a temporary buffer receives “part of the image data.” Ex. 1001
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`at 2:23-55; Ex. 2015 at ¶¶46-47. Thus, the techniques distinguished by the ’949
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`patent are not limited to those that involve copying an entire executable image into
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`a temporary buffer.
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`Intel also argues that the specification distinguishes “between the buffer
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`receiving a header separately from data segments (as claimed) and receiving a
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`packet that includes both a header and data segments, and not that the buffer is
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`temporary.” Intel. Br. at 10 (boldface and italics by Intel). This, too, is wrong.
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`Ex. 2015 at ¶¶48-53. First, the ’949 patent states, without qualification, that “the
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`direct scatter load technique avoids use of a temporary buffer.” Ex. 1001 at 4:46-47.
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`Second, the patent describes a modem processor 110 that “stores the modem
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`executable image 132 directly … to the final destination without copying the data
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`into a temporary buffer in the modem processor RAM 112.” Id. at 5:31-35. These
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`statements distinguish the use of a temporary buffer in system memory and do not
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`limit the distinction only to temporary buffers that receive packets with both a header
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`and data segments. Ex. 2015 at ¶53.
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`Intel’s attempts to avoid these two statements fail. Id. at ¶¶54-56. Intel argues
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`that the first statement (at Ex. 1001 at 4:46-47) must be “read in light of the
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`surrounding context,” and that the surrounding context shows that the ’949 patent
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`“distinguishes receiving a packet that includes both a header and data segments, not
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`the use of temporary buffers for all purposes.” Intel Br. at 11. But the statement at
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`column 4, lines 46-47 is categorical and does not link or limit avoidance of the
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`temporary buffer to systems that use packets containing headers and data. Ex. 2015
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`at ¶54. The statement is also consistent with other portions of the ’949 patent (see,
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`e.g., Ex. 1001 at 5:31-35, 7:16-30, 11:11-24) describing the elimination of temporary
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`buffers in system memory without reference to the packet/header distinction that
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`Intel tries to make. Further, the relevant “context” for the statement at column 4,
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`lines 46-47 is the patent’s discussion of the “Zero Copy Transport flow” in column 7,
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`which describes “alleviat[ing] the intermediate step of buffering required in
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`traditional loading processes” without mentioning packets or headers. Ex. 1001
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`at 7:16-30; Ex. 2015 at ¶54.
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`Regarding the second statement (at Ex. 1001 at 5:31-35), Intel argues that “the
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`specification describes transferring the executable image into the final location in
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`the system memory (i.e., RAM 112) without copying the data into a temporary
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`buffer in the same system memory (i.e., RAM 112).” Intel Br. at 11 (boldface and
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`italics by Intel). Thus, Intel argues that the hardware buffer cannot be located in the
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`RAM 112 but could be located in some other system memory of the modem
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`processor 110. Id. But as Dr. Rinard explains (Ex. 2015 at ¶¶55-56), the patent
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`precludes the hardware buffer from being in the only system memory of the
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`processor 110 (i.e., RAM 112), and it would be illogical for the patent to address
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`(nonexistent) system memories separate from the RAM 112 that are not described
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`in the patent.
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`E.
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`Intel’s Proposed Construction Is Overly Broad And Does Not
`Capture The Scope Of The Actual Invention
`Intel argues that the claimed “hardware buffer” is “memory that is physically
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`separate from the memory into which the software image is loaded for execution.”
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`Intel Br. at 5. Intel argues that its construction “does not foreclose the possibility of
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`implementing a [hardware] buffer in some other system memory.” Id. at 6.
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`Intel’s construction is wrong for several reasons. Ex. 2015 at ¶¶57-61. First,
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`Intel’s construction encompasses a buffer formed in system memory, which is the
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`exact configuration described in the Background section and distinguished
`
`throughout the ’949 patent. Id. at ¶59; Sections II.A-B above.
`
`Second, Intel’s construction is contrary to the Federal Circuit’s finding that
`
`the hardware buffer is conceptually distinct from system memory. Opinion at 810.
`
`The court did not state that the hardware buffer and system memory must merely be
`
`physically distinct; rather, the court stated that “there must be some distinction
`
`between those two concepts.” Id. Locating the hardware buffer in system memory
`
`(as is permissible under Intel’s construction) would eliminate the conceptual
`
`distinction between the two components and fail to achieve the “Zero Copy
`
`Transport Flow” that the inventors intended to envelop. Ex. 2015 at ¶60.
`
`Third, Intel’s construction is contrary to positions it took previously. Intel’s
`
`declarant Dr. Lin has acknowledged that “[t]he ’949 patent makes a distinction
`
`between prior art systems that used a ‘temporary buffer’ that was part of the system
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`
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`IPR2018-01334
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`memory … and the alleged invention that uses a ‘hardware buffer’ separate from the
`
`system memory.” Ex. 1002 at ¶111. Intel now abandons that position, arguing that
`
`the hardware buffer can be in system memory. Intel Br. at 6. This shows that Intel’s
`
`shifting positions are nothing more than litigation-induced maneuvering.
`
`Finally, Intel wrongly argues that the prosecution history supports its
`
`proposed construction. Intel argues that “the Examiner expressly identified
`
`Svensson’s ISA as a ‘hardware buffer,’” and Applicant did not “argu[e] that
`
`Svensson lacked a ‘hardware buffer.’” Intel Br. at 11-12. But unilateral statements
`
`by an Examiner cannot redefine claim terms, Salazar v. Procter & Gamble Co., 414
`
`F.3d 1342, 1344-48 (Fed. Cir. 2005), and “[a]n applicant’s silence in response to an
`
`examiner’s characterization of a claim does not reflect the applicant’s clear and
`
`unmistakable acquiescence to that characterization if the claim is eventually allowed
`
`on grounds unrelated to the examiner’s unrebutted characterization.” 3M Innovative
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`Props. Co. v. Avery Dennison Corp., 350 F.3d 1365, 1373-74 (Fed. Cir. 2003).
`
`The ’949 claims were allowed for reasons unrelated to the Examiner’s mistaken
`
`belief that Svensson’s ISA is a hardware buffer, and Applicant was therefore not
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`acquiescing to the Examiner’s position. See Paper 16 (“PO Resp.”) at 8.
`
`III. CLAIMS 1-9 AND 12 ARE NOT UNPATENTABLE
`Under Qualcomm’s correct construction of “hardware buffer,” claims 1-9
`
`and 12 are not unpatentable over Bauer, Svensson, and Kim. Intel argues that the
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`-15-
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`
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`IPR2018-01334
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`ISA of Bauer and Svensson discloses the claimed “hardware buffer” (Intel Br. at 13),
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`but this is wrong for the reasons detailed below. Ex. 2015 at ¶¶62-70.
`
`A. The ISA Is Not A Permanent Buffer
`Qualcomm previously showed that Bauer/Svensson’s ISA is a temporary
`
`buffer reserved in system memory at run time and used to hold data that is
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`subsequently transferred to a final destination in system memory. PO Resp. at 41,
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`42, 55; Paper 25 (“Sur-Reply”) at 2, 17-26; Ex. 2007 at ¶¶112-113, 135-144. The
`
`Board agreed with Qualcomm: “Patent Owner argues that the intermediate storage
`
`area of Bauer and Svensson is a temporary buffer …. We agree with Patent Owner.
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`Svensson discloses that the intermediate storage area is reserved at runtime of the
`
`program loader .... Thus, we find that the intermediate storage area of Bauer and
`
`Svensson is a temporary buffer.” Paper 30 (“FWD”) at 55-56.
`
`Intel did not challenge this factual finding on appeal, and the Federal Circuit’s
`
`opinion does not disturb it. Therefore, the Board’s finding that Bauer/Svensson’s
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`ISA is a temporary buffer should stand on remand. Because the Board has already
`
`found that the ISA of Bauer/Svensson is temporary—i.e., not permanent—the ISA
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`is not a “hardware buffer” as properly construed by Qualcomm.
`
`Intel tries to re-litigate the issue of whether the ISA of Bauer/Svensson is
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`temporary, arguing that “even under a construction that excludes temporary buffers,
`
`the ISA would satisfy the ‘hardware buffer’ limitation[] since the ISA is never
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`IPR2018-01334
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`deallocated and instead functions solely as a permanent buffer.” Intel Br. at 17.
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`Intel’s deallocation argument is a red herring. Ex. 2015 at ¶64. As explained above,
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`the temporary buffer described in the Background section of the ’949 patent—like
`
`the ISA of Bauer/Svensson—is temporary because it is generated (i.e., reserved or
`
`allocated) by software at run time and does not exist absent the software. Id.
`
`In Bauer/Svensson, specifically, the ISA is reserved in DSP SARAM &
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`DARAM 108/208 by software running on the client processor 104/204. Ex. 1010
`
`at 5:3-36. Absent the software allocation, the ISA does not exist in the DSP SARAM
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`& DARAM 108/208, and that is why it is temporary: It exists only after it is
`
`allocated by software at run time, and therefore, it is not a permanent, fixed buffer.
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`Ex. 2015 at ¶¶65-67. The fact that Bauer/Svensson does not describe deallocation
`
`of the ISA is beside the point, and the ISA is indistinguishable from the temporary
`
`buffers described in the Background section of the ’949 patent. See, e.g., PO Resp.
`
`at 41, 42, 55; Sur-Reply at 2, 17-26; Ex. 2007 at ¶¶112-113, 135-144.
`
`B.
`
`The ISA Is Not A Dedicated Buffer Distinct From System
`Memory
`The ISA of Svensson/Bauer also fails to disclose the claimed “hardware buffer”
`
`because it is not a dedicated buffer distinct from system memory. Ex. 2015 at ¶¶68-
`
`70. Qualcomm previously showed that in Bauer/Svensson, system memory consists
`
`of the DSP SARAM & DARAM 108/208—including the portion thereof allocated
`
`as the ISA—and the DSP XRAM 110/210:
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`-17-
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`
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`IPR2018-01334
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`PO Resp. at 50-58; Sur-Reply at 17-26; Ex. 2007 at ¶¶135-144. The Board declined
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`to construe “system memory” in the Final Written Decision, but Qualcomm showed
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`that the ISA is located in system memory under both parties’ constructions of the
`
`term. See PO Resp. at 50-58; Sur-Reply at 17-26; Ex. 2007 at ¶¶135-144. Further,
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`Intel’s declarant Dr. Lin conceded that the SARAM & DARAM 108/208 of
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`Bauer/Svensson “could be used to load and execute programs,” such that it satisfies
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`Intel’s construction of system memory (i.e., “memory where an executable software
`
`image can be loaded and executed”). Ex. 2008 at 53:18-24.
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`Accordingly, the ISA of Bauer/Svensson is not a “hardware buffer” because
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`it is allocated in system memory (i.e., the SARAM & DARAM 108/208) and
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`th
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