UNITED STATES PATENT AND TRADEMARK OFFICE
`______________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`______________________
`
`Intel Corporation
`Petitioner
`
`v.
`
`Qualcomm Incorporated
`Patent Owner
`______________________
`
`Case IPR2018-013341
`Patent 8,838,949
`______________________
`
`DECLARATION OF DR. MARTIN RINARD
`
`I, Martin Rinard, do hereby declare:
`
`1.
`
`I am making this declaration at the request of Qualcomm Incorporated
`
`(“Qualcomm” or “Patent Owner”) in the matter of the Inter Partes Review of U.S.
`
`Patent No. 8,838,949 (“the ’949 patent”).
`
`1 IPR2018-01335 and IPR2018-01336 have been consolidated with the instant
`proceeding.
`
`QUALCOMM EXHIBIT 2007
`Intel v. Qualcomm
`IPR2018-01334
`
`Page 1
`
`
`______________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`______________________
`
`Intel Corporation
`Petitioner
`
`v.
`
`Qualcomm Incorporated
`Patent Owner
`______________________
`
`Case IPR2018-013341
`Patent 8,838,949
`______________________
`
`DECLARATION OF DR. MARTIN RINARD
`
`I, Martin Rinard, do hereby declare:
`
`1.
`
`I am making this declaration at the request of Qualcomm Incorporated
`
`(“Qualcomm” or “Patent Owner”) in the matter of the Inter Partes Review of U.S.
`
`Patent No. 8,838,949 (“the ’949 patent”).
`
`1 IPR2018-01335 and IPR2018-01336 have been consolidated with the instant
`proceeding.
`
`QUALCOMM EXHIBIT 2007
`Intel v. Qualcomm
`IPR2018-01334
`
`Page 1
`
`
`
`2.
`
`I am being compensated for my work in this matter at my standard
`
`hourly rate of $850 for consulting services. My compensation in no way depends
`
`on the outcome of this proceeding.
`
`3.
`
`In preparing this Declaration, I considered the following materials:
`
`a. The ’949 patent (Ex. 10012) and its file history;
`b. Petitions for Inter Partes Review of U.S. Patent No. 8,838,949
`filed in IPR2018-01334, -01335, -01336 (Paper 3 in each
`proceeding);
`c. The Declarations of Dr. Bill Lin (Exs. 1002, 1020, 1021);
`d. U.S. Patent Pub. No. 2006/0288019 to Bauer (Ex. 1009)
`(“Bauer”);
`e. U.S. Patent No. 7,356,680 to Svensson (Ex. 1010) (“Svensson”);
`f. Translation of Korean Patent Application Pub. No. 2002
`0036354 A to Kim (Ex. 1012) (“Kim”);
`g. U.S. Patent Pub. No. 2007/0140199 to Zhao (Ex. 1013)
`(“Zhao”);
`h. U.S. Patent No. 7,203,829 to Lim (Ex. 1014) (“Lim”);
`i. The Board’s Institution Decisions in IPR2018-01334, -01335,
`and -01336 (Paper 10 in each proceeding);
`j. Lin Deposition Transcript (Ex. 2001);
`k. U.S. Provisional Patent Application No. 61/324,122 (Ex. 2002);
`l. Qualcomm v. Apple, Case No. 3:17-CV-1375-DMS-MDD,
`S.D. Cal., Transcript of Jury Trial:
`
`2 All citations to Petitioner’s exhibits herein refer to the exhibits listed in
`Petitioner’s Consolidated Exhibit List (Paper 14), as filed in IPR2018-01334.
`
`Page 2
`
`
`
`i. Day 2, Volumes 2-A and 2-B (Exs. 2003 and 2004,
`respectively),
`ii. Day 6, Volume 6-B (Ex. 2005),
`iii. Day 7, Volume 7-A (Ex. 2006); and
`m. Any other materials referenced herein.
`
`I.
`
`Professional Background
`4.
`Full descriptions of my educational background, professional
`
`achievements, qualifications, and publications are set forth more fully in my
`
`curriculum vitae, which is attached to this report as Appendix A. Here, I provide a
`
`summary of my background and qualifications.
`
`5.
`
`I am currently a tenured Professor in the Department of Electrical
`
`Engineering and Computer Science and a member of the Computer Science and
`
`Artificial Intelligence Laboratory at the Massachusetts Institute of Technology
`
`(MIT). I hold an Sc.B. in Computer Science from Brown University and a Ph.D.
`
`in Computer Science from Stanford University. Before coming to MIT, I was an
`
`Assistant Professor at the University of California, Santa Barbara (UCSB). As a
`
`faculty member at MIT, I teach courses and perform research in a range of fields
`
`related to computer science. I have published over 175 papers in refereed
`
`workshops, conferences, and journals in the areas of programming languages,
`
`program analysis, distributed computing, parallel computing, compilers, computer
`
`security, mobile computing, and other areas of computer science. During my time
`
`Page 3
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`
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`at MIT and UCSB, I have taught both undergraduate and graduate computer
`
`science courses on a variety of topics including computer systems, data structures
`
`and algorithms, compilers, operating systems, software engineering, program
`
`analysis, and programming languages.
`
`6.
`
`I have received, among other awards, an Alfred P. Sloan Research
`
`Fellowship and a National Science Foundation Early Career Development Award.
`
`I have received multiple Best or Distinguished paper awards at top publication
`
`venues. In 2009 I was recognized as an ACM Fellow by the Association for
`
`Computing Machinery (ACM). According to the ACM, “The ACM Fellows serve
`
`as distinguished colleagues to whom the ACM and its members look for guidance
`
`and leadership as the world of information technology evolves.”
`
`7. My research has been supported by many entities, including the
`
`United States National Science Foundation, the United States Department of
`
`Defense, including the Defense Advanced Research Projects Agency, the
`
`government of Singapore, the NASA Jet Propulsion Laboratory (JPL), as well as
`
`private entities such as SUN Microsystems, Microsoft, Samsung, and IBM. I have
`
`been a Principal Investigator or co-Principal Investigator on research grants and
`
`contracts totaling over $50 million in research funding from a variety of
`
`government and private sources.
`
`Page 4
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`
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`8.
`
`Before starting graduate school, I worked as a software engineer at
`
`two startup companies, Ikan Systems and Polygen Corporation. At Ikan Systems
`
`my responsibilities involved user interface design and implementation as well as
`
`programming language design and implementation. At Polygen Corporation my
`
`responsibilities involved a variety of tasks, including developing software to work
`
`with computerized representations of molecules and user interface implementation.
`
`9. My Ph.D. thesis at Stanford was on the design, implementation, and
`
`evaluation of the Jade programming language. Jade programs executed, without
`
`modification, on a range of parallel computing platforms, including shared-
`
`memory multiprocessors and groups of computers that communicate using the
`
`Internet or specialized high-performance computing networks. Jade provided a
`
`unified model of data access in which Jade tasks specified the data objects that
`
`they accessed, and the Jade implementation was responsible for locating these
`
`objects at execution time. When a Jade task executed on a given processor, it may
`
`have needed to access objects stored both locally in the memory of the processor
`
`and remotely in the memories of other processors or computers participating in the
`
`computation. It was the responsibility of the Jade implementation to locate these
`
`objects in both local and remote memories and generate the communication
`
`required to implement the abstraction of a single unified object store. The Jade
`
`implementation therefore dealt extensively with communication protocols and
`
`Page 5
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`techniques across a wide range of parallel computing platforms. The Jade research
`
`also dealt extensively with techniques that optimized the efficiency of data
`
`communication on multiple different parallel computing platforms, including
`
`techniques designed to optimize the transfer of large amounts of data between
`
`processors operating together in a parallel computing platform.
`
`10. At UCSB and MIT, I have taught both undergraduate and graduate
`
`courses in a variety of areas including operating systems, programming languages,
`
`computer systems, compilers, and software engineering. Topics covered in these
`
`courses included various aspects of parallel and distributed computing systems,
`
`including communication and coordination issues that arise in this context as well
`
`as data communication protocols in parallel and distributed computing systems. I
`
`have supervised both undergraduate and graduate research projects that focus on
`
`efficient parallel computation and communication techniques in parallel and
`
`distributed computing systems, including the use of DMA for efficient
`
`communication of large shared objects between processors in parallel computing
`
`platforms.
`
`11. At MIT I have supervised multiple research projects involving
`
`software for mobile computing devices such as smartphones. These projects
`
`involved, among other considerations, analyzing communications between
`
`components of mobile computing platforms such as processors, cameras,
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`Page 6
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`
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`microphones, wireless network access devices, and other devices as information
`
`sources and sinks. They also involved analyzing communication and information
`
`flow involving devices, processors, and nonvolatile storage mechanisms such as
`
`files and databases stored in the mobile device and accessed via processors in the
`
`device.
`
`12. These projects included the static analysis of communication,
`
`information flow, and information storage in smartphones (i.e., analyzing the
`
`smartphone software before it runs to determine possible communication,
`
`information flow, and information storage patterns). They also included the
`
`dynamic analysis of communication, information flow, and information storage in
`
`smartphones (i.e., instrumenting the software and collecting information about the
`
`software as it runs on the smartphone).
`
`13. These projects therefore required understanding communication
`
`protocols, mechanisms, and techniques in mobile computing and smartphone
`
`devices, including communication between components of the smartphone
`
`executing in parallel. They also involved understanding how information was
`
`stored in databases and files on smartphones and mobile devices, including how
`
`information was communicated between devices, files, and processors on
`
`smartphones and mobile devices.
`
`Page 7
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`
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`14. Much of this research was funded by the United States Department of
`
`Defense. The project “ClearScope: Transparent multi-level inter-process and intra-
`
`process information scoping,” for example, developed a new system for efficiently
`
`tracking the flow of information through smartphone components to obtain
`
`information provenance graphs that capture how information is acquired at devices
`
`such as the camera, microphone, and wireless network interface (as implemented
`
`by the baseband processor), flows through software components and nonvolatile
`
`storage components such as files and databases, then exits the smartphone at
`
`devices such as the wireless network interface (again as implemented by the
`
`baseband processor).
`
`15. The project “Provably Safe Android Apps,” for example, developed a
`
`system that analyzed the smartphone software before it ran with the goal of finding
`
`communication and information flow patterns in smartphone devices that did not
`
`conform to specified security policies. This project involved analyzing how the
`
`smartphone software acquired and communicated data between hardware devices
`
`and processors, including the use of nonvolatile storage. The extracted information
`
`flow data was then used, for example, to determine if the communication patterns
`
`and protocols implemented by the smartphone software conformed to desired
`
`restrictions on the smartphone information flow.
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`Page 8
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`
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`16. Together, these two projects attracted over $10 million in funding
`
`from the United States Department of Defense.
`
`17.
`
`I have also served as an expert in multiple trials involving smartphone
`
`or communications technology. For example, I testified at trial in Apple v.
`
`Samsung, case no. 12-cv-630-LHK (N.D. Cal.), Intellectual Ventures I LLC v.
`
`Motorola Mobility LLC, case no.11-cv-00908 (D. Del.), Rovi v. Comcast, ITC
`
`Investigation No. 337-TA-1001, and Qualcomm v. Apple, case no. 3:17-CV-1375-
`
`DMS-MDD (S.D. Cal.).
`
`II. Relevant Legal Standards
`18.
`I have been asked to provide my opinion as to whether claims 1-23 of
`
`the ’949 patent would have been obvious to a person of ordinary skill in the art
`
`(“POSA”) at the time of the invention, in view of the alleged prior art.
`
`19.
`
`I am a computer scientist by training and profession. The opinions I
`
`am expressing in this Declaration involve the application of my computer science
`
`knowledge and experience to the evaluation of certain alleged prior art with respect
`
`to the ’949 patent. Aside from my experience in litigation support, my knowledge
`
`of patent law is no different than that of any lay person. Therefore, I have requested
`
`the attorneys from Jones Day, who represent Qualcomm, to provide me with
`
`guidance as to the applicable patent law in this matter. The paragraphs below
`
`Page 9
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`
`
`express my understanding of how I must apply current principles related to
`
`patentability.
`
`20.
`
`It is my understanding that in determining whether a patent claim is
`
`obvious in view of the alleged prior art, the Patent Office must construe the claim
`
`by giving the claim its broadest reasonable interpretation consistent with the
`
`specification as it would have been understood by one of ordinary skill in the art.
`
`For the purposes of this review, I have construed each claim term in accordance with
`
`its plain and ordinary meaning under the required broadest reasonable interpretation.
`
`21.
`
`It
`
`is my understanding
`
`that a claim
`
`is unpatentable under
`
`35 U.S.C. § 103 if the claimed subject matter as a whole would have been obvious
`
`to a POSA at the time of the invention. I also understand that an obviousness
`
`analysis takes into account the scope and content of the prior art, the differences
`
`between the claimed subject matter and the prior art, and the level of ordinary skill
`
`in the art at the time of the invention.
`
`22.
`
`In determining the scope and content of the prior art, it is my
`
`understanding that a reference is considered appropriate prior art if it falls within the
`
`field of the inventor’s endeavor. In addition, a reference is prior art if it is reasonably
`
`pertinent to the particular problem with which the inventor was involved. A
`
`reference is reasonably pertinent if it logically would have commended itself to an
`
`inventor’s attention in considering his problem. If a reference relates to the same
`
`Page 10
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`
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`problem as the claimed invention, that supports use of the reference as prior art in
`
`an obviousness analysis.
`
`23. To assess the differences between prior art and the claimed subject
`
`matter, it is my understanding that 35 U.S.C. § 103 requires the claimed invention
`
`be considered as a whole. This “as a whole” assessment requires showing that one
`
`of ordinary skill in the art at the time of invention, confronted by the same problems
`
`as the inventor and with no knowledge of the claimed invention, would have selected
`
`the elements from the prior art and combined them in the claimed manner.
`
`24.
`
`It is my further understanding that the Supreme Court has recognized
`
`several rationales for combining references or modifying a reference to show
`
`obviousness of claimed subject matter. Some of these rationales include: combining
`
`prior art elements according to known methods to yield predictable results; simple
`
`substitution of one known element for another to obtain predictable results; a
`
`predictable use of prior art elements according to their established functions;
`
`applying a known technique to a known device (method or product) ready for
`
`improvement to yield predictable results; choosing from a finite number of
`
`identified, predictable solutions, with a reasonable expectation of success; and some
`
`teaching, suggestion, or motivation in the prior art that would have led one of
`
`ordinary skill to modify the prior art reference or to combine prior art reference
`
`teachings to arrive at the claimed invention.
`
`Page 11
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`
`
`III. THE ’949 PATENT
`A. Technology Background and Overview of the ’949 Patent
`25. U.S. Patent No. 8,838,949 (“the ’949 Patent”), titled “Direct Scatter
`
`Loading of Executable Software Image From a Primary Processor to One or More
`
`Secondary Processor in a Multi-Processor System,” generally relates to multi-
`
`processor systems in which a primary processor is coupled to a non-volatile memory
`
`storing executable software image(s) of one or more secondary processors that are
`
`each coupled to a dedicated volatile memory, where the executable software images
`
`are efficiently communicated from the primary processor to the secondary
`
`processor(s) in a segmented format (e.g., using a direct scatter load process). See
`
`Ex. 1001 at 1:25-33. The ’949 Patent issued on September 16, 2014 from an
`
`application filed on March 21, 2011. The ’949 Patent claims priority to three
`
`provisional applications, the earliest of which was filed on April 14, 2010.
`
`26.
`
`“In a multi-processor system, each processor may require respective
`
`boot code for booting up. As an example, in a smartphone device that includes an
`
`application processor and a modem processor, each of the processors may have
`
`respective boot code for booting up.” Id. at 1:39-43. The ’949 Patent explains that
`
`in some multi-processor systems, one of the processors is responsible for storing the
`
`boot code for one or more other processors in the system and loading the respective
`
`boot code to the other processor(s) at power-up. “In this type of system, the software
`
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`(e.g., boot image) is downloaded from the first processor to the other processor(s)
`
`(e.g., to volatile memory of the other processor(s)), and thereafter the receiving
`
`processor(s) boots with the downloaded image.” Id. at 2:1-14.
`
`27. The Background section of the ’949 Patent describes systems in which
`
`the boot image is loaded onto a target “secondary” processor from a first “primary”
`
`processor using “an intermediate step where the binary multi-segmented image is
`
`transferred into the system memory and then later transferred into target locations
`
`by the boot loader.” See id. at 2:17-22. “One way of performing such loading is to
`
`allocate a temporary buffer into which each packet is received.” Id. at 2:25-26. “The
`
`temporary buffer would be some place in system memory, such as in internal
`
`random-access-memory (RAM) or double data rate (DDR) memory, for example.”
`
`Id. at 2:32-34.
`
`28. Petitioner alleges that the ’949 patent characterizes the prior art over
`
`which it improves as employing a “double copy” approach that requires “copying
`
`the entire software image into one part of the modem processor’s system memory,
`
`and then copying the image into another part of system memory when loading it for
`
`execution.” Paper 33 at 10. This allegation is incorrect. The ’949 patent identifies
`
`prior art approaches that receive packets that contain part of the image data into a
`
`
`3 All citations to papers (e.g., “Paper 3”) herein refer to documents filed in
`IPR2018-01334 unless otherwise noted.
`
`Page 13
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`
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`temporary buffer, then copy the image data into their final destination. Ex. 1001
`
`at 2:23-55.
`
` U.S. Provisional Patent Application No. 61/324,122 (“’122
`
`application”), a provisional application to which the ’949 patent claims priority, also
`
`discusses this “temporary buffer” approach in which the buffer receives “part of the
`
`image data from the primary processor” and then the image data is scattered from
`
`the buffer into the “final destination” as prior art over which the invention improves.
`
`Ex. 2002 at page 17, ¶¶[0005]-[0008]. The ’949 patent incorporates the ’122
`
`application by reference. Ex. 1001 at 1:10-20.
`
`29. As the Background sections of the ’949 patent and ’122 application
`
`discuss, the ’949 patent improves over prior art approaches that receive “part of the
`
`image data from the primary processor” into a “temporary buffer” and then copy the
`
`image data into the “final destination.” The prior art discussed in the ’949 patent
`
`and ’122 application is not limited to so-called “double copy” approaches that
`
`require “copying the entire software image into one part of the modem processor’s
`
`system memory, and then copying the image into another part of system memory
`
`when loading it for execution” (Paper 3 at 10), as Petitioner incorrectly alleges.
`
`30. The ’949 Patent improves upon the technology described in its
`
`Background section by providing “a direct scatter load technique” for loading a
`
`segmented image from a primary processor’s non-volatile memory to a secondary
`
`processor’s volatile memory without using “the intermediate step of buffering
`
`Page 14
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`
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`required in traditional loading processes.” Ex. 1001 at 4:43-47, 7:20-26. The ’949
`
`patent refers to this as a “Zero Copy Transport Flow,” an example of which is
`
`illustrated in Fig. 3, reproduced below.
`
`31.
`
`In Fig. 3, a software image (e.g., boot image) for the secondary
`
`processor 302 is stored to non-volatile memory of the primary processor 301. See
`
`id. at 7:67-8:2. The software image 303 is a multi-segmented image that includes an
`
`
`
`Page 15
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`
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`image header and multiple data segments (shown as data segments 1-5). Id. at 8:2-
`
`5. In a first stage of the loading process, the image header is transferred from the
`
`primary processor 301 to a scatter loader controller 304 of the secondary
`
`processor 302. Id. at 8:9-11, 9:21-23. The image header includes information used
`
`by the secondary processor 302 to identify where each of the image data segments
`
`are to be placed into system memory 305. Id. at 8:18-21, 8:57-63, 9:23-24. “Data
`
`segments are then sent from system memory 307 to the primary hardware transport
`
`mechanism 308. The segments are then sent from the hardware transport mechanism
`
`308 of the primary processor 301 to a hardware transport mechanism 309 of the
`
`secondary processor over an inter-chip communication bus 310 (e.g., a HS-USB
`
`cable.)” Id. at 8:24-30. Using the information from the image header, the scatter
`
`load controller 304 transfers the image segments from the hardware buffer of the
`
`hardware transport mechanism 309 directly into their respective target locations in
`
`the secondary processor’s system memory 305. See id. at 9:21-27.
`
`32. An examination of Fig. 3 further reveals how the different components
`
`interact and the roles they play in the transfer. Data enters the secondary
`
`processor 302 via physical data pipe (i.e., HS-USB Cable) into hardware transport
`
`mechanism (i.e., USB controller) 309, more specifically into the hardware buffer
`
`within the hardware transport mechanism. As part of the transfer, the data moves
`
`through a hardware buffer within the hardware transport mechanism. The controller
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`Page 16
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`
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`304 within the hardware transport mechanism, and not the CPU, moves the data from
`
`the hardware buffer into the system memory 305. The arrow from the hardware
`
`buffer within primary processor 301 to hardware buffer within secondary processor
`
`302 indicates the data movement from the primary to the secondary processor over
`
`the physical data pipe (i.e., HS-USB-Cable). Arrows going from the hardware buffer
`
`to controller 304 within the hardware transport mechanism of secondary processor
`
`302, then from the controller 304 to system memory 305, indicate the data movement
`
`from the hardware buffer into the system memory.
`
`33. Notably, as Fig. 3 illustrates, at no time does the CPU within secondary
`
`processor 302 transfer the software image data into its final destination in system
`
`memory – instead, the controller 304 transfers the software image data into its final
`
`destination. There is a very good reason for this lack of involvement of the CPU –
`
`as the ’949 patent repeatedly explains, one of the benefits of the invention is the
`
`elimination of temporary buffers and extra memory copy operations associated with
`
`prior art techniques. The title of Fig. 3, for example, is “Zero Copy Transport Flow.”
`
`See also, for example, the statement in the ’949 patent that “[t]he modem
`
`processor 110 stores the modem executable image 132 directly into the modem
`
`processor RAM (Random Access Memory) 112 to the final destination without
`
`copying the data into a temporary buffer in the modem processor RAM 112.”
`
`Ex. 1001 at 5:31-35 (emphasis added). See also, for example, the statement in the
`
`Page 17
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`
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`’949 patent that “aspects of the present disclosure may reduce the time it takes to
`
`boot secondary processors in a multi-processor system where secondary processor
`
`images are transferred from the primary processor. This reduction is achieved by
`
`avoiding extra memory copy operations and enabling concurrent image transfers
`
`with background data processing, such as authentication.” Id. at 11:17-24.
`
`34. For the CPU to transfer the software image data into its final location
`
`in system memory, it would need to copy the software image data from system
`
`memory to its final location. Any such technique would entail the use of the extra
`
`memory copy operations that the ’949 patent explicitly states are outside the scope
`
`of the invention. The invention of the ’949 patent uses the hardware transport
`
`mechanism to efficiently move the software image data through the hardware buffer
`
`integrated into the hardware transport mechanism 309 directly into the system
`
`memory 305 without involving the CPU in the direct transfer.
`
`35. Reinforcing these points, the ’949 patent states that the CPU of the
`
`secondary processor is not involved in the direct scatter loading of the executable
`
`image. For example, the patent states that “[o]nce the image header is processed,
`
`the executable image is directly scatter loaded into target memory, bypassing farther
`
`CPU involvement. ” Id. at 9:54-56. The ’949 patent also discloses that “[i]n one
`
`aspect, upon completion of each segment’s transfer, the secondary processor 302
`
`programs the scatter loader controller 304 to transfer the next segment and starts
`
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`
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`authentication of the segment that was just transferred. This enables the scatter
`
`loader controller 304 to transfer data while the secondary processor 302 performs
`
`the authentication.” Id. at 10:27-32. This disclosure further emphasizes that the
`
`direct transfer of the ’949 patent does not involve the CPU of the secondary
`
`processor. It is precisely this CPU that is performing the authentication at the same
`
`time as the transfer of the next segment is taking place. It is the scatter loader
`
`controller 304 which performs the transfer, not the CPU.
`
`36. The ’122 application further explains that “conventional loading
`
`processes require an intermediate step where the binary multi-segmented image is
`
`buffered (e.g., transferred into the system memory) and the later scattered into target
`
`locations (e.g., by a boot loader). Embodiments of the present disclosure provide
`
`techniques that alleviate the intermediate step of buffering required in conventional
`
`loading processes. Thus, embodiments of the present disclosure avoid extra memory
`
`copy operations, thereby improving performance (e.g., reducing the time required to
`
`boot secondary processors in a multi-processor system).” Ex. 2002 at pages 20-21,
`
`¶[0025].
`
`37. The direct scatter load technique disclosed in the ’949 patent has been
`
`the subject of litigation, including being asserted by Qualcomm against Apple in a
`
`recent trial in San Diego (Qualcomm vs. Apple, case no. 3:17-CV-1375-DMS-MDD,
`
`S.D. Cal.). As part of this litigation, expert witnesses and named inventors have
`
`Page 19
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`
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`characterized the scope of the direct scatter loading technique disclosed and claimed
`
`in the ’949 patent. For example, Intel’s declarant Dr. Lin testified at trial that the
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`“direct scatter loading” technique disclosed in the ’949 patent uses the “standard
`
`hardware transfer mechanism,” specifically a “communication bus” to “directly
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`scatter load the segments into memory” without the use of a buffer. Ex. 2005
`
`at 1174-77. Dr. Lin testified that some of the disclosed benefits of this approach are
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`“that it avoids extra memory and it avoids extra memory copy time.” Id. at 1177.
`
`Dr. Lin also testified that the “secret sauce” of the ’949 patent is that “separate
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`receipt enables direct scatter loading.” Id. at 1175-77. In other words, because the
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`modem processor receives the header first, it can “find out what the segments are
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`and the locations, and then with this information, it can directly move the segments
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`into memory.” Id.
`
`38. Similarly, Steve Haenichen, a named inventor of the ’949 patent,
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`testified at trial that prior art systems would “receive things in the memory, process
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`them, and then place them where they needed to be.” Ex. 2003 at 216. Mr.
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`Haenichen testified that in the system that was the basis for the ’949 patent, “we
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`really focused on getting rid of all of those stages of copying so things would come
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`right in the pipe from USB and land right in memory where they needed to be.” Id.
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`39. Mr. Haenichen further contrasted a particular prior art system named
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`“Gobi” with the patented invention as follows: “So if you look at Gobi, it reads
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`Page 20
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`
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`things into memory, figures out what they are, where they need to go, and it copies
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`them there; whereas in [the system that was the basis for the ’949 patent], we would
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`receive the data directly from USB and the only place it would go is right where it
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`needs to be. So we compared to like a nonstop flight. Instead of a flight with a stop
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`in the middle and a long layover, you just put it right where it needs to be at the end.”
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`Id. at 222.
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`40. Mr. Haenichen confirmed the fact that the ’949 patent involves direct
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`transfer of each data segment in the image to its final destination, with no
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`intermediate copies in the buffer, during cross examination. Ex. 2004 at 243-46.
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`Mr. Haenichen also confirmed that in the ’949 patent, the header is transmitted
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`before and separately from the data segments. Id. Mr. Haenichen also confirmed
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`that the reason for transmitting the header before and separately from the data
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`segments was so that the claimed secondary processor could request each data
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`segment and transfer the data segment directly from the hardware buffer into its final
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`destination in memory. Id.
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`41. As this testimony shows, receiving image data into a temporary or
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`intermediate memory buffer, then copying the data from this buffer into its final
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`location in system memory, is prior art technology to the ’949 patent.
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`Page 21
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`
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`42. At trial, Apple’s declarant Dr. Lin confirmed that he agreed with Mr.
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`Haenichen’s characterization of the invention of the ’949 patent. See, e.g., Ex. 2006
`
`at 1301-1302:
`
`Q. I want to take you to page 245 of the trial transcript, starting at line
`15.
`
`QUESTION: So, if you could sum up here, Qualcomm’s solution was
`to transfer the image header first, separately from the rest of the image.
`The image header specifies the final destination for each segment. The
`secondary processor then uses the image header to request each data
`segment, transferring each data segment directly from the hardware
`buffer into its final destination in memory. Have I accurately
`summarized the invention?
`ANSWER: Yeah, I think so.
`Were you here when Mr. Haenichen testified in that fashion?
`A.
`I was.
`Q. How does that compare with your analysis what Qualcomm’s
`proposed solution was?
`A.
`It is consistent.
`
`43. Dr. Lin also confirmed at trial that the ’949 invention does not use a
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`buffer located in the system memory to store the software image data. See, e.g., id.
`
`at 1177:
`
`Q. And what about the buffer? Is the buffer used for those data
`segments under this approach?
`A. No. It’s standard hardware transfer mechanism.
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`Page 22
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`
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`B.
`44.
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`Prosecution History of the ’949 Patent
`I have reviewed the prosecution history of the ’949 patent. The
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`following is a summary of key events.
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`45. U.S. Patent Application No. 13/052,516, which later issued as the ’949
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`Patent, was filed on March 21, 2011. The original claims of the application were all
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`rejected in an Office Action issued on July 19, 2013 as being anticipated by
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`International Publication No. WO 2006/077068 to Svensson (Ex. 1003), which is
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`referred to by Petitioner as “Svensson PCT.” Ex. 1004. Svensson PCT claims
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`priority to, and includes the same disclosure as, the Svensson patent (Ex. 1010) that
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`is relied on extensively throughout the petitions as the primary reference.
`
`46.
`
`In response to the rejections over Svensson PCT, the independent
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`claims were amended to require receiving, at a secondary processor, an image header
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`and at least one data segment of an executable software image, with “the image
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`header and each data segment being received separately.” Ex. 1005 at 2-7. The
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`claims were further amended to require scatter loading each data segment directly to
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`system memory of the secondary processor. See id.
`
`47. Following the amendments distinguishing the claims from Svensson
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`PCT, no further prior art rejections were made by the Patent Office. The ’949 Patent
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`was allowed on August 11, 2014 (Ex. 1006),
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