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`IPR2018-01334
`U.S. Patent No. 8,838,949
`Petitioner’s Reply Brief on Remand
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________________________________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________________________________________
`
`INTEL CORPORATION,
`Petitioner,
`
`v.
`
`QUALCOMM INCORPORATED,
`Patent Owner.
`____________________________________________
`
`
`IPR2018-01334
`U.S. Patent No. 8,838,949
`____________________________________________
`
`PETITIONER’S REPLY BRIEF ON REMAND1
`
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`1 IPR2018-01335 and IPR2018-01336 have been consolidated with IPR2018-
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`01334, and Petitioner will file this brief only in IPR2018-01334. All citations are
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`to IPR2018-01334 unless otherwise noted.
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`IPR2018-01334
`U.S. Patent No. 8,838,949
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`TABLE OF CONTENTS
`
`
`I.
`
`II.
`
`INTRODUCTION ........................................................................................... 1
`
`PATENT OWNER’S CONSTRUCTION OF HARDWARE BUFFER IS
`INCORRECT. .................................................................................................. 1
`
`A.
`
`B.
`
`The Intrinsic Evidence Does Not Support Patent Owner’s
`Construction. ......................................................................................... 1
`
`Patent Owner’s Construction Goes Beyond the Alleged
`Advance of the ’949 Patent. .................................................................. 3
`
`III.
`
`PETITIONER’S PROPOSED CONSTRUCTION OF “HARDWARE
`BUFFER” IS SUPPORTED BY THE INTRINSIC RECORD. ..................... 5
`
`IV. UNDER EITHER PROPOSED CONSTRUCTION, THE PRIOR ART
`DISCLOSES A “HARDWARE BUFFER.” ................................................... 6
`
`V.
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`THE PRIOR ART CHALLENGE TO CLAIMS 16 AND 17 CAN BE
`RESOLVED IN FAVOR OF PETITIONER. ................................................. 8
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`
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`i
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`IPR2018-01334
`U.S. Patent No. 8,838,949
`TABLE OF AUTHORITIES
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`
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`Page(s)
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`CASES
`Intel Corp. v. Qualcomm Inc., 21 F.4th 801 (Fed. Cir. 2021) ............................... 1, 8
`Unwired Planet v. Google, 660 F. App’x 974 (Fed. Cir. 2016) ................................ 5
`Wi-Lan USA, Inc. v. Apple, Inc., 830 F.3d 1374 (Fed. Cir. 2016) ............................. 2
`STATUTES, RULES, AND REGULATIONS
`37 C.F.R. § 42.6(a)(3) ................................................................................................ 4
`OTHER AUTHORITIES
`Cisco Systems. v. C-Cation Techs., Case IPR2014-00454 (PTAB Aug.
`29, 2014) (Paper 12) ........................................................................................ 4
`
`
`
`ii
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`
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`INTRODUCTION
`Patent Owner’s construction of “hardware buffer” is tantamount to the
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`IPR2018-01334
`U.S. Patent No. 8,838,949
`
`
`I.
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`negative construction already rejected by the Federal Circuit as “inadequate.” Intel
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`v. Qualcomm, 21 F.4th 801, 811 (Fed. Cir. 2021). Moreover, Patent Owner fails to
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`show that its construction is necessary to achieve its sweeping, out-of-context
`
`assertions about the claimed invention’s purpose. Regardless, because the
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`intermediate storage area (“ISA”) of Bauer and Svensson is neither a temporary
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`buffer nor part of any “system memory,” let alone the claimed system memory, it
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`satisfies either party’s construction of “hardware buffer.”
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`II.
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`PATENT OWNER’S CONSTRUCTION OF HARDWARE BUFFER IS
`INCORRECT.
`A. The Intrinsic Evidence Does Not Support Patent Owner’s
`Construction.
`
`Patent Owner’s construction is incorrect because the “hardware buffer” can be a
`
`temporary buffer as long as it is physically separate from the claimed system memory.
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`First, the statements that Patent Owner cites as support for excluding all
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`temporary buffers (PO Resp. Br. 5 (citing Ex. 1001, 2:17-55, 4:43-47, 5:31-35, 7:16-
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`30, 9:42-50, 11:17-24)) do not evidence such a purpose. See Pet. Op. Br. 7-11.
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`Statements such as “the direct scatter load technique avoids use of a temporary buffer”
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`(PO Resp. Br. 12 (citing Ex. 1001, 4:46-47)) are taken out of context, because they are
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`surrounded by discussion of other specific aspects of using temporary buffers, see Pet.
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`
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`1
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`
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`Op. Br. 7-11. It is these specific uses, such as a temporary buffer that stores the entire
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`IPR2018-01334
`U.S. Patent No. 8,838,949
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`executable software image, that the ’949 specification distinguishes. Id.; Ex. 1026 ¶¶
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`21-29; Ex. 1027 ¶¶ 8, 30. Further, as discussed in Section II.B, the ’949 statements
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`cited by Patent Owner to demonstrate that the “hardware buffer” is necessary for the
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`asserted advance evince at best a general intent to provide a more efficient loading
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`technique but do not call for a permanent, dedicated buffer. See Ex. 1027 ¶¶ 7-9.
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`Second, the ’949 specification does not require that the “hardware buffer” be
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`separate from all memory that might be characterized as system memory, as Patent
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`Owner suggests, PO Resp. Br. 6-7. Patent Owner’s construction imports this
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`restriction, contrary to the Board’s finding in its Final Written Decision that the ’949
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`patent “does not foreclose the possibility of implementing a [hardware] buffer in some
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`other system memory.” See FWD (Paper 30) at 13; Pet. Op. Br. 6.
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`Finally, Patent Owner’s attempts to use claim 2 to support its construction also
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`fail. PO Resp. Br. 10-11. Although Patent Owner argues that claim differentiation is
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`not a rigid rule (id., 10), there is a presumption that claim differentiation applies. Wi-
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`Lan USA, Inc. v. Apple, Inc., 830 F.3d 1374, 1391 (Fed. Cir. 2016). Regardless, even
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`Patent Owner concedes that claim 2 is narrower than claim 1. Indeed, while making
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`sweeping assertions across all claims, including claim 1, about the critical objectives
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`achieved by “the elimination of ‘extra memory copy operations’ in system memory,”
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`Patent Owner simultaneously argues that claim 2 is narrower than claim 1 because
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`2
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`
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`claim 2 excludes “copying data between system memory locations on the secondary
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`IPR2018-01334
`U.S. Patent No. 8,838,949
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`processor.” Id., 10-11. Patent Owner cannot import into claim 1 a prohibition on
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`copying between system memory locations while saying that claim 2 is narrower than
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`claim 1 because it excludes the same feature. Petitioner’s construction, on the other
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`hand, allows for claim differentiation. Pet. Op. Br. 6-7.
`
`B.
`
`Patent Owner’s Construction Goes Beyond the Alleged Advance of
`the ’949 Patent.
`
`Patent Owner primarily supports its “hardware buffer” construction by alleging
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`that it allows for a more “efficient” “zero copy” scatter loading technique, which it
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`claims is the key advance of the ’949 patent. PO Resp. Br. 4-10. This is incorrect.
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`First, the term “zero copy” is a misnomer. There is always an intermediate copying
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`step as the executable image moves from the primary processor to the hardware buffer,
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`and then to the claimed “system memory,” whether the hardware buffer is a permanent
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`buffer, temporary buffer, or internal RAM. Ex. 1027 ¶¶ 13-14 (distinguishing Ex.
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`1001, 7:20-26 and 11:17-24).
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`Second, Patent Owner’s citations to the specification (PO Resp. Br. 6-7 (citing
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`Ex. 1001, 4:43-47, 7:20-26, 11:17-24)) do not require that the “hardware buffer” be a
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`permanent buffer to enhance the scatter loading technique. The ’949 specification and
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`claims do not use the term “permanent” or require a particular level of performance or
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`efficiency. See Ex. 1027 ¶ 15.
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`Third, even assuming the ’949 patent requires the type of “efficient” scatter
`3
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`loading technique Patent Owner suggests (PO Resp. Br. 6), the use of a permanent,
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`IPR2018-01334
`U.S. Patent No. 8,838,949
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`dedicated buffer distinct from any system memory is not necessary to achieve this
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`goal.2 If anything, it is the separation between the “hardware buffer” and the claimed
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`“system memory” that provides efficiency in moving data segments from the
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`“hardware buffer” to the physically separate “system memory.” Ex. 1027 ¶ 17.
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`Moreover, because RAM internal to a processor chip works at near the speed of the
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`processor, copying data segments from an internal RAM (even if in system memory) to
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`an external DRAM (a physically separate system memory) would, like use of the
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`permanent buffer Patent Owner describes, be faster and more efficient than copying
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`data segments between external DRAM locations (the system memory copy operations
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`Patent Owner describes). Id. ¶¶ 18-26 (citing Ex. 2014, 288-89, 311; Ex. 2012, 72, 73,
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`97). Accordingly, the term “hardware buffer” should not be construed to preclude the
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`use of such an internal RAM as a “hardware buffer,” regardless of whether it might be
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`characterized as part of some system memory. Id. ¶ 19; see also Ex. 1028 (Rinard
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`Dep.), 77:8-80:1 (stating “hardware buffer” could be in RAM).
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`2 The Board should not consider any arguments in Dr. Rinard’s declaration (Ex. 2015
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`¶¶ 48-53) that are not set forth in Patent Owner’s brief. 37 C.F.R. § 42.6(a)(3)
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`(prohibiting incorporation by reference); Cisco Systems. v. C-Cation Techs., Case
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`IPR2014-00454 (PTAB Aug. 29, 2014) (Paper 12) (same).
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`4
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`Finally, Patent Owner’s self-serving inventor testimony is of limited relevance.
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`IPR2018-01334
`U.S. Patent No. 8,838,949
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`See Unwired Planet v. Google, 660 F. App’x 974, 984 (Fed. Cir. 2016) (“[I]nventor
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`testimony as to the inventor’s subjective intent is irrelevant to the issue of claim
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`construction.”). This is especially true where, as here, the broadest reasonable
`
`interpretation standard applies. Moreover, Mr. Haehnichen’s testimony boils down to
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`the proposition that Patent Owner allegedly wanted to develop a more efficient process
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`without “copying things around memory.” PO Resp. Br. 8-9 (Ex. 2003, 216:16-21;
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`Ex. 2015 ¶¶ 39-40). Yet, the ’949 patent requires copying from a “hardware buffer” to
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`“system memory,” an efficient scatter loading process does not require the use of a
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`permanent buffer, and the ’949 patent does not even discuss the details of the “Gobi”
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`or “Sahara” systems Mr. Haehnichen described. Ex. 1027 ¶ 16.
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`III. PETITIONER’S PROPOSED CONSTRUCTION OF “HARDWARE
`BUFFER” IS SUPPORTED BY THE INTRINSIC RECORD.
`Patent Owner unpersuasively argues that Petitioner’s proposed construction is
`
`incorrect for several reasons. First, Patent Owner argues that the patent distinguishes
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`prior art temporary buffers formed in system memory. PO Resp. Br. 5, 14 (citing Ex.
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`1001, 2:17-22, 2:23-28, 2:29-31, 2:35-41, 7:20-26). The cited statements, however,
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`distinguish the prior art on other grounds. See Pet. Op. Br. 9-11.
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`Moreover, Petitioner’s construction does not encompass temporary buffers in
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`the claimed “system memory,” since the “hardware buffer” must be physically separate
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`from the claimed “system memory.” Id. This is what Petitioner’s expert referred to in
`5
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`IPR2018-01334
`U.S. Patent No. 8,838,949
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`stating that “[t]he ’949 patent makes a distinction between prior art systems that used a
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`‘temporary buffer’ that was part of the system memory (Ex-1001, 2:23-41), and the
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`alleged invention that uses a ‘hardware buffer’ separate from the system memory (id.,
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`2:58-61, 7:20-26, Fig. 3),” belying Patent Owner’s suggestion of an inconsistency (PO
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`Resp. Br. 14-15). See Ex. 1027 ¶ 28; Pet. Op. Br. 11.
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`Second, in accordance with Federal Circuit guidance, Petitioner’s construction
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`creates both a physical and conceptual distinction between the “hardware buffer” and
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`claimed “system memory.” But see PO Resp. Br. 14. That is because the “hardware
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`buffer” does not perform the function of a memory into which the image is loaded and
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`executed, as does the claimed “system memory.” Pet. Op. Br. 7-8.
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`Finally, Patent Owner minimizes the relevance of the prosecution history, PO
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`Resp. Br. 15, which shows that the Examiner understood the ISA of Bauer and
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`Svensson to be a “hardware buffer.” Pet. Op. Br. 11-12. Although Patent Owner now
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`asserts that the “hardware buffer” is a key asserted advance, PO Resp. Br. 10, Patent
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`Owner never advanced such a position during prosecution. Indeed, Patent Owner
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`admits that its “hardware buffer” is not the reason for the patent’s allowance over the
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`cited prior art, id. at 15, and its expert admitted that “hardware buffers” were well-
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`known in the prior art, Ex. 1022 (Rinard Dep.) 43:11-17.
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`IV. UNDER EITHER PROPOSED CONSTRUCTION, THE PRIOR ART
`DISCLOSES A “HARDWARE BUFFER.”
`Under the correct construction proposed by Petitioner, Bauer and Svensson’s
`6
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`ISA is a “hardware buffer” because (1) it is memory separate from the memory where
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`IPR2018-01334
`U.S. Patent No. 8,838,949
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`the image is loaded and executed, and (2) even if the ISA were to be found to be part
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`of some other system memory, it is still physically separate from Bauer and Svensson’s
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`DSP XRAM. Pet. Op. Br. 13-17; Ex. 2010, 21:9-26:21.
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`Patent Owner argues that it is more “efficient” to use a permanent, dedicated
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`buffer for direct transfer to a separate system memory, in part because it is fast. PO
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`Resp. Br. 7. But it is just as fast and efficient to use Bauer and Svensson’s ISA for
`
`direct transfer to a separate system memory. Ex. 1027 ¶ 33. Both cases require
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`copying from one memory—Bauer and Svensson’s ISA (whether it is characterized as
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`permanent or temporary) or a permanent buffer in Patent Owner’s scenario—and then
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`writing to the “system memory.” Id. Given that Bauer and Svensson’s ISA is in
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`internal RAM 108/208 that operates at or near the speed of the processor, it will
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`operate as quickly and efficiently as copying from a permanent buffer. Id. (citing Ex.
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`1010, 3:64-4:3).
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`Even under Patent Owner’s construction, the ISA is a permanent buffer distinct
`
`from the claimed “system memory.” Though Patent Owner argues that the ISA is a
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`temporary buffer because it exists only after being allocated (PO Resp. Br. 17), the
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`ISA is never described as deallocated and functions solely to perform the same
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`function as a permanent buffer. See Pet. Op. Br. 16-17 (Ex. 1026 ¶¶ 41-45). Even if
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`Bauer and Svensson’s SARAM & DARAM 108/208 were considered “system
`
`
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`7
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`
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`memory,” PO Resp. Br. 18, this does not make the ISA a system memory because it
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`IPR2018-01334
`U.S. Patent No. 8,838,949
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`cannot be used to load and execute programs, Ex. 1027 ¶ 34.
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`Finally, Patent Owner is wrong that the Board’s finding that the ISA is a
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`temporary buffer was not challenged on appeal or disturbed by the Federal Circuit’s
`
`opinion. PO Resp. Br. 16. Petitioner did challenge that finding on appeal, and the
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`Federal Circuit vacated the “rejection of Intel’s challenges to claims 1–9 and 12,”
`
`noting separately that “[i]t is not clear what precisely constitutes a ‘temporary buffer.’”
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`Intel, 21 F.4th at 811-12; Ex. 1029 (Appeal Op. Br.) at 3 (challenging finding that the
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`ISA is a temporary buffer).
`
`V. THE PRIOR ART CHALLENGE TO CLAIMS 16 AND 17 CAN BE
`RESOLVED IN FAVOR OF PETITIONER.
`The Board can and should find that Petitioner has provided sufficient evidence
`
`to show that claims 16 and 17 are unpatentable. The Federal Circuit guidance that
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`indefiniteness does not render the adjudication of a prior art challenge impossible in a
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`scenario involving alternative claim limitations was merely exemplary, unlike what
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`Patent Owner suggests, PO Resp. Br. 19. Given that Patent Owner and Petitioner have
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`identified the same structures for the means-plus-function terms (and Patent Owner has
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`not pointed to any other structures, PO Resp. Br. 19), these structures are the only ones
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`that can be used to determine whether claims 16-17 are unpatentable in view of
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`Petitioner’s prior art combination. See Pet. Op. Br. 18-19.
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`8
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`Date: June 15, 2022
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`IPR2018-01334
`U.S. Patent No. 8,838,949
`
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`Respectfully submitted,
`
`/Joseph F. Haag/
`Joseph F. Haag
`Registration No. 42,612
`
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`9
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`IPR2018-01334
`U.S. Patent No. 8,838,949
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`TABLE OF EXHIBITS
`
`Exhibit
`
`Description
`
`1001
`
`1002
`
`1003
`
`1004
`
`1005
`
`1006
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`1007
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`1008
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`1009
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`1010
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`1011
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`1012
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`1013
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`1014
`
`U.S. Patent No. 8,838,949 (“’949 patent”)
`
`Declaration of Professor Bill Lin
`PCT Publication No. WO 2006/077068 to Svensson et al.
`(“Svensson PCT”)
`’949 File History, Jul. 19, 2013 Office Action
`
`’949 File History, Oct. 17, 2013 Response to Office Action
`
`’949 File History, May 9, 2014 Notice of Allowance
`Inv. No. 337-TA-1065, Order No. 28: Construing Terms of the
`Asserted Patents dated Mar. 5, 2018 (“Claim Construction
`Order”)
`Inv. No. 337-TA-1065, Joint Claim Construction Chart dated
`Nov. 20, 2017 (“Claim Construction Chart”)
`U.S. Patent Application Publication No. 2006/0288019 to Bauer
`et al. (“Bauer”)
`U.S. Patent No. 7,356,680 to Svensson et al. (“Svensson”)
`Korean Patent Application Publication No. 10-2002-0036354 to
`Kim (“Kim”)
`English language translation of Korean Patent Application
`Publication No. 10-2002-0036354 (Kim), with Translator’s
`Certificate of Translation
`U.S. Patent Application Publication No. 2007/0140199 to Zhao et
`al. (“Zhao”)
`U.S. Patent No. 7,203,829 to Lim (“Lim”)
`
`
`
`10
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`
`
`
`Exhibit
`
`1015
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`1016
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`1017
`
`1018
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`1019
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`1020
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`1021
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`1022
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`1023
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`1024
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`1025
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`1026
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`1027
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`1028
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`1029
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`IPR2018-01334
`U.S. Patent No. 8,838,949
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`
`Description
`Computer Technology Encyclopedia: Quick Reference for
`Students and Professionals, 2009 (“Encyclopedia”)
`Dictionary of Computer and Internet Terms, 10th Ed., 2009
`(“Dictionary”)
`IBM Dictionary of Computing, 1994 (“IBM Dictionary”)
`Microsoft Computer Dictionary, 5th Ed., 2002 (“Microsoft
`Dictionary”)
`U.S. Patent Application Publication No. 2009/0307478 to
`Gehrmann (“Gehrmann”)
`Declaration of Dr. Bill Lin (originally IPR2018-01335 Exhibit
`1102)
`Declaration of Dr. Bill Lin (originally IPR2018-01336 Exhibit
`1202)
`Transcript of August 28, 2019 Deposition of Martin C. Rinard
`
`Reply Declaration of Dr. Bill Lin
`Defendant And Counterclaim Plaintiff Apple Inc.’s Opening
`Claim Construction Brief, Case No. 3:17-CV-01375-DMS-MDD
`Memorandum In Support Of Apple Inc.’s Motion For Judgment
`As A Matter Of Law Pursuant To Rule 50(A), Case No. 3:17-
`CV-01375-DMS-MDD
`Declaration of Professor Bill Lin on Remand
`
`Reply Declaration of Professor Bill Lin on Remand
`
`Remand Deposition of Dr. Martin Rinard
`
`Petitioner’s Opening Brief on Appeal
`
`
`
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`11
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`IPR2018-01334
`U.S. Patent No. 8,838,949
`
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`CERTIFICATE OF SERVICE
`
`I hereby certify that, on June 15, 2022, I caused a true and correct copy of
`
`the following materials:
`
` Petitioner’s Reply Brief on Remand
` Exhibits 1027-1029
` Updated Exhibit List
`
`to be served via electronic mail on the following lead and backup counsel:
`
`Matthew W. Johnson (mwjohnson@jonesday.com)
`Joseph M. Sauer (jmsauer@jonesday.com)
`Joshua R. Nightingale (jrnightingale@jonesday.com)
`David B. Cochran (dcochran@jonesday.com)
`David M. Maiorana (dmaiorana@jonesday.com)
`
`
`
`Dated: June 15, 2022
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`/Joseph F. Haag/
`Joseph F. Haag
`Reg. No. 42,612
`
`
`
`
`
`12
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`
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