UNITED STATES PATENT AND TRADEMARK OFFICE
`____________________________________________
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________________________________________
`Intel Corporation
`Petitioner
`v.
`Qualcomm Incorporated
`Patent Owner of U.S. Patent No. 8,838,949
`Claims 1-9, 22, and 23
`____________________________________________
`Trial No. IPR2018-01334
`____________________________________________
`DECLARATION OF BILL LIN, PH.D.
`ON BEHALF OF PETITIONER
`
`INTEL 1002
`
`

`

`U.S. Patent No. 8,838,949
`Declaration of Bill Lin, Ph.D.
`
`TABLE OF CONTENTS
`I. 
`BACKGROUND ............................................................................................. 1 
`II.  MATERIALS CONSIDERED ........................................................................ 4 
`III.  LEGAL PRINCIPLES ..................................................................................... 5 
`A. 
`Claim Construction ............................................................................... 5 
`B. 
`Anticipation ........................................................................................... 6 
`C. 
`Obviousness .......................................................................................... 7 
`IV.  SUMMARY OF OPINIONS ........................................................................... 9 
`V. 
`BRIEF DESCRIPTION OF THE TECHNOLOGY ..................................... 10 
`A.  Multi-Processor Systems ..................................................................... 10 
`1. 
`Processor-To-Processor Communications ................................ 10 
`2. 
`Processor Software Code .......................................................... 14 
`3. 
`Characteristics of Memory ........................................................ 15 
`Storing, Loading, and Executing Processor Software
`Code ..................................................................................................... 16 
`1. 
`Storing the Processor Software Code in Memory .................... 16 
`2. 
`Loading and Executing Multi-Segmented Software
`Images ....................................................................................... 17 
`Sharing Memory in Multi-Processor Systems .......................... 19 
`3. 
`Boot Loading ....................................................................................... 20 
`C. 
`VI.  OVERVIEW OF THE ʼ949 PATENT .......................................................... 22 
`A.  Alleged Problem of the Prior Art ........................................................ 22 
`B. 
`Purported Solution of the ’949 Patent ................................................. 23 
`
`B. 
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`U.S. Patent No. 8,838,949
`Declaration of Bill Lin, Ph.D.
`
`X. 
`
`C. 
`Prosecution History of the ’949 Patent ............................................... 30 
`VII.  LEVEL OF ORDINARY SKILL IN THE ART ........................................... 34 
`VIII.  CLAIM CONSTRUCTION .......................................................................... 34 
`A. 
`“image header” (claims 1, 4, 5, 20, and 22) ........................................ 35 
`IX.  OVERVIEW OF PRINCIPAL PRIOR ART REFERENCES ...................... 36 
`A. 
`Svensson (Ex-1010) ............................................................................ 36 
`B. 
`Bauer (Ex-1009) .................................................................................. 39 
`C. 
`Kim (Ex-1011) (Including English Translation (Ex-
`1012)) .................................................................................................. 43 
`Zhao (Ex-1013) ................................................................................... 46 
`D. 
`Lim (Ex-1014) ..................................................................................... 48 
`E. 
`SPECIFIC GROUNDS FOR CHALLENGE ................................................ 50 
`A.  Ground 1: Claims 1-9, 22, And 23 Are Rendered
`Obvious By The Combination Of Bauer, Svensson, And
`Kim ...................................................................................................... 50 
`1. 
`Reference to “Bauer and Svensson Combined” ....................... 50 
`2. 
`Claim 1 ...................................................................................... 52 
`3. 
`Claim 2: “The multi-processor system of claim 1
`in which the scatter loader controller is configured
`to load the executable software image directly
`from the hardware buffer to the system memory of
`the secondary processor without copying data
`between system memory locations on the
`secondary processor.” ............................................................... 81 
`Claim 3: “The multi-processor system of claim 1
`in which raw image data of the executable
`software image is received by the secondary
`processor via the interface.” ...................................................... 82 
`ii
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`4. 
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`U.S. Patent No. 8,838,949
`Declaration of Bill Lin, Ph.D.
`
`5. 
`
`6. 
`
`Claim 4: “The multi-processor system of claim 1
`in which the secondary processor is configured to
`process the image header to determine at least one
`location within the system memory to store the at
`least one data segment.” ............................................................ 84 
`Claim 5: “The multi-processor system of claim 4
`in which the secondary processor is configured to
`determine, based on the received image header, the
`at least one location within the system memory to
`store the at least one data segment before receiving
`the at least one data segment.” .................................................. 85 
`Claim 6: “The multi-processor system of claim 1,
`in which the secondary processor further
`comprises a non-volatile memory storing a boot
`loader that initiates transfer of the executable
`software image for the secondary processor.” .......................... 88 
`Claim 7: “The multi-processor system of claim 1
`in which the primary and secondary processors are
`located on different chips.” ....................................................... 94 
`Claim 8: “The multi-processor system of claim 1
`in which the portion of the executable software
`image is loaded into the system memory of the
`secondary processor without an entire executable
`software image being stored in the hardware
`buffer.” ...................................................................................... 96 
`10.  Claim 9: “The multi-processor system of claim 1
`integrated into at least one of a mobile phone … a
`computer, a hand-held personal communication
`systems (PCS) unit, a portable data unit….” ............................ 99 
`11.  Claim 22 .................................................................................. 100 
`12.  Claim 23: “The method of claim 22 further
`comprising performing the sending, receiving and
`executing in at least one of a mobile phone … a
`
`7. 
`
`8. 
`
`9. 
`
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`U.S. Patent No. 8,838,949
`Declaration of Bill Lin, Ph.D.
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`computer, a hand-held personal communication
`systems (PCS) unit, a portable data unit….” .......................... 104 
`XI.  AVAILABILITY FOR CROSS-EXAMINATION .................................... 184 
`XII.  RIGHT TO SUPPLEMENT ........................................................................ 185 
`XIII.  JURAT ......................................................................................................... 186 
`
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`U.S. Patent No. 8,838,949
`Declaration of Bill Lin, Ph.D.
`
`1.
`
`I, Bill Lin, Ph.D. declare as follows:
`
`I.
`
`BACKGROUND
`2.
`I am currently Professor and Vice Chair of Electrical and Computer
`
`Engineering at the University of California, San Diego (UCSD). I am also Adjunct
`
`Professor of Computer Science and Engineering at UCSD.
`
`3. My Curriculum Vitae, which states my qualifications more fully, is
`
`attached as Appendix A. A list of all cases in which I have testified as an expert at
`
`trial or by deposition in the last four years is also included in Appendix A.
`
`4.
`
`I received a Bachelor’s of Science degree in 1985, a Master’s of
`
`Science degree in 1988, and a Ph.D. in 1991, all in Electrical Engineering and
`
`Computer Sciences from the University of California, Berkeley.
`
`5.
`
`I joined UCSD in 1997, and I have been a tenured professor since
`
`1999. My teaching and research has focused on computer architecture and
`
`computer network problems, including the design of multiprocessor and multi-core
`
`processor architectures, multiprocessor and multi-core processor interconnection
`
`buses and networks, network processors, systems-on-chips, and data networks. I
`
`regularly teach a senior-level design course on the design of advanced processors,
`
`and I have taught graduate courses in hardware/software co-design and advanced
`
`special topics in computer architecture.
`
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`U.S. Patent No. 8,838,949
`Declaration of Bill Lin, Ph.D.
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`6.
`
`At UCSD, I am a Principal Investigator in the UCSD Center for
`
`Networked Systems (CNS). CNS brings together researchers to work on a range
`
`of challenges in the design of future networked systems. My contribution to CNS
`
`has been expertise in the design of computer architecture solutions for packet
`
`processing and computer networking. I am also a Principal Investigator in the
`
`UCSD Center for Wireless Communications (CWC). CWC brings together
`
`researchers to work on a range of challenges in the design of future wireless
`
`communications systems. My contribution to CWC has been expertise in the
`
`design of multi-core processor architectures for wireless communications and
`
`mobile computing.
`
`7.
`
`Prior to joining UCSD, I was the Head of the Systems and
`
`Communications Group at IMEC in Leuven, Belgium, where I led a team of
`
`researchers who worked on a range of computer design problems, including
`
`hardware/software co-design, processor interfaces, multiprocessor and multi-core
`
`processor design methodologies, and specialized processors for wireless
`
`communications and computer networking.
`
`8.
`
`During my career, I have received or worked on research efforts that
`
`received millions of dollars in research funding from both government agencies
`
`and industry, including funding for research in multi-core processor design,
`
`2
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`U.S. Patent No. 8,838,949
`Declaration of Bill Lin, Ph.D.
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`system-on-chips, hardware/software co-design, packet processing, and computer
`
`networks.
`
`9.
`
`I have served as an Associate or Guest Editor for several journals
`
`published by the Association for Computing Machinery (“ACM”) and the Institute
`
`of Electrical and Electronics Engineers (“IEEE”). I have also served as General
`
`Chair of several ACM/IEEE conferences, and on the Organizing or Steering
`
`Committees of many ACM/IEEE conferences, and I have served on the Technical
`
`Program Committees of numerous ACM/IEEE conferences. I am the author of
`
`over 170 peer-reviewed publications in the field of computer engineering dating to
`
`the 1980s, including journal articles, conference papers, book chapters, technical
`
`reports, and invited papers. A number of these publications have received best
`
`paper awards or distinguished paper citations. I have also given numerous invited
`
`and keynote talks around the world. A list of my publications within the last ten
`
`years is included in my CV.
`
`10.
`
`I am the inventor of five patents: U.S. Patent Nos. 8,443,444,
`
`7,860,004, 7,672,005, 5,870,588, and 5,748,487.
`
`11.
`
`I have been retained by counsel for Intel Corporation (“Petitioner”) as
`
`an independent expert witness for the above captioned Petition for Inter Partes
`
`Review of U.S. Patent No. 8,838,949 (the “’949 patent”) (Ex-1001). I am being
`
`3
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`U.S. Patent No. 8,838,949
`Declaration of Bill Lin, Ph.D.
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`compensated at my normal hourly consulting rate of $550 for my work. My
`
`compensation is not dependent on and in no way affects the substance of my
`
`statements in this Declaration.
`
`12.
`
`I have no financial interest in the Petitioner. I similarly have no
`
`financial interest in the ’949 patent, and have had no contact with the named
`
`inventors of the ’949 patent.
`
`II. MATERIALS CONSIDERED
`13.
`I have reviewed the specification, claims, and file history of the ’949
`
`patent. I understand that the ’949 patent claims priority to U.S. Provisional
`
`Application No. 61/324,035, filed April 14, 2010, U.S. Provisional Application
`
`No. 61/316,369, filed March 22, 2010, U.S. Provisional Application No.
`
`61/324,122, filed April 14, 2010, and U.S. Provisional Application No.
`
`61/325,519, filed April 19, 2010.
`
`14.
`
`I have also reviewed the following references, all of which I
`
`understand to be prior art to the ’949 patent:
`
` U.S. Patent Application Publication No. US2006/0288019A1 to
`
`Bauer et al. (“Bauer”) (Ex-1009)
`
` U.S. Patent No. 7,356,680 to Svensson et al. (“Svensson”) (Ex-
`
`1010).
`
`4
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`U.S. Patent No. 8,838,949
`Declaration of Bill Lin, Ph.D.
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` Korean Patent Application Publication No. 10-2002-0036354 to
`
`Kim (“Kim”) (Ex-1011) (English language translation - Ex-1012).
`
`15.
`
`In addition to the documents listed above, I have also reviewed the
`
`file history of the ’949 patent, all of the documents listed in Petitioner’s List of
`
`Exhibits in the accompanying petition and all other documents cited in this
`
`declaration.
`
`III. LEGAL PRINCIPLES
`16.
`I am not an attorney. For the purposes of this declaration, I have been
`
`informed about certain aspects of the law that are relevant to my opinions. My
`
`understanding of the law is as follows:
`
`A. Claim Construction
`17.
`I have been informed that claim construction is a matter of law and
`
`that the final claim construction will ultimately be determined by the Board. For
`
`the purposes of my analysis in this proceeding and with respect to the prior art, I
`
`have been informed that patents are currently reviewed in an inter partes review
`
`(IPR) proceeding under the “broadest reasonable interpretation” standard
`
`(hereinafter “BRI standard”). I also have been informed that IPRs may soon be
`
`reviewed under what is known as “the Phillips standard.”
`
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`U.S. Patent No. 8,838,949
`Declaration of Bill Lin, Ph.D.
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`18.
`
`I have been informed that the BRI standard refers to the broadest
`
`reasonable interpretation that a person of ordinary skill in the art would give to a
`
`claim term in light of the specification.
`
`19.
`
`I have been informed that under the Phillips standard, claim terms are
`
`generally given their plain and ordinary meaning as understood by a person of
`
`ordinary skill in the art at the time of the invention, with the claim term read not
`
`only in the context of the particular claim in which the disputed term appears, but
`
`also in the context of the entire patent, including the specification.
`
`20.
`
`I have been informed that the patentee can serve as his or her own
`
`lexicographer. As such, if a claim term is provided with a specific definition in the
`
`specification, that claim term should be interpreted in light of the particular
`
`definition provided by the patentee.
`
`B. Anticipation
`21.
`I have been informed and understand that a patent claim is invalid if it
`
`is “anticipated” by prior art. For the claim to be invalid because it is anticipated,
`
`all of its requirements must have existed in a single device or method that predates
`
`the claimed invention, or must have been described in a single publication or
`
`patent that predates the claimed invention. A patent claim may be “anticipated” if
`
`each element of that claim is present either explicitly, implicitly, or inherently in a
`
`single prior art reference. I have also been informed that, to be an inherent
`6
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`U.S. Patent No. 8,838,949
`Declaration of Bill Lin, Ph.D.
`
`disclosure, the prior art reference must necessarily disclose the limitation, and the
`
`fact that the reference might possibly practice or contain a claimed limitation is
`
`insufficient to establish that the reference inherently teaches the limitation.
`
`C. Obviousness
`22.
`I have been informed and understand that a patent claim is invalid if
`
`the claimed invention would have been obvious to a person of ordinary skill in the
`
`art at the time the application was filed. This means that, even if all of the
`
`requirements of a claim are not found in a single prior art reference, the claim is
`
`not patentable if the differences between the subject matter in the prior art and the
`
`subject matter in the claim would have been obvious to a person of ordinary skill in
`
`the art at the time the application was filed.
`
`23.
`
`I have been informed and understand that a determination of whether
`
`a claim would have been obvious should be based upon several factors, including,
`
`among others:
`
` the level of ordinary skill in the art at the time the application was
`
`filed;
`
` the scope and content of the prior art; and
`
` what differences, if any, existed between the claimed invention and
`
`the prior art.
`
`7
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`U.S. Patent No. 8,838,949
`Declaration of Bill Lin, Ph.D.
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`24.
`
`I have been informed and understand that the teachings of two or
`
`more references may be combined in the same way as disclosed in the claims, if
`
`such a combination would have been obvious to one having ordinary skill in the
`
`art. In determining whether a combination based on either a single reference or
`
`multiple references would have been obvious, it is appropriate to consider, among
`
`other factors:
`
` whether the teachings of the prior art references disclose known
`
`concepts combined in familiar ways, which, when combined,
`
`would yield predictable results;
`
` whether a person of ordinary skill in the art could implement a
`
`predictable variation, and would see the benefit of doing so;
`
` whether the claimed elements represent one of a limited number of
`
`known design choices, and would have a reasonable expectation of
`
`success by those skilled in the art;
`
` whether a person of ordinary skill would have recognized a reason
`
`to combine known elements in the manner described in the claim;
`
` whether there is some teaching or suggestion in the prior art to
`
`make the modification or combination of elements claimed in the
`
`patent; and
`
`8
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`U.S. Patent No. 8,838,949
`Declaration of Bill Lin, Ph.D.
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` whether the innovation applies a known technique that had been
`
`used to improve a similar device or method in a similar way.
`
`25.
`
`I understand that one of ordinary skill in the art has ordinary
`
`creativity, and is not an automaton.
`
`26.
`
`I understand that in considering obviousness, it is important not to
`
`determine obviousness using the benefit of hindsight derived from the patent being
`
`considered.
`
`27.
`
`I have been informed and understand that a single reference alone can
`
`render a patent claim obvious, if any differences between that reference and the
`
`claims would have been obvious to a person of ordinary skill in the art at the time
`
`of the alleged invention—that is, if the person of ordinary skill could readily adapt
`
`the reference to meet the claims of the patent, by applying known concepts to
`
`achieve expected results in the adaptation of the reference.
`
`IV. SUMMARY OF OPINIONS
`28.
`It is my opinion that every limitation of claims 1-9, 22, and 23 of the
`
`’949 patent is disclosed by the prior art, and that claims 1-9, 22, and 23 are
`
`rendered obvious by the prior art cited in this declaration.
`
`9
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`

`U.S. Patent No. 8,838,949
`Declaration of Bill Lin, Ph.D.
`
`V. BRIEF DESCRIPTION OF THE TECHNOLOGY
`A. Multi-Processor Systems
`1.
`Processor-To-Processor Communications
`29. The ’949 patent generally relates to communications between
`
`processors. Processors are common components in electrical devices that perform
`
`various functions to make the devices operate. Electrical devices may have
`
`multiple processors to handle different responsibilities. For example, a mobile
`
`telephone may include a “baseband” processor—which the ’949 patent calls a
`
`“modem” processor—and an “application” processor. Ex-1001, 1:41-44.
`
`30. The baseband/modem processor typically performs tasks relating to
`
`the transmission and reception of data to/from other devices over a network such as
`
`a wireless communication network. For example, Figure 5 of the ’949 patent
`
`shows a mobile telephone 520 communicating with base stations 540 in a wireless
`
`communication system 500.
`
`10
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`U.S. Patent No. 8,838,949
`Declaration of Bill Lin, Ph.D.
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`
`
`Ex-1001, Fig. 5.
`31. The baseband/modem processor in the mobile telephone 520 is
`
`responsible for sending data to and receiving data from base stations 540. The
`
`base stations 540 facilitate communication between the mobile telephone 520 and
`
`other devices, such as a portable computer 530, in the wireless communication
`
`system 500. Ex-1001, 11:25-39, Fig. 5.
`
`32. The application processor typically runs applications and other
`
`computer programs on the mobile telephone—e.g., email applications, video chat,
`
`text messaging, phone applications, GPS applications, etc.
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`11
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`U.S. Patent No. 8,838,949
`Declaration of Bill Lin, Ph.D.
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`33. The baseband/modem and application processors need to
`
`communicate with each other. For example, when a user of a mobile telephone
`
`composes an email or text message using an application running on the application
`
`processor, the application processor must send the message to the
`
`baseband/modem processor so that the baseband/modem processor can transmit the
`
`message to the base station. Similarly, when a mobile telephone receives data
`
`from the base station, the baseband/modem processor receives the data and then
`
`transfers it to the application processor so that the user can view the data in an
`
`email or other application.
`
`34. The baseband/modem and application processors typically
`
`communicate with each other by sending pieces of data over a “bus.” A bus,
`
`sometimes referred to as an “interface,” is typically a set of wires over which
`
`processors send electrical signals to each other. For example, Figure 2 of the ’949
`
`patent shows two processors (Application Processor 204 and Modem Processor
`
`210) connected by Inter-Chip Communication Bus 234.
`
`12
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`U.S. Patent No. 8,838,949
`Declaration of Bill Lin, Ph.D.
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`
`
`Ex-1001, Fig. 2.
`35. Many different types of buses were known prior to the alleged
`
`invention of the ’949 patent. To enable compatibility between processors of
`
`different manufacturers, buses usually operate according to one of a number of
`
`well-known standards. Standardized buses that were commonly used in mobile
`
`telephones and other multi-processor devices include High Speed Synchronous
`
`Interface (HSI), Universal Serial Bus (USB), USB High Speed Inter-Chip (HSIC),
`
`Mobile Industry Processor Interface (MIPI), Secure Digital Input/Output (SDIO),
`
`Universal Asynchronous Receiver-Transmitter (UART), Serial Peripheral Interface
`
`(SPI) and Inter-Integrated Ciruit (I2C). See, e.g., Ex-1001, 5:35-43; see also Ex-
`
`13
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`U.S. Patent No. 8,838,949
`Declaration of Bill Lin, Ph.D.
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`1013, ¶32, Fig. 5 (disclosing interfaces such as “one or more universal serial bus
`
`(USB) interfaces, micro-USB interfaces, universal asynchronous receiver-
`
`transmitter (UART) interfaces, general purpose input/output (GPIO) interfaces,
`
`control/status lines, control/data lines, shared memory, and so forth”).
`
`2.
`Processor Software Code
`36. A processor operates by executing software code that instructs the
`
`processor to perform specific operations. There are different types of software
`
`code for performing different types of operations. For example, when a processor
`
`is initially powered up, it typically executes “boot code” that instructs the
`
`processor to perform certain initialization operations. Such initialization
`
`operations may include determining what other devices may be connected to the
`
`processor and where such other devices may be located. For example, the boot
`
`code may instruct the processor to determine addresses associated with hardware
`
`peripherals, such as a keypad, a visual display, and memory.
`
`37. After the processor executes its boot code, it typically executes
`
`“program code” that instructs the processor to perform various operations that the
`
`processor has been designated to perform. For example, in the case of the above-
`
`described baseband/modem processor, the program code may instruct the
`
`baseband/modem processor to transfer received data to the application processor so
`
`that a user can view the data in an email or other application. In the case of the
`14
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`U.S. Patent No. 8,838,949
`Declaration of Bill Lin, Ph.D.
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`above-described application processor, the program code may instruct the
`
`application processor to send a message to the baseband/modem processor so that
`
`the baseband/modem processor can transmit the message to the base station.
`
`3.
`Characteristics of Memory
`38. To be executed, software code must be stored in memory that is
`
`accessible to the processor. The processor reads the code from the memory and
`
`then executes the code. There are basically two types of memory—non-volatile
`
`memory and volatile memory. Non-volatile (or persistent) memory is designed to
`
`store code and other data regardless of whether power is being applied to the
`
`memory. In contrast, volatile memory can only store code and other data when
`
`power is being applied to the memory. That is, once power is removed from
`
`volatile memory, all code and other data previously stored in the memory will be
`
`lost.
`
`39. Examples of non-volatile memory include electrically erasable
`
`programmable read-only memory (EEPROM) and flash memory. These types of
`
`non-volatile memory, as well as others, have characteristics that make them
`
`suitable for long-term persistent storage. For example, non-volatile memory can
`
`store code and other data for long periods of time after they have been initially
`
`programmed regardless of whether power is being applied to the memory.
`
`15
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`U.S. Patent No. 8,838,949
`Declaration of Bill Lin, Ph.D.
`
`However, non-volatile memory typically costs more, provides lower performance
`
`(e.g., operates slower), and requires more space than volatile memory.
`
`40. Examples of volatile memory include random access memory (RAM),
`
`dynamic RAM (DRAM) and static RAM (SRAM). These types of volatile
`
`memory, as well as others, have characteristics that make them suitable for short-
`
`term storage. For example, code and other data can be quickly stored and retrieved
`
`from volatile memory, thereby increasing system performance. But any code or
`
`other data stored in volatile memory is lost after power is removed from the
`
`memory, so using volatile memory for long-term storage is typically not feasible in
`
`devices that may lose power (e.g., mobile telephones).
`
`41. A data buffer is typically used as a temporary storage area that allows
`
`data to be moved from one location to another. The data buffer is often some
`
`portion of volatile memory.
`
`B.
`
`Storing, Loading, and Executing Processor Software Code
`1.
`Storing the Processor Software Code in Memory
`42. Software code is typically stored, at least initially, in non-volatile
`
`memory. The code is often later transferred from non-volatile memory to volatile
`
`memory, which is typically faster (and can be less expensive) than non-volatile
`
`memory. It is common for system designers to have processors use a type of
`
`volatile memory as a work space where the processor can execute software and
`
`16
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`U.S. Patent No. 8,838,949
`Declaration of Bill Lin, Ph.D.
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`perform other processing functions. When coupled to a processor, engineers will
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`often refer to this type of volatile memory coupled to the processor as “system
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`memory.”
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`43. Software code is typically packaged and stored in memory as a
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`software file or program called an “executable image” or “executable software
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`image.” The ’949 patent makes clear that executable software images were known
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`in the prior art, including “multi-segmented” images that included (1) one or more
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`headers, tables, or other structures that contain information about the overall image
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`and/or its underlying data, and (2) one or more segments containing code or other
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`data used by the image, which the patent refers to as “data segments.”1 Ex-1001,
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`2:14-16, 4:34-42.
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`2.
`Loading and Executing Multi-Segmented Software Images
`44. Before a processor can execute a multi-segmented software image, the
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`processor usually must load the image into its system memory, from where it is
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`then executed. Most multi-segmented executable software images are designed to
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`be loaded in multiple steps. In the first step, the processor reads information in the
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`one or more headers, tables, and/or other structures of the software image. That
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`1 References to “data” include code and/or data, and references to “data segment”
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`include segments containing code and/or data.
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`U.S. Patent No. 8,838,949
`Declaration of Bill Lin, Ph.D.
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`information might identify the type of image (e.g., an image format such as
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`Executable and Linking Format (ELF)), the size of the image, the number and size
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`of any data segments in the image, the storage locations of the data segments, and
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`the locations in system memory where the data segments are to be loaded for
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`execution. In one or more other steps, the processor uses that information to load
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`the data segments into memory and execute the image.
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`45. When transferred into memory, the data segments of a software image
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`can be stored either in contiguous (i.e., continuous) memory locations or spread
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`across non-contiguous (i.e., non-continuous) memory locations. “Scatter loading”
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`is a well-known loading process in which one or more portions of a software image
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`are loaded (or “scattered”) into memory. When there are multiple portions of a
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`software image, the portions are loaded across either contiguous or non-contiguous
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`locations in memory. Given this aspect of scatter loading, a mapping mechanism
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`is typically needed to allow a processor (or other component loading the code or
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`other data) to know the destination locations where the various parts of the image
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`are to be stored in memory. Many prior art executable software image formats
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`(such as ELF) were designed for scatter loading—by including information in the
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`image about where segments of the image should be loaded in memory for later
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`execution.
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`U.S. Patent No. 8,838,949
`Declaration of Bill Lin, Ph.D.
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`3.
`Sharing Memory in Multi-Processor Systems
`In order to reduce costs and space requirements in a multi-processor
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`46.
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`system, such as a mobile telephone having a baseband/modem processor and an
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`application processor, program code for both processors may be stored in a single
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`non-volatile memory. For example, the application processor may have direct
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`access to non-volatile memory that stores program code for both the application
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`processor and the baseband/modem processor. The application processor may also
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`have direct access to volatile memory for storing its program code after power up.
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`47. The baseband/modem processor, on the other hand, may have direct
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`access to only volatile memory and not non-volatile memory. Upon power up,
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`therefore, the application processor may have to transfer program code from non-
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`volatile memory to volatile memory so that the baseband/modem processor can use
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`it. The application processor can transfer the baseband/modem processor’s
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`program code from the non-volatile memory connected to the application
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`processor to the baseband/modem processor, which may then store the program
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`code in the volatile memory connected to the baseband/modem processor.
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`48. The transfer of the program code is typically performed by
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`transferring segments of code or other data over a bus, where it is then loaded into
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`memory. A large software image may be split into smaller data segments to
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`facilitate its transfer. In one embodiment, a separate header containing the
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`U.S. Patent No. 8,838,949
`Declaration of Bill Lin, Ph.D.
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`destination address for a data segment is transferred before each data segment. In
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`another embodiment, the destination addresses for all the data segments are
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`transferred before all the data segments. Each data segment is typically received
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`by a processor and stored in memory temporarily while the processor determines
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`the destination address where the data payload should be later stored in the same or
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`different memory. Thereafter, th