UNITED STATES INTERNATIONAL TRADE COMMISSION
`WASHINGTON,D.C. 20436
`
`In the Matter of
`
`
`
`
`
`CERTAIN MOBILE ELECTRONIC
`DEVICES AND RADIO FREQUENCY
`AND PROCESSING COMPONENTS
`THEREOF
`
`Inv. No. 337-TA-1065
`
`ORDERNO.28:
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`CONSTRUING TERMSOF THE ASSERTED PATENTS
`
`(March5, 2018)
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`The claim terms construed in this Order are done so for the purposesofthis Investigation.
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`Hereafter, discovery andbriefing in this Investigation shall be governed by the construction of
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`the claim termsin this Order. Those termsnotin dispute need not be construed. See Vanderlande
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`Indus. Nederland BV v. Int’! Trade Comm’n, 366 F.3d 1311, 1323 (Fed. Cir. 2004) (noting that
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`the administrative law judge need only construe disputed claim terms).
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`INTEL 1007
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`INTEL 1007
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`1
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`TABLE OF CONTENTS
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`Page
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`Introduction ........cccccccccccccescescesccsscescceseeseceecenecsecseesersececeseeseesseesesessessuseeceassesseseeeseeesareneenssenenes 1
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`Il.
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`— Relevant Law ......cccccccssccessscessecssnceessnecssececceecaeeeseeesseesssecssuceeseeceeesessseenseeesseeensesseseseeseenense2
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`IT.
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`The Asserted Patents ............:ceeeceesscceeseceereatesseessessneosseeeseneeaeeseeeeseeensnsecsnnecesnneneenaeecanasenen5
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`A.
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`B.
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`C.
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`D.
`E.
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`F,
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`U.S. Patent No. 8,698,558... cccccsssssnsnesceeceeeeeeseseesacnecaeeeescaseeseseseesessesssersneeeees 5
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`U.S. Patent No, 9,608,675..vssssssssssssssssssssssssssssesssassssstsssssssssesssinssessseesese
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`USS. Patent No. 8,838,949... ccccscsesecsscnessecsecssessceseceeeesecseessssssseasssessessesssesaseneenee6
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`US. Patent No. 8,633,936.......c:ccccccsscssccesecsrecsreceeessecsseessascsssesecesscssssesssssssessscsenenseeas6
`USS. Patent No. 9,535,490...cscsseeesserecssessssesessseeeneeeesstenteveeeeeenee7
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`Level of Ordinary Skill in the Art...ees seceesseeeseereecnseseseesseensesereesaeenseenees7
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`IV.
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`Construction of Disputed Claim Term..0.......ececceccsseesccsscsssseeseseeseeseessesneeneeesnserseeesnesaees9
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`A.
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`558 Patent .......cccsscccssccccssetccceseeerersecesseccesseeeessasecssssesseseseensaseeeeseeeeeeseeseenseeeesnaees 9
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`1.
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`2.
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`3.
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`“based ON” ....ccccseccsssecsetecescceseceeneesecesceeeseeceneecesseeessecesesesssseesesecsssersnseeeneees9
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`“current sense amplifier” .......0... seceseseueesseesueessessvesseee aceesseeeecereneees 11
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`“envelope Signal”oo... eceesseeesscesesscesssessessseseseeseeneseseecsasseeseeseeseesenees 13
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`B.
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`7675 Patent .......ccccccscccsssscessecesnccessceesecescersasesssesssacsssecssecesseeessssesnesesssesesaeeeeenessneeeaes 14
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`1.
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`“a plurality of carrier aggregated transmit signals being sent
`SimUItancOUSL]y”..........cceeceesecneceneeeeeeeecesecssscseusessesseesscesesenseesseenseeeneeeneeneees 14
`
`“powertracker” 0.0...eeesesvsnsnseceencnsnnaseceeconneasencnennarecenananscensnnnnnneety 18
`2.
`“single power tracking signal”......|eeeseeaceeseceaceececeseeeseeessenseesseoesseeseeseseeesns20
`3.
`°949 Patent ecscscsesssssssecsssnsseestvsseensssnststssesensssnsunsssassasssessaneaetnesinese,23
`
`C.
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`1.
`
`“means for receiving at a secondary processor, from a primary
`processorvia an inter-chip communication bus, an image header for
`an executable software image for the secondary processorthatis
`stored in memory coupledto the primary processor” (claim 16) ..............23
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`2
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`TABLE OF CONTENTS (CONT’D)
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`Page
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`2.
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`“meansfor receiving at the secondary processor, from the primary
`processor via the inter-chip communication bus, each data segment”
`CeaTT TG) seme serene axrcemen sesoreenconm aera noma eacinmsontena ss earurmeomtamemeamenirmnsiieesecens waxice27
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`D.
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`93.6 Patent occ-sceresscsssernnevenennesnsennseanennsoneenersennsnunennsonsoansenenonnnnn dla ce Tin ai sae 29
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`I
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`2.
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`“programmable streaming processor”(claims 1, 10, 19, 29,38,
`SNC 07) see sem arrose ctor eee os IRE TE eRTOT GN HSE29
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`. convert[] graphics
`.
`“(conversion/executable) instruction(s) [to] .
`data. .
`. [from a] (first/second/different) data precision [to a]...
`(second/first/indicated) data precision”(claims 1, 10, 19, 29, 38, 49,
`55, AN 67) wo.eececscesseesscssceesecetecsceeseesseceeeesseeseeesacessessesesessesensesssensesseeseeerens32
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`il
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`3
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`The following abbreviations may be used in this Order:
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`Declaration
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`EDIS
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`Initial Markman Brief
`IMB
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`PMB
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`Post-Markman “Bullet-Point” Brief
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`Electronic Document Imaging System
`
`Administrative Law Judge
`ALJ
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`
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` Complainants or Complainants’
`Compl.
`Decl.
`}
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`ee
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`ili
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`4
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`I.
`
`Introduction
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`By publication of a notice in the Federal Register on August 14, 2017, pursuant to
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`subsection (b) of section 337 of the Tariff Act of 1930, as amended, the Commissioninstituted
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`this investigation to determine:
`
`Pursuant to subsection (b) of section 337 of the Tariff Act of 1930, as
`amended, an investigation be instituted to determine whether there is a
`violation of subsection (a)(1)(B) of section 337 in the importation into the
`United States, the sale for importation, or the sale within the United States
`after importation of certain mobile electronic devices and radio frequency
`and processing components thereof by reason of infringement of one or
`more of claims 1-27, 29, 38, 49, 55-60, 67, and 68 of the °936 patent
`[U.S. Patent No. 8,633,936]; claims 1 and 6-20 of the *558 patent [U.S.
`Patent No. 8,698,558]; claims 9, 10, 12, 14, and 20-22 of the 658 patent
`[U.S. Patent No. 8,487,658]; claims 1-8, 10-14, 16, 20, and 22 of the °949
`patent [U.S. Patent No. 8,838,949]; claims 1-6, 8, 10, 16, 17, and 31 of the
`°490 patent [U.S. Patent No. 9,535,490]; and claims 1-3 and 7-14 ofthe
`°675 patent [U.S. Patent No. 9,608,675]; and whether an industry in the
`United States exists as required by subsection (a)(2) of section 337.
`
`82 Fed. Reg. 37899 (Aug. 14, 2017).
`
`Additionally, pursuant to Commission Rule 210.50(b)(1), the Commission ordered:
`
`the
`Pursuant to Commission Rule 210.50(b)(1), 19 CFR 210.50(b)(1),
`presiding Administrative Law Judge shall
`take evidence or other
`information and hear arguments from the parties or other interested
`persons with respect
`to the public interest
`in this investigation, as
`appropriate, and provide the Commission with findings of fact and a
`recommended determination on this issue, which shall be limited to the
`statutory public interest factors set forth in 19 U.S.C. 1337(d)(1), (DQ),
`(g)().
`
`Id.
`
`The complainantis Qualcomm Incorporated (“Qualcomm”) of San Diego, California.
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`The named respondent is Apple Inc. (“Apple”) of Cupertino, California. The Commission
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`Investigative Staff (“Staff”) is also a party to this investigation.Id.
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`5
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`

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`Qualcomm subsequently movedto terminate the °658 patent from the investigation based
`on withdrawal of allegations from the complaint. I granted the motion in an initial determination.
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`Order No. 6 (Aug. 30, 2017), aff'd, Notice of Comm’n Non-Review (Sept. 20, 2017).
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`The parties submitted a Joint Claim Construction Chart (EDIS Doc. No. 629504)
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`identifying claim terms that needed construction.' The parties subsequently submitted Initial and
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`Reply Claim Construction Briefs in which they narrowed the numberof claim termsto be
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`construction to ten. I held a one-day combined technologytutorial and Markman hearing on
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`January 23, 2018, and ordered the parties to submit Bullet-Point briefs the following week. See,
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`e.g., MarkmanTr. 1-305.
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`Qualcomm subsequently movedto terminate claims 9 and 10 of the °558 patent from the
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`investigation based on withdrawal ofallegations from the complaint. I granted the motion in an
`initial determination. Order No. 24 (Feb. 20, 2018). That initial determination remains pending
`before the Commission.
`.
`
`II. Relevant Law
`
`“An infringement analysis entails two steps. Thefirst step is determining the meaning
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`and scope ofthe patent claimsasserted to be infringed. The second step is comparing the
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`properly construed claimsto the device accused ofinfringing.” Markman v. Westview
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`Instruments, Inc., 52 F.3d 967, 976 (Fed. Cir. 1995) (en banc)(internal citations omitted), aff'd,
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`517 U.S. 370 (1996). Claim construction is a “matter of law exclusively for the court.” Jd. at
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`970-71. “The construction of claims is simply a way of elaborating the normally terse claim
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`' A copyofthe parties’ joint chart can be found at Exhibit JDX-1 to Qualcomm’s Initial Claim
`Construction Brief.
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`6
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`

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`language in order to understand and explain, but not to change, the scope of the claims.” Embrex,
`Inc. v. Ser Eng’g Corp., 216 F.3d 1343, 1347 (Fed. Cir. 2000).
`|
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`Claim construction focuses on the intrinsic evidence, which consists of the claims
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`themselves, the specification, and the prosecution history. See Phillips v. AWH Corp., 415 F.3d
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`1303, 1314 (Fed. Cir. 2005) (en banc); see also Markman, 52 F.3d at 979. As the Federal Circuit
`
`in Phillips explained, courts must analyze each of these components to determine the “ordinary
`and customary meaning of a claim term”as understood by a person ofordinaryskill in art at the |
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`time of the invention. 415 F.3d at 1313. “Suchintrinsic evidence is the most significant source of
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`the legally operative meaning of disputed claim language.” Bell Atl. Network Servs., Inc.v.
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`Covad Commc’ns Grp., Inc., 262 F.3d 1258, 1267 (Fed. Cir. 2001).
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`“It is a ‘bedrock principle’ of patent law that ‘the claimsof a patent define the invention
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`to which the patenteeis entitled the right to exclude.” Phillips, 415 F.3d at 1312 (quoting
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`Innova/Pure Water, Inc. v. Safari Water Filtration Sys., Inc., 381 F.3d 1111, 1115 (Fed. Cir.
`
`2004)). “Quite apart from the written description and the prosecution history, the claims
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`themselves provide substantial guidance as to the meaning of particular claims terms.”
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`Id. at 1314; see also Interactive Gift Express, Inc. v. Compuserve Inc., 256 F.3d 1323, 1331 (Fed.
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`Cir. 2001) (“In construing claims, the analytical focus must begin and remain centered on the
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`languageofthe claims themselves,forit is that languagethat the patentee choseto use to
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`‘particularly point[ ] out and distinctly claim [ ] the subject matter which the patentee regardsas
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`his invention.”). The context in which a term is used in an asserted claim can be “highly
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`instructive.” Phillips, 415 F.3d at 1314. Additionally, other claims in the samepatent, asserted or
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`unasserted, may also provide guidanceas to the meaning of a claim term. Jd.
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`7
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`

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`Thespecification “is always highly relevant to the claim construction analysis. Usuallyit
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`is dispositive;it is the single best guide to the meaning of a disputed term.”Phillips, 415 F.3dat
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`1315 (quoting Vitronics Corp. v. Conceptronic, Inc., 90 F.3d 1576, 1582 (Fed. Cir. 1996)).
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`“T]he specification may reveala special definition given to a claim term by the patentee that
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`‘differs from the meaning it would otherwise possess. In such cases, the inventor’s lexicography
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`governs.” Jd. at 1316.“In other cases, the specification may revealan intentional disclaimer, or
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`disavowal, of claim scope by the inventor.” Jd. As a general rule, however, the particular
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`examples or embodiments discussed in thespecification are not to be read into the claims as
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`limitations. Jd. at 1323. In the end,“[t]he construction that stays true to the claim language and
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`mostnaturally aligns with the patent’s description of the invention will be .
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`.
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`. the correct
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`construction.”Jd. at 1316 (quoting Renishaw PLC v. Marposs Societa’ per Azioni, 158 F.3d
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`1243, 1250 (Fed. Cir. 1998)).
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`In addition to the claims and the specification, the prosecution history should be
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`examined,if in evidence. Phillips, 415 F.3d at 1317; see also Liebel-Flarsheim Co. v. Medrad,
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`Inc., 358 F.3d 898, 913 (Fed. Cir. 2004). The prosecution history can “often inform the meaning
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`of the claim language by demonstrating how theinventor understoodthe invention and whether
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`the inventor limited the invention in the course of prosecution, making the claim scope narrower
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`than it would otherwise be.” Phillips, 415 F.3d at 1317; see also Chimie v. PPG Indus. Inc., 402
`F.3d 1371, 1384 (Fed. Cir. 2005) (“The purpose of consulting the prosecution history in
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`construing a claim is to exclude any interpretation that was disclaimed during prosecution.”).
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`Whenthe intrinsic evidence does not establish the meaning of a claim, then extrinsic
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`evidence(i.e., all evidence -externaltothe patent and the prosecutionhistory, including
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`dictionaries, inventor testimony, expert testimony, and learned treatises) may be considered.
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`4
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`8
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`Phillips, 415 F.3d at 1317. Extrinsic evidence is generally viewedaslessreliable than the patent
`itself and its prosecution history is determining how to defineclaim terms. Jd. at 1317. “The
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`court may receive extrinsic evidence to educateitself about the invention and the relevant
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`technology, but the court may notuse extrinsic evidenceto arrive at a claim construction that is
`clearly at odds with the construction mandatedbythe intrinsic evidence.” Elkay Mfg. Co. v. Ebco
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`Mfg. Co., 192 F.3d 973, 977 (Fed. Cir. 1999).
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`If, after a review ofthe intrinsic and extrinsic evidence, a claim term remains ambiguous,
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`the claim should be construed so as to maintain its validity. Phillips, 415 F.3d at 1327. Claims,
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`however, cannotbe judicially rewritten in orderto fulfill the axiom ofpreserving their validity.
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`See Rhine v. Casio, Inc., 183 F.3d 1342, 1345 (Fed. Cir. 1999). Thus, “if the only claim
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`construction that is consistent with the claim’s language and the written description renders the
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`claim invalid, then the axiom does not apply and the claim is simply invalid.” Id.
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`III.
`
`The Asserted Patents
`
`A.
`U.S. Patent No. 8,698,558
`Asserted U.S. Patent No. 8,698,558 is titled, “Low-Voltage Power-Efficient Envelope
`
`Tracker.” The ’558 patentissued on April 15, 2014, and the named inventors are Lennart K.
`
`Mathe, Thomas Domenick Marra, and Todd R. Sutton. Qualcomm asserts claims 1, 6-8, and
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`11-20 of the 558 patent. 82 Fed. Reg. 37899 (Aug. 14, 2017). Claims 1, 6, 8, 12, and 15 are
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`independentclaims. See °558 patent.”
`
`* A copy ofthe ’558 patent can be found at Exhibit JX-1 to Qualcomm’s Initial Claim
`Construction Brief. The °558 prosecution history can be found at Exhibit JX-6 to Qualcomm’s
`Initial Claim Construction Brief.
`
`9
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`

`

`B.
`U.S. Patent No. 9,608,675
`Asserted U.S. Patent No. 9, 608,675 is titled, “Power Tracker for Multiple Transmit
`
`Signals Sent Simultaneously.” The 675 patent issued on March 28, 2017, and the named
`
`inventor is Alexander Dorosenco. Qualcomm asserts claims 1-3 and 7-14 of the °675 patent. 82
`
`Fed. Reg. 37899 (Aug.14, 2017). Claim 1 is an independentclaim. See 675 patent.?
`
`Cc,
`
`US. Patent No. 8,838,949
`
`Asserted U.S. Patent No. 8,838,949 istitled, “Direct Scatter Loading of Executable
`
`Software Image From a Primary Processor to One or More Secondary Processor in a Multi-
`
`Processor System.” The ’949 patent issued on September 16, 2014, and the named inventorsare
`
`Nitin Gupta, Daniel H. Kim, Igor Malamant, and Steve Haehnichen. Qualcommasserts claims
`1-8, 10-14, 16, 20, and 2” ofthe ’949 patent. 82 Fed. Reg. 37899 (Aug. 14, 2017). Claims 1, 10,
`
`16, 20, and 21 are independentclaims. See 949 patent.’
`
`D.
`
`U.S. Patent No. 8,633,936
`
`Asserted U.S. Patent No. 8,663,936 istitled, “Programmable Streaming Processor With
`
`Mixed Precision Instruction Execution.” The ’936 patent issued on January 21, 2014, and the
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`named inventors are Yun Du, Chun Yu, Guofang Jiao, and Stephen Molloy. Qualcomm asserts
`
`3 A copy ofthe ’675 patent can be foundat Exhibit JX-2 to Qualcomm’s Initial Claim
`Construction Brief. The ’675 prosecution history can be found at Exhibit JX-7 to Qualcomm’s
`Initial Claim Construction Brief.
`* A copy ofthe °949 patent can be foundat Exhibit JX-4 to Qualcomm’s Initial Claim
`Construction Brief. The ’949 prosecution history can be found at Exhibit JX-9 to Qualcomm’s
`Initial Claim Construction Brief.
`
`10
`
`10
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`

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`claims 1-27, 29, 38, 49, 55-60, 67, and 68 of the ’936 patent. 82 Fed. Reg. 37899 (Aug.14,
`2017). Claims 1, 10, 19, 29, 38, 49, 55, and 67 are indlependdent claims. See °936 patent.”
`
`E.
`
`U.S. Patent No. 9,535,490
`
`Asserted U.S. Patent No. 9,535,490 istitled, “Power Saving Techniques in Computing
`
`Devices.” The °490 patent issued on January 3, 2017, and the named inventors are Vinod
`
`Harimohan Kaushik, Uppinder Singh Babbar, Andrei Danaila, Neven Klacar, Muralidhar
`
`Coimbatore Krishnamoorthy, Arunn Coimbatore Krishnamurthy, Vaibhav Kumar, Vanitha
`
`Aravamudhan Kumar, Shailesh Maheshwari, Alok Mitra, Roshan ThomasPius, and Hariharan
`
`Sukumar. Qualcommasserts claims 1-6, 8, 10, 16, 17, and 31 of the ’490 patent. 82 Fed. Reg.
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`37899 (Aug. 14, 2017). Claims 1, 16, and 31 are independent claims. See °490 patent.®
`
`F.
`
`Level of Ordinary Skill in the Art
`
`Apple addressed the level of ordinary skill in the art in its Ground Rule 7.5 Disclosure of
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`Invalidity Contentions on October23, 2017.’ In that disclosure, Apple proposedthat one of
`
`ordinaryskill in the art of the °936 patent would have had “a Master’s Degree in Electrical
`Engineering, Computer Engineering, or in Computer Science combined with at least 2 years of
`
`experience in processorarchitectureora relatedfield, or alternatively, a Bachelor’s Degree in
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`Electrical Engineering, Computer Engineering, or in Computer Science combined with atleast 4
`
`years of experience in processorarchitecture or a related field.” Jd. at 5. For the ’949 patent,
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`> A copyof the ’936 patent can be found at Exhibit JX-5 to Qualcomm’s Initial Claim
`Construction Brief. The 7936 prosecution history can be found at Exhibit JX-10 to Qualcomm’s
`Initial Claim Construction Brief.
`° A copyofthe °490 patent can be foundat Exhibit JX-3 to Qualcomm’s Initial Claim
`Construction Brief. The parties do not seek construction of terms from the °490 patent.
`7 Excerpts of Apple’s invalidity disclosure can be found at Exhibit SXM-004to the Staff’s Initial
`Claim Construction Brief.
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`11
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`11
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`

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`Apple proposedthat one having ordinary skill in the art would have had “a Master’s degree in
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`Computer Science or Computer Engineering with at least two years of experience in
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`multiprocessor systems, or a Bachelor’s degree in Computer Science or Computer Engineering
`
`with at least two to four years of experience in multiprocessor systems.” Jd. at 197. For the °490
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`patent, Apple proposed that one of ordinary skill in the art would have had “a Master’s degree in
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`Computer Science with at least two years of experience in multiprocessor systems and/or
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`interconnection networks, or a Bachelor’s degree in Computer Science with two to four years of
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`experience in multiprocessor systems and/or interconnection networks.” Jd. at 444. Apple’s
`invalidity disclosure did not address the level of ordinary skill for the °558 or °675 patent.
`
`In view of Apple’s proposals, I find that one of ordinary skill in the relevant art for each
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`of the asserted patents would have had a Master’s degree in Electrical Engineering, Computer
`
`Engineering, or Computer Scienceplusat least two years of relevant experience, or a Bachelor’s
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`degree in oneofthose fields plus at least four years of relevant experience. “Relevant
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`experience,”in the context of the asserted patents, refers to experience with mobile device
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`architecture as well as the following:
`
`e
`
`558 patent: transmission and powercircuitry for radio frequency devices. See
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`°558 patent at Abstract, 1:7-9, 30-31 (“Techniques for efficiently generating a
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`powersupply for a power amplifier and/or other circuits are described herein.”).
`
`e
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`’°675 patent: transmission and powercircuitry for radio frequency devices. See
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`°675 patent at Abstract, 1:8-10, 35-38 (“The present disclosure relates generally to
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`electronics, and more specifically to techniques for generating a power supply
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`voltage for a circuit such as an amplifier.”).
`
`12
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`12
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`

`

`e
`
`e
`
`°936 patent: graphics processing and processorarchitectures. See ’936 patent
`at Abstract, 1:7-8, 53-56 (“The disclosure relates to graphics proeesing and, more
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`particularly, to graphics processor architectures.”).
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`°949 patent: multi-processor systems. See ’490 patent at Abstract, 1:20-21,
`1:64-2:3 (“Aspects disclosed in the detailed description include power saving
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`techniques in computing devices. In particular, as data is received by a modem
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`processorin a computing device, the data is held until the expiration of a modem
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`timer. The data is then passed to an application processor in the computing device
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`over a peripheral componentinterconnect express (PCie) interconnectivity bus.”).
`
`e
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`°490 patent: multi-processor systems. See °490 patent at Abstract, 1:20-21,
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`1:64-2:3 (“Aspects disclosed in the detailed description include powersaving
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`techniques in computing devices. In particular, as data is received by a modem
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`processorin a computing device,the data is held until the expiration of a modem
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`timer. The data is then passed to an application processor in the computing device
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`over a peripheral componentinterconnect express (PCie) interconnectivity bus.”).
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`I reserve the right to amendthis determination in myfinalinitial determination if new,
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`persuasive information onthis issue is presented at the evidentiary hearing.
`
`IV.
`
`Construction of Disputed Claim Terms
`
`A.
`
`°558 Patent
`1.
`“based on”
`The term “based on” appearsin asserted claims 1, 6-8, 11-14, 16, and 18-19 ofthe °558
`patent. The parties agree that the term “based on” can begivenits plain and ordinary meaning for
`
`claims 6, 8, 12-14, 16, and 18-19. See Qualcomm PMBat 1; Apple PMBat 1; Staff PMBat 2.
`
`13
`
`13
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`

`

`°675 prosecution history (Notice of Allowance of Jan. 27, 2017) at QCAppleITC-00002751
`to -2754.In particular, the examiner stated: “Prior art ofrecord fails to disclose determining a
`single power tracking signal based on a plurality of inphase (I) and quadrature (Q) components
`ofa plurality ofcarrier aggregated transmit signals being sent simultaneously.”Jd. at
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`QCAppleITC-00002752.
`
`In view ofthe intrinsic evidence summarized above, the word “single,” as used in context
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`ofthe claim term at issue, indicates a singular value, i.e., only one in number. “Single”should
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`not be construed to include the use of multiple signals, such as two differential signals, as long as
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`the multiple signals are commonto multiple transmit signals.
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`Therefore, I construe the claim term “single power tracking signal” to mean “one (single-
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`ended) powertracking signal.”
`
`Cc.
`
`°949 Patent
`
`1.
`
`“means for receiving at a secondary processor, from a primary
`processorvia an inter-chip communication bus, an image headerfor
`an executable software image for the secondary processorthatis
`stored in memory coupled to the primary processor” (claim 16)
`
`The claim term “meansfor receiving at a secondary processor, from a primary processor
`
`via an inter-chip communication bus, an image header for an executable software image for the
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`secondary processorthat is stored in memory coupled to the primary processor”is recited in
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`asserted claim 16 of the °949 patent. The parties agree that this term is a means-plus-function
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`term subject to 35 U.S.C. § 112,para. 61°
`Construing a means-plus-function claim term is a two-step process. The first step is to
`identify the claimed function. The second step is to determine what structure disclosed in the
`
`'© The 949 patent is subject to the pre-America Invents Act version of 35 U.S.C. § 112. See
`America Invents Act, Pub. L. No. 112-29 § 4(c).
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`specification, if any, correspondsto the claimed function. Williamsonv. Citrix Online, LLC, 792
`F.3d 1339, 1351-52 (Fed. Cir. 2015). “Structure disclosed in the specification qualifies as
`
`‘correspondingstructure’ if the intrinsic evidence clearly links or associates that structure to the
`function recited in theclaim.” Id. at 1352. “While correspondingstructure need notincludeall
`
`things necessary to enable the claimed invention to work, it must includeall structure that
`
`actually performsthe recited function.” Default ProofCredit Card Sys., Inc. v. Home Depot
`
`U.S.A., Inc., 412 F.3d 1291, 1298 (Fed. Cir. 2005).
`
`Theparties’ positions with respect to this claim term are as follows:
`
`
`
`Complainant’s Construction|Respondent’s Construction Staff's Construction
`
`Function: receiving at a secondary processor, from a primary processor via an inter-chip
`communication bus, an image headerfor an executable software image for the secondary
`processorthat is stored in memory coupled to the primary processor
`
`column 5, lines 35-43, and shown in Figure 3
`
`Structure: a secondary processor connected to a primary
`Structure: a modem
`processor via an interface for a USB-based High Speed Inter-
`processor, or a controller in
`Chip (HSIC)bus, a MIPI High Speed SynchronousInterface
`the modem processor, and
`equivalents thereof (see 949|(HSI) bus, a Secure Digital I/O Interface (SDIO)bus,a
`Patent at 4:58-5:43, 5:59-6:39,|Universal Asynchronous Receiver/Transmitter (UART) bus, a
`7:60-10:44, 11:1-10, and Figs.|Serial Peripheral Interface (SPI) bus,or an Inter-Integrated
`1-3)
`Circuit (I2C) bus, and equivalents thereof, as described at
`
`All parties agree that the function performed by this claim elementis “receiving at a
`
`secondary processor, from a primary processor via an inter-chip communication bus, an image
`
`header for an executable software image for the secondary processorthat is stored in memory
`
`coupledto the primary processor.” Qualcomm proposesthat the corresponding structure
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`disclosed in the specification is “a modem processor,” ora controller in the modem processor,
`and equivalents ‘hereof? whereas Apple and the Stafftake the position that the corresponding
`
`structure is “a secondary processor connectedto a primary processor via [certain specific types
`
`of inter-chip communication buses] and equivalents thereof.” See Qualcomm PMBat17-19;
`Apple PMBat 16; StaffPMBat14.
`|
`The parties agree that the correspondingstructure includesat least a modem processoror
`secondary processor, but Apple and the Staffpropose that the corresponding structure should
`
`also include a primary processor and a businterface connecting the two processors. Qualcomm
`
`arguesthat including these additional items discounts the embodimentset forth in Figure 4,
`
`“which mirrors the recited function verbatim, and which states thatit is the secondary or modem
`
`processor that performs the claimed function.” See Qualcomm PMBat 18. Qualcomm cites to
`two excerpts from the specification in support ofits position:
`|
`[A] secondary processor receives, from a primary processor via an inter-
`chip communication bus, an image header for an executable software
`image for the secondary processor that is stored in memory coupledto the
`primary processor....
`
`[T]he secondary processor receives, from a primary processor via the
`inter-chip communication bus,the at least one data segment.
`
`°949 patent at 10:53-57; 10:62-65.
`Qualcomm’s argumentthat the comeaponding structure comprises only the secondary or
`
`modem processoris not persuasive, inasmuch as Qualcomm’s proposalfails to include all
`
`structure needed to perform the function agreed-to by the parties. The claim limitationat issue.
`
`recites a meansfor receiving an image header (1) at a secondary processor(2) from a primary
`
`'! The °949 specification uses the terms “secondary processor” and “modem processor”
`interchangeably. 949 patent at 6:65-66 (“The secondary processor (modem processor 210).”).
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`processor(3) via an inter-chip communication bus. Therefore,all three of these elements must be
`
`includedin the structure.
`
`With respect to the claimed inter-chip communication bus, the ’949 specification teaches:
`
`The inter-processor communication bus 134 may be, for example, a HSIC
`bus (USB-based High Speed Inter-Chip), an HSI bus (MIPI High Speed
`Synchronous Interface), a SDIO bus (Secure Digital I/O interface), a
`UART bus (Universal Asynchronous Receiver/Transmitter), an SPI bus
`(Serial Peripheral Interface), an I2C bus(Inter-Integrated Circuit), or any
`other hardware interface suitable for inter-chip communication available
`on both the modem processor 110 and the application processor 104.
`
`JX-004 (949 patent) at 5:35-43; see also id. Figs. 1, 3.
`
`This languageis “clearly link[ed]” to the claim 16 function “receiving at a secondary
`
`processor, from a primary processorvia an inter-chip communication bus.” This portion ofthe
`
`specification describes a “primary processor” (application processor 104), a “secondary
`processor” (modem processor 110), and an “inter-chip communication bus”(bus 134), all of
`which comprise the corresponding structure associated with the recited function. The teachings
`
`ofthe intrinsic evidence are thus reflected in the construction proposed by Apple and theStaff,
`
`but not in the construction proposed by Qualcomm.
`
`Therefore, I construe the claim 16 term “meansfor receiving at a secondary processor,
`from a primary processorvia an inter-chip communication bus, an image header for an
`executable software image for the secondary processorthat is stored in memory coupled to the
`
`primary processor” to be a means-plus-function term subject to 35 U.S.C. § 112,para. 6. The
`
`function performed bythis.claim element is “receiving at a secondary processor, from a primary
`
`processorvia an inter-chip communication bus, an image headerfor an executable software
`image for the secondary processorthatis stored in memory coupled to the primary processor.”
`
`The correspondingstructure disclosed in the specification is “a secondary processor connected to
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`a primary processorvia an interface for a USB-based High Speed Inter-Chip (HSIC)bus,a MIPI
`High Speed SynchronousInterface (HSI) bus, a Secure Digital I/O Tatenface (SDIO) bus, a
`Universal Asynchronous Receiver/Transmitter (UART) bus, a Serial Peripheral Interface (SPI)
`bus,or an Inter-Integrated Circuit (I2C) bus, and equivalents thereof.”
`De
`“means for receiving at the secondary processor, from the primary
`processorvia the inter-chip communication bus, each data segment”
`(claim 16)
`
`|
`
`The claim term “meansfor receiving at the secondary processor, from the primary
`
`processorvia the inter-chip communication bus, each data segment”is recited in asserted claim
`
`16 ofthe °949 patent. The parties agree that this term is a means-plus-function term subject to 35
`
`U.S.C. § 112, para.6.
`
`
`
`Complainant’s Construction|Respondent’s Construction Staff’s Construction
`
`Function:receiving at the secondary processor, from the primary processorvia the inter-chip
`communication bus, each data segment
`
`Structure: a secondary processor connected to a primary
`Structure: a modem
`processorvia an interface for a USB-based High SpeedInter-
`processor, or a controller in
`Chip (HSIC) bus, a MIPI High Speed SynchronousInterface
`the modem processor, and
`equivalents thereof (see 949_|(HSI) bus, a Secure Digital I/O Interface (SDIO) bus, a
`Patent at 4:58-5:43, 5:59-6:39,|Universal Asynchronous Receiver/Transmitter (UART) bus, a
`7:60-10:44, 11:1-10, and Figs.|Serial Peripheral Interface (SPI) bus, or an Inter-Integrated
`1-3)
`Circuit (I2C) bus, and equivalents thereof, as described at
`column5, lines 35-43, and shown in Figure 3
`
`
`
`The parties agree that the function performedbythis claim element is “receiving at the
`
`secondary processor, from the primary processorvia the inter-chip communication bus, each data
`
`segment.” As with the claim term discussed immediately above, the parties disagree as to the
`
`correspondingstructure. Qualcommproposesthat the corresponding structure disclosed in the
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`Zi
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`specification is “a modem processor, or a controller in the modem processor, and equivalents
`thereof,”whereas Apple andthe Stafftake the position that the corresponding structure is “a
`secondary processor connected to a primary processorvia [certain specific types ofinter-chip
`communication buses] and equivalents thereof.” See Apple PMB at 21; Staff PMBat 15.
`For the reasons discussed abovewith respect to “means for receiving at a secondary
`
`processor, from a primary processorvia an inter-chip communication bus, an image header for
`
`an executable software image for the secondary processorthat is stored in memory coupled to
`
`the primary processor,” I hereby construe the claim 16 term “meansfor receiving at the
`
`secondary processor, from the primary processor via the inter-chip communication bus, each data
`
`segment” to be a means-plus-function term subject to 35 U.S.C. § 112,para. 6.
`
`Also consistent with my reasons for “meansfor receiving at a secondary processor, from
`a primary processorvia an inter-chip communication bus, an image header for an executable
`
`software imagefor the secondary processor that is stored in memory coupled to the primary
`processor,” the function performed bythis claim elementis “receiving at the secondary
`processéf, from the primary processorvia the inter-chip communication bus, each data seg