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`UNITED STATES PATENT AND TRADEMARK OFFICE
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`INTEL CORPORATION,
`Petitioner
`
`v.
`
`QUALCOMM INCORPORATED,
`Patent Owner
`
`Patent No. 8,838,949
`
`
`
`
`Case IPR2018-01334
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`PATENT OWNER’S SUR-REPLY ON REMAND1
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`1 IPR2018-01335 and IPR2018-01336 have been consolidated with IPR2018-
`01334, and Patent Owner will file this brief only in IPR2018-01334. All citations
`are to IPR2018-01334 unless otherwise noted.
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`IPR2018-01334
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`TABLE OF CONTENTS
`LIST OF PATENT OWNER EXHIBITS ................................................................ ii
`I.
`INTEL’S CONSTRUCTION AND ARGUMENTS CONTRADICT
`THE INTRINSIC RECORD AND FEDERAL CIRCUIT OPINION ........... 1
`A.
`The Federal Circuit Did Not Reject The Board’s Construction .......... 1
`B.
`Intel’s Argument That The Hardware Buffer Can Be
`Implemented In System Memory Is Contrary To The Opinion ........... 2
`The Federal Circuit Found That The Hardware Buffer Provides
`Efficiency By Eliminating Extra Memory Copy Operations ............... 3
`The Federal Circuit Directed Evaluation Of Inventor Testimony ....... 5
`D.
`CLAIMS 1-9 AND 12 ARE NOT UNPATENTABLE ................................. 6
`A.
`The Board’s Finding That The ISA Is Temporary Is Dispositive ....... 6
`B.
`The ISA Formed In Internal System Memory Is The Exact
`Prior-Art Configuration Distinguished By The ’949 Patent ................ 7
`III. CONCLUSION ............................................................................................... 8
`
`C.
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`II.
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`
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`-i-
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`IPR2018-01334
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`LIST OF PATENT OWNER EXHIBITS
`Transcript of the Deposition of Dr. Bill Lin
`Ex. 2001
`Ex. 2002 U.S. Provisional Patent Application No. 61/324,122
`Ex. 2003 Qualcomm v. Apple, Case No. 3:17-CV-1375-DMS-MDD, S.D. Cal.,
`Transcript of Jury Trial, Day 2, Volume 2-A
`Ex. 2004 Qualcomm v. Apple, Case No. 3:17-CV-1375-DMS-MDD, S.D. Cal.,
`Transcript of Jury Trial, Day 2, Volume 2-B
`Ex. 2005 Qualcomm v. Apple, Case No. 3:17-CV-1375-DMS-MDD, S.D. Cal.,
`Transcript of Jury Trial, Day 6, Volume 6-B
`Ex. 2006 Qualcomm v. Apple, Case No. 3:17-CV-1375-DMS-MDD, S.D. Cal.,
`Transcript of Jury Trial, Day 7, Volume 7-A
`Ex. 2007 Declaration of Dr. Martin Rinard
`Ex. 2008
`Transcript of Second Deposition of Dr. Bill Lin
`Ex. 2009
`Patent Owner’s Demonstratives
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`Ex. 2010
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`Ex. 2011 Oxford University Press, “A Dictionary of Computing” (6th ed.)
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`Ex. 2012
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`Lin Deposition Transcript (May 5, 2022)
`
`“Computer Architecture—A Quantitative Approach” by John L.
`Hennessy and David A. Patterson (5th ed.)
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`Ex. 2013
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`Ex. 2014
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`FIFO Architecture, Functions, and Applications (Texas Instruments,
`1999)
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`“Computer Architecture—A Quantitative Approach” by John L.
`Hennessy and David A. Patterson (4th ed.)
`
`
`Ex. 2015 Remand Declaration of Dr. Martin Rinard
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`-ii-
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`IPR2018-01334
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`The Board should confirm the patentability of the challenged claims, as
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`explained in Qualcomm’s Response on Remand (Paper 37, “PO Resp. Br.”) and here.
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`I.
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`INTEL’S CONSTRUCTION AND ARGUMENTS CONTRADICT
`THE INTRINSIC RECORD AND FEDERAL CIRCUIT OPINION
`The intrinsic record supports Qualcomm’s construction. PO Resp. Br. at 3-8.
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`Intel’s construction and arguments are inconsistent with that record. Indeed, the
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`Federal Circuit opinion directly addressed the ’949 patent specification and claims,
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`providing significant guidance for this remand. Intel Corp. v. Qualcomm Inc., 21
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`F.4th 801, 811 (Fed. Cir. 2021) (hereinafter, the “Opinion”). Yet, Intel’s Reply
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`largely disregards the Federal Circuit’s opinion, or even argues contrary to it.
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`A. The Federal Circuit Did Not Reject The Board’s Construction
`Intel misreads the Opinion in saying it “rejected” the Board’s construction.
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`Pet. Reply at 1. The Court did not dispute the substance of the Board’s construction.
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`Rather, it found the Board “failed to tie its construction … to the actual invention
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`described in the specification”; “[w]hat is needed, then, is an analysis of the
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`specification ….” Opinion at 804, 810. The Court made clear it was not “suggesting
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`how, if at all, a proper construction will be substantively different” from the Board’s
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`negative construction excluding temporary buffers. Id. at 810 (emphasis added).
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`The Federal Circuit said that an analysis of the specification “seems likely to
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`support an affirmative construction in place of the Board’s purely negative one.”
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`Opinion at 812. To that end, Qualcomm has provided the analysis mandated by the
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`IPR2018-01334
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`Opinion (PO Resp. Br. at 3-13), yielding a positive construction consistent with the
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`Federal Circuit’s guidance. Intel, by contrast, disregards the Board’s previous
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`analysis and proposes a new construction significantly different from anything
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`considered before remand. This is wrong and unnecessary. The Court did not
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`dispute the substance of the Board’s construction, and hence there is no reason to
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`wipe the slate clean. The Board should bolster its analysis of the specification (as
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`instructed by the Court) and affirm the patentability of claims 1-9 and 12 for reasons
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`similar to those already provided in the Final Written Decision.
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`B.
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`Intel’s Argument That The Hardware Buffer Can Be
`Implemented In System Memory Is Contrary To The Opinion
`Intel argues that the “hardware buffer” can be implemented in system memory.
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`See, e.g., Pet. Reply at 2. This, too, is inconsistent with the Federal Circuit’s Opinion.
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`The Opinion states that “there must be some distinction between [the] two concepts”
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`of “hardware buffer” and “system memory.” Opinion at 810. The Opinion also
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`highlights “the distinctions between ‘system memory’ and ‘hardware buffer’ that are
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`drawn both in the claim language and in the specification.” Id. at 811. Intel’s
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`position cannot be reconciled with the Federal Circuit’s findings.
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`Intel argues that “since the ‘hardware buffer’ must be physically separate from
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`the claimed ‘system memory’” under its construction, there is no inconsistency with
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`the Opinion. Pet. Reply at 5 (emphasis added). But the Court never suggested that
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`physical separation from the claimed system memory is sufficient to constitute a
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`-2-
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`IPR2018-01334
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`hardware buffer. Rather, the Court found that “Qualcomm’s ‘hardware buffer’ is …
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`different from ‘system memory,’” and that there must be some distinction between
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`these “concepts,” recognizing that the hardware buffer cannot be located in any
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`system memory of the secondary processor.2 Opinion at 810-11. Intel’s reliance on
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`dicta from the Final Written Decision (Pet. Reply at 2, citing Paper 30 at 13) is
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`unavailing in view of the Federal Circuit’s subsequent findings. Further, the ’949
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`patent repeatedly distinguishes conventional techniques that use a buffer formed in
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`system memory. PO Resp. Br. at 3-13.
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`Intel rehashes its claim-differentiation argument in support of its position that
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`the hardware buffer can be located in system memory (Pet. Reply at 2-3), but
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`Qualcomm has already rebutted this. PO Resp. Br. at 10-11. Claims 1 and 2 have
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`different respective scopes, and the doctrine of claim differentiation therefore does
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`not support Intel’s position.
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`C. The Federal Circuit Found That The Hardware Buffer Provides
`Efficiency By Eliminating Extra Memory Copy Operations
`The Federal Circuit cited multiple portions of the ’949 patent’s specification
`
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`2 Intel argues that its construction creates a conceptual distinction between the
`hardware buffer and the claimed system memory because the “‘hardware buffer’
`does not perform the function of a memory into which the image is loaded and
`executed.” Pet. Reply at 6. But the same distinction existed between the prior-art
`temporary buffers and the final locations in system memory from which software
`images were executed. PO Resp. Br. at 3-8. As Qualcomm showed (see id.), Intel’s
`construction of “hardware buffer” reads on the prior-art temporary buffers and is
`wrong for at least this reason.
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`-3-
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`IPR2018-01334
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`that “support an understanding that use of a ‘hardware buffer’ relates to one of the
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`key claimed advances of the invention—the elimination of ‘extra memory copy
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`operations.’” Opinion at 811 (citing Ex. 1001 at 5:31-35, 7:16, 7:27-30, 9:42-46).
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`Intel ignores the Court’s finding and the specification’s disclosure. It argues
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`that extra memory copy operations are not eliminated in the invention of the ’949
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`patent because “[t]here is always an intermediate copying step as the executable
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`image moves from the primary processor to the hardware buffer, and then to the
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`claimed ‘system memory’….” Pet. Reply at 3. Even accepting arguendo Intel’s
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`view that copying is involved with the hardware buffer, that is immaterial. The
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`copying that the ’949 patent seeks to avoid is copying in system memory. PO Resp.
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`Br. at 3-8. The ’949 patent describes that these copy operations in system memory
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`result in reduced efficiency and increased boot times (see, e.g., Ex. 1001 at 7:16-30),
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`whereas the invention uses the hardware buffer to eliminate these copy operations
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`in system memory and provide “a more efficient direct loading process” (see, e.g.,
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`id. at 9:43-50). Ex. 2015 (Rinard Remand Decl.) at ¶¶ 23-34.
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`Notably, Intel does not challenge (much less rebut) Qualcomm’s showings
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`about the differences between system memory and the hardware buffer of the ’949
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`patent. Dr. Rinard provided detailed testimony, supported by documentary evidence
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`(id. at ¶¶ 6-15), that system memory is general-purpose and is not specifically
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`configured to buffer data in a multi-processor system. Id. at ¶¶ 25-26. He further
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`-4-
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`IPR2018-01334
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`explained that the ’949 patent’s hardware buffer is permanently assigned within the
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`structure of the hardware to perform the single task of loading data segments directly
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`to system memory. Id. at ¶¶ 31-34. All of this testimony stands unrebutted.
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`Rather than address Qualcomm’s showings head-on, Intel argues that “an
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`internal RAM (even if in system memory)” would buffer data “as quickly and
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`efficiently as … a permanent [hardware] buffer.” Pet. Reply at 4, 7. Therefore,
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`according to Intel, “the term ‘hardware buffer’ should not be construed to preclude
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`the use of such an internal RAM as a ‘hardware buffer,’ regardless of whether it
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`might be characterized as part of some system memory.” Id. at 4. But this is wrong
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`because the ’949 patent explicitly distinguishes prior-art approaches that use internal
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`RAM of system memory for buffering data in a multi-processor system. Ex. 1001
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`at 2:31-34 (describing prior-art approach in which “[t]he temporary buffer would be
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`some place in system memory, such as in internal random-access-memory
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`(RAM) ….”), 4:46-47 (“[T]he direct scatter load technique [of the invention] avoids
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`use of a temporary buffer.”). These portions make clear that the hardware buffer
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`cannot be located in internal RAM of system memory, and the alleged efficiency of
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`internal RAM therefore cannot transform it into a hardware buffer.
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`D. The Federal Circuit Directed Evaluation Of Inventor Testimony
`Intel criticizes Qualcomm’s citation to inventor testimony as “self-serving”
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`and “irrelevant.” Pet. Reply at 5, Ex. 1027 at ¶ 16. But the Federal Circuit directed
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`-5-
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`IPR2018-01334
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`the Board to consider this testimony—it “would benefit from attention on remand.”
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`Opinion at 812. The inventor testimony is relevant and evidences Qualcomm’s
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`desire to develop an efficient loading process that avoids “copying things around
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`memory” (Ex. 2003 at 216:16-21), consistent with the description of the ’949 patent.
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`II. CLAIMS 1-9 AND 12 ARE NOT UNPATENTABLE
`A. The Board’s Finding That The ISA Is Temporary Is Dispositive
`Under the correct construction of “hardware buffer” (i.e., “a permanent,
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`dedicated buffer that is distinct from system memory”), Intel’s patentability
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`challenges to claims 1-9 and 12 fail because the Board has already determined that
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`the intermediate storage area (ISA) of Svensson/Bauer is temporary, i.e., not
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`permanent. As Qualcomm explained (PO Resp. Br. at 3, 16), the Federal Circuit did
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`not disturb this finding that the ISA is temporary, and it should stand on remand.
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`Intel suggests this issue remains open, arguing that the Federal Circuit vacated
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`the Final Written Decision as to claims 1-9 and 12 and that Intel’s appeal challenged
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`the ISA as a temporary buffer. Pet. Reply at 8 (internal quotation omitted). But the
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`Federal Circuit vacated and remanded “for reconsideration of claim construction”
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`(Opinion at 812), not for the Board to reconsider its (correct) finding that
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`Svensson/Bauer’s ISA is a temporary buffer. As the Board explained, “Svensson
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`discloses that the intermediate storage area is reserved at runtime,” and “[t]hus, we
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`find that the intermediate storage area of Bauer and Svensson is a temporary buffer.”
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`-6-
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`IPR2018-01334
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`FWD at 56 (citing Ex. 1010 (Svensson) at 5:21-29; see also Paper 29 (Hearing Tr.)
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`at 19:19-25 (Intel agreeing that the ISA is reserved at runtime). The Board’s analysis
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`and findings are correct and consistent with Dr. Rinard’s testimony that the ISA is
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`temporary because “[i]t exists only after it is allocated by software at run time, and
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`therefore, it is not a permanent, fixed buffer.” Ex. 2015 at ¶ 65.
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`Intel raises its deallocation argument again (Pet. Reply at 7), but Qualcomm
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`has already rebutted this—the ISA of Svensson/Bauer is no different than the prior-
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`art temporary buffers described in the ’949 patent, which likewise makes no mention
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`of deallocation (PO Resp. Br. at 16-17)—and the Reply raises no new arguments on
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`this point. In any event, just because Svensson does not explicitly “describe[]”
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`deallocation of the ISA (Pet. Reply at 7), it does not follow that the ISA exists forever
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`(i.e., permanently). The ISA is allocated in the volatile DSP SARAM &
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`DARAM 108/208 and therefore will cease to exist at least when the multi-processor
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`system is powered down, if not sooner. It is not a permanent buffer.
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`B.
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`The ISA Formed In Internal System Memory Is The Exact Prior-
`Art Configuration Distinguished By The ’949 Patent
`Intel argues that because the ISA of Svensson/Bauer is formed in internal DSP
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`SARAM & DARAM 108/208, the ISA necessarily operates “as quickly and
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`efficiently as copying from a permanent buffer.” Pet. Reply at 7. This argument
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`amounts to mere speculation. Specifically, although Intel argues that internal
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`memory implemented as SRAM is “much faster” than DRAM (Ex. 1027 at ¶¶ 19,
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`-7-
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`IPR2018-01334
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`23), neither Svensson nor Bauer describes the DSP SARAM & DARAM 108/208 as
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`being SRAM. Likewise, Intel’s argument that cache memory is “typically
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`implemented using SRAM” and “function[s] at or near the speed of the CPU” (id.
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`at ¶¶ 22-24) is irrelevant to the Svensson/Bauer ground because these references do
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`not describe the memory 108/208 or its ISA as a cache. Any advantages of SRAM
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`or cache memory cannot be imputed to the ISA.
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`In any event, the alleged efficiency of the ISA is beside the point. The ISA is
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`indistinguishable from the prior-art temporary buffers formed in system memory.
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`Compare Ex. 1001 (’949 patent) at 2:23-34 (“[O]ne way of performing such loading
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`is to allocate a temporary buffer …. From the temporary buffer, … the payload
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`would get copied over to the final destination. The temporary buffer would be some
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`place in system memory, such as in internal random-access-memory (RAM) ….”)
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`to Ex. 1010 (Svensson) at 5:21-29 (“The idle process reserves a block of memory
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`in … ‘internal’ memory …. [T]his reserved block of memory is used for intermediate
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`storage of information (code and/or data) to be transferred to the slave-private
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`memory.”); see also PO Resp. Br. at 15-19. If the term “hardware buffer” could
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`encompass the ISA of Svensson/Bauer, then the claims would read on the prior-art
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`techniques distinguished throughout the ’949 patent. That cannot be correct.
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`III. CONCLUSION
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`The Board should hold that claims 1-9, 12, 16, and 17 are not unpatentable.
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`-8-
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`IPR2018-01334
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`Date: July 13, 2022
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`Respectfully submitted,
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`
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`By: /David B. Cochran/
`Joseph M. Sauer, Reg. No. 47,919
`David B. Cochran, Reg. No. 39,142
`David M. Maiorana, Reg. No. 41,449
`Matthew W. Johnson, Reg. No. 59,108
`Joshua R. Nightingale, Reg. No. 67,865
`JONES DAY
`North Point, 901 Lakeside Avenue
`Cleveland, OH 44114
`(216) 586-3939
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`-9-
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`IPR2018-01334
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`CERTIFICATE OF SERVICE
`
`The undersigned hereby certifies that the foregoing Patent Owner Sur-Reply
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`on Remand was served via email on the date below, upon the following:
`
`David L. Cavanaugh
`David.Cavanaugh@wilmerhale.com
`
`Thomas E. Anderson
`Tom.Anderson@wilmerhale.com
`
`Joseph H. Haag
`Joseph.Haag@wilmerhale.com
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`Dated: July 13, 2022
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`
`/Joshua R. Nightingale/
`Counsel for Patent Owner
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