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`571-272-7822
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`Paper 46
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` Date: September 2, 2022
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`__________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`__________
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`INTEL CORPORATION,
`Petitioner,
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`v.
`
`QUALCOMM INCORPORATED
`Patent Owner.
`__________
`
`IPR2018-01334
`Patent 8,838,949 B2
`__________
`
`Record of Oral Hearing
`Held: August 4, 2022
`__________
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`Before TREVOR M. JEFFERSON, DANIEL J. GALLIGAN, and
`AARON W. MOORE, Administrative Patent Judges.
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`571-272-7822
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`Paper 46
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` Date: September 2, 2022
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`__________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`__________
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`INTEL CORPORATION,
`Petitioner,
`
`v.
`
`QUALCOMM INCORPORATED
`Patent Owner.
`__________
`
`IPR2018-01334
`Patent 8,838,949 B2
`__________
`
`Record of Oral Hearing
`Held: August 4, 2022
`__________
`
`Before TREVOR M. JEFFERSON, DANIEL J. GALLIGAN, and
`AARON W. MOORE, Administrative Patent Judges.
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`IPR2018-01334
`Patent 8,838,949 B2
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`
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`APPEARANCES:
`
`ON BEHALF OF THE PETITIONER:
`
`
`JOSEPH HAAG, ESQ.
`Wilmer Cutler Pickering Hale & Dorr LLP
`2600 El Camino Real
`Suite 400
`Palo Alto, CA 94306
`joseph.haag@wilmerhale.com
`
`
`
`DAVID CAVANAUGH, ESQ.
`THOMAS ANDERSON, ESQ.
`Wilmer Cutler Pickering Hale & Dorr LLP
`1875 Pennsylvania Avenue NW
`Washington, DC 20006
`david.cavanaugh@wilmerhale.com
`tom.anderson@wilmerhale.com
`
`
`ON BEHALF OF THE PATENT OWNER:
`
`
`DAVID B. COCHRAN, ESQ.
`Jones Day
`901 Lakeside Avenue
`Cleveland, Ohio 44114
`dcochran@jonesday.com
`
`
`
`The above-entitled matter came on for hearing on Thursday,
`August 4, 2022, commencing at 1:00 p.m. EDT, via Video-Teleconference.
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`IPR2018-01334
`Patent 8,838,949 B2
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`P-R-O-C-E-E-D-I-N-G-S
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`(1:00 p.m.)
`
`JUDGE GALLIGAN: Good afternoon. This is an oral hearing for
`
`IPR2018-01334. The patent is US Patent 8,838,949 B2. The Petitioner is
`Intel Corporation. The Patent Owner is Qualcomm Corporation .
`
`This case is on remand from the Federal Circuit and that decision is
`at 21 F 4th 801. I'm Administrative Patent Judge Galligan. With me are
`APJs Jefferson and Moore.
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`May we have appearances, starting first with Petitioner, please? I
`think you're on mute.
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`UNKNOWN SPEAKER: Joe, I think you're on mute.
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`MR. HAAG: Thank you. Sorry about that. This is Joseph Haag for
`Petitioner Intel Corporation. With me is Tom Anderson and David
`Cavanaugh.
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`JUDGE GALLIGAN: Okay and thank you.
`
`And Patent Owner, please?
`
`MR. CAVANAUGH: Yeah. For the Patent Owner you have David
`Cochran from Jones Day, and I'm by myself today.
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`JUDGE GALLIGAN: Thanks. And Mr. Cochran, your microphone
`is a little low, so at least I'm hearing it a little faintly.
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`MR. CAVANAUGH: How does that sound? A little better?
`
`JUDGE GALLIGAN: That's perfect. That's perfect, thank you.
`Okay. Before we begin I just wanted to look at -- I think I missed -- I think I
`said it's Qualcomm Corporation. It's Qualcomm Incorporated. If I misspoke
`I apologize for the Patent Owner.
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`IPR2018-01334
`Patent 8,838,949 B2
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`As set forth in the oral hearing order in this case, each party has 60
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`minutes of oral argument time. Our first priority is your right to be heard, so
`if at any time during the hearing you encounter technical or other difficulties
`that you feel undermine your ability to adequately represent your client
`please let us know immediately.
`
`And you may do this by contacting the team who have provided you
`with the connection information. If you stop hearing and drop off, try to
`note what was being discussed so we can figure out where to pick up again.
`
`Please mute your mic and only unmute when speaking. And if
`you're on a speakerphone and a judge is asking you a question if you could
`just -- if you just mute while we're asking a question. Sometimes we get
`feedback.
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`Please identify yourself when you speak so that the transcript
`accurately reflects the speaker. When referring to an item in the record
`please do so with specificity so that the panel can follow along and for
`clarity in the transcript.
`
`And one last thing, there is a public line. I don't think there's
`anything confidential here but I wanted to remind the parties of that. And
`Petitioner you will proceed first. You have the burden on the -- of
`persuasion on the patentability issue. You have 60 minutes. Would you like
`to reserve any time for rebuttal?
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`MR. HAAG: Yes, Your Honor, if I could reserve 15 minutes,
`please?
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`JUDGE GALLIGAN: Okay. So I'll give you a heads up around
`then. Just keep a watch as well.
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`IPR2018-01334
`Patent 8,838,949 B2
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`And Patent Owner, you have an option for a surrebuttal if the
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`Petitioner has a rebuttal. And I'll ask you about that when your time starts.
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`With that, it is 1:03. Petitioner, you may begin.
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`MR. HAAG: Thank you, Your Honor. I'm Joseph Haag for
`Petitioner Intel Corporation. As I mentioned, I've got David Cavanaugh and
`Tom Anderson here with me today, and then on the public line I also have
`Brad Waugh and Matt Fagan from Intel Corporation.
`
`If we can turn to Petitioner's demonstrative Exhibit -- or Slide 5,
`Petitioner initially challenged many claims in the '949 patent. Many of these
`challenged claims have already been found unpatentable and those
`unpatentable claims do not remain at issue here.
`
`The only claims left in this IPR on remand are Claims 1 through 9,
`12 and 16 through 17, of which Claims 1 and 16 are the only independent
`claims.
`
`If we can turn to Slide 6, we see Claim 1 of the '949 patent here. The
`'949 patent describes a system and method to scatter load a software image
`from a primary processor to a secondary processor, and that is done without
`the entire software image from a buffer in the secondary processor, as the
`'949 patent describes at Column 9, Lines 42 to 56.
`
`The only issue on remand for Claim 1, you know, and the issues are
`the proper construction of hardware buffer, the meaning of system memory
`as it relates to the hardware buffer and the application of the hardware buffer
`to the prior art.
`
`I've highlighted some of the key language in Claim 1 here. In
`particular, there is a secondary processor that includes a system memory and
`a hardware buffer. And the system memory and hardware buffer must
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`IPR2018-01334
`Patent 8,838,949 B2
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`receive the image header in each data segment separately. And I've
`highlighted that language in gray here on the slide.
`
`And I emphasize that language because it's our position that that's the
`key asserted advance to the extent there is one of the '949 patent that is not
`the hardware buffer.
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`If we turn to Slide 7, we see here challenged Claim 16 with the two
`key limitations highlighted, at least partially highlighted, and those are the
`means for processing and the means for scatter loading terms.
`
`Petitioner identified the same structure for the means for processing
`and the means for scatter loading that the Patent Owner had identified in
`litigation in the ITC, and that's a modem processor coupled to a system
`memory.
`
`The issue on remand is to determine whether the Board can resolve
`the prior art challenge to the patentability of Claims 16 and 17 despite their
`potential indefiniteness of these two means-plus-function terms, or whether
`the terms are indefinite and it's logically impossible to adjudicate the prior
`art challenge on the merits. And that's the sole remaining issue for Claims
`16 and 17.
`
`If we could turn the Slide 9, I want to briefly discuss the Svensson
`prior art before I turn to the claim construction issue. Svensson discloses a
`technique for loading code and/or data from a memory associated with the
`host processor -- that's the non-volatile memory 106 shown in orange here
`on Slide 9 -- to a memory associated with a client processor in a multi-
`processor system.
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`IPR2018-01334
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`Svensson's secondary processor includes an intermediate storage
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`area or ISA, and that's what we've shown here highlighted in blue, and a
`DSP XRAM, 110, that's shown highlighted in a reddish color.
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`The ISA is part of an internal memory called the DSP SARAM and
`DARAM 108, and that's a separate memory from the external DSP XRAM
`110 that's highlighted in red.
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`The ISA is a hardware buffer that functions just like the hardware
`buffer in the '949 patent and the external DSP XRAM is a system memory
`that is just like the system memory in the '949 patent.
`
`The Bauer reference, as you know, contains a Figure 2 that is
`identical to Svensson's Figure 1 that we see here on Slide 9, but the
`numbering in Bauer's Figure 2 is slightly different. And Bauer has
`additional details on a file format that improves on Svensson's format.
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`Bauer and Svensson combined disclose that the secondary processor
`transfers the software image directly from the hardware buffer to the system
`memory for execution.
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`If I could turn now to Slide 0--
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`JUDGE MOORE: Mr. Haag?
`
`MR. HAAG: Yes.
`
`JUDGE MOORE: This is Judge Moore, just a quick question. In
`Svensson does the ARM CPU write directly to the internal storage area of
`the DSP or is there some sort of interface or controller in the DSP that data
`goes through?
`
`MR. HAAG: So I think it's a two-part answer. The ARM CPU --
`the memory 108, that internal memory 108 of the DSP is accessible by both
`the ARM side of the host and also by the DSP side, so both sides. So the
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`IPR2018-01334
`Patent 8,838,949 B2
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`ARM can access it, as can the DSP CPU on the client side. And there's also
`a DMA that's discussed in Svensson that can also access that internal
`memory 108.
`
`JUDGE MOORE: Okay, thank you.
`
`MR. HAAG: If we could turn to Slide 13, and I'm going to -- so the
`first issue on remand is the proper construction of hardware buffer and going
`along with this issue, as the Board mentioned in this order on remand, is the
`meaning of system memory as it relates to hardware buffer.
`
`If we could turn to Slide 15, here we see the parties' proposed
`constructions of hardware buffer, and I'm first going to go through
`Petitioner's construction and demonstrate how it is consistent with the
`guidance in the Federal Circuit's opinion for the term hardware buffer. And
`I'll then turn to the intrinsic evidence and then finally to Patent Owner's
`construction.
`
`First, Petitioner's construction specifies that the hardware buffer is
`more than just a buffer implemented in hardware as the Federal Circuit
`specified. In particular, the hardware buffer must be physically separate
`from the system memory.
`
`Second, Petitioner's construction is consistent with the Federal
`Circuit's guidance that there must be some distinction between the claimed
`hardware buffer and the claimed system memory. And in particular, the
`hardware buffer is physically separate from the claimed system memory in
`Petitioner's construction.
`
`And third, under Petitioner's construction, the executable software
`image may be moved directly from the hardware buffer to the final location
`in system memory from which it is executed, as the Federal Circuit noted,
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`IPR2018-01334
`Patent 8,838,949 B2
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`without copying in system memory locations. And I'll discuss these in more
`detail on the following slides.
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`If we could turn to Slide 16, this is just --
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`JUDGE MOORE: Mr. Haag?
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`MR. HAAG: Yes.
`
`JUDGE MOORE: Judge Moore again. What do you mean by
`physically separate? What does that mean? I mean, if two memory
`locations are right next to each other on the same media is that physically
`separate or is it -- I'm just not quite understanding what this separate means -
`-
`MR. HAAG: I think they have to --
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`JUDGE MOORE: -- in this phrase?
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`MR. HAAG: Sorry, Your Honor. Yeah, I think they have to be
`
`different memories. So the particular example, of course, I have in mind is
`Svensson where we know that we've got an internal memory internal to the
`DSP. That's 108. And we also have an external memory that's the DSP
`XRAM. Those are physically separate no matter how you look at it.
`
`And so that's what we mean by physically separate. You've got one
`memory that could be one chip that's separate from another chip. They're
`physically separate from one another.
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`JUDGE MOORE: Okay.
`
`MR. HAAG: If we could turn to Slide 16, the specification uses the
`term hardware buffer only twice, and the term is also used in Figure 3,
`which is described as an example. And based on the two specification
`excerpts we see here on Slide 16, it's only clear that first the hardware buffer
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`IPR2018-01334
`Patent 8,838,949 B2
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`is located on the secondary processor and that it receives at least a portion of
`an executable software image.
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`And second, and this is the part at 9, 37 to 41, that the hardware
`buffer is used to load the image into the system memory without the entire
`executable image being stored in the hardware buffer. There's no language
`there that restricts the location of the hardware buffer within the secondary
`processor.
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`Now, I emphasize this language at 9, 37 to 41 because it's the only
`time in the '949 specification that we see the hardware buffer, the term
`hardware buffer used in connection with some limiting language. And in
`particular, I've highlighted that limiting language here, "without an entire
`executable software image being stored in the hardware buffer."
`
`And so the idea is that the hardware buffer should not have the entire
`executable image stored in it as part of the loading process.
`Patent Owner argues that to create a distinction between the hardware buffer
`and system memory, as the Federal Circuit suggested, the hardware buffer
`cannot be allocated in any system memory. That restriction on the hardware
`buffer is not necessary.
`
`Petitioner's construction takes into account and creates a distinction
`between the hardware buffer and system memory and that the two are
`physically separate from each other. In Petitioner's construction the
`hardware buffer is distinct from the system memory in Claim 1.
`
`Now, Claim 1 separately recites a system memory but that recitation
`of a separate system memory by itself does not foreclose the possibility of
`implementing a hardware buffer in some other system.
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`If we can turn to Slide 18, and I want to --
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`IPR2018-01334
`Patent 8,838,949 B2
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`JUDGE MOORE: This is Judge Moore. So in your construction,
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`this is Judge Moore again, you would not have that hardware buffer be an
`area that is permanently dedicated for that buffering purpose?
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`MR. HAAG: If there is a -- the system memory into which the data
`is going to be loaded and executed, the hardware buffer could not be in that
`same system memory.
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`JUDGE MOORE: Okay. It's sort of a line drawing issue there,
`right? I mean, you could have one piece of media and you could have an
`area on that piece of media that is always used as a buffer. So then is that
`not physically separate? That would not fall under your construction?
`
`MR. HAAG: So I think there are two points of this, Your Honor.
`The first is that the hardware buffer needs to be physically separate from the
`claimed system memory. So you've got to have something that maps to the
`claimed system memory that's physically separate from the hardware buffer.
`That's the first point.
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`The second point is that that hardware buffer follows from the first.
`It can't be in that same physical system memory.
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`And I should say there's actually one more point to make here, which
`is that if you have some other system memory, not what's being mapped to
`the claimed system memory, but some other system memory, now it is
`possible that you could have a buffer in there that's a hardware buffer. That
`is possible.
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`So it's a different system memory from the claimed system memory.
`That's the point I'm making there.
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`JUDGE MOORE: Okay.
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`IPR2018-01334
`Patent 8,838,949 B2
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`MR. HAAG: If we can turn this Slide 18, I wanted to briefly address
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`the claimed system memory. The system memory is memory where
`executable software image can be loaded and executed. And that is, after
`all, the point of loading an executable software in the '949 patent is so that it
`can be executed from that system memory.
`
`This understanding of system memory is supported by both
`Petitioner's and Patent Owner's experts. And you can see here in the first
`quote, Dr. Bill Lin, that's Petitioner's expert, testified that system memory is
`"where programs could be routed and executed."
`
`And likewise, Dr. Rinard, that's Patent Owner's expert, testified that
`one thing about system memory is that it is where programs are loaded and
`executed.
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`Now, on the top of Page 5 of this response brief on remand, the
`Patent Owner agrees that, and this is a quote, the system memory is used for
`"various data and code storage tasks required to execute the software," end
`quote. That is correct and that's consistent with what we say system memory
`means.
`Now, I'm briefly going to turn to Slide 19, and as I stated earlier, it's
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`not necessary that the hardware buffer be separate from any system memory
`as the Patent Owner argues. Dependent Claim 2 requires loading of the
`executable image without copying data between memory locations on the --
`between system memory locations on the secondary processor
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`In Petitioner's construction of hardware buffer with this physical
`separateness from the claimed system memory allows for the possibility of
`copying directly to the system memory without copying between system
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`IPR2018-01334
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`memory locations. And that's consistent with the Federal Circuit's guidance
`in connection with Claim 2.
`
`Now, if we can turn to Slide 20, I did want to go over a number of
`places in the specification that have been pointed to by the Patent Owner as
`relating to restrictions on the hardware buffer. So the hardware, and again
`I'm on Slide 20, the specification does not limit where the hardware buffer
`can be aside from that it be in the secondary processor.
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`And to the extent the specification distinguishes any uses of buffers,
`it distinguishes the uses that I specify here on Slide 20, and I'm going to go
`through a few more slides on this that talk about the quotes from the patent
`as well. But the specification does not distinguish the use of temporary
`buffers per se or all uses of temporary buffers.
`
`First, the patent specifies that its more efficient loading process
`allows the loading of image segments without the entire executable software
`image being stored in the hardware buffer at once.
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`Second, Claim 1 requires the image header in each data segment
`being received separately rather than together. And that is also set forth in
`the specification, and as we can see that's the asserted advance of the '949
`patent.
`And then third, Claim 1 does not cover the hardware buffer being in
`
`the claimed system memory but instead the two are separate. The hardware
`buffer can be in some other system memory, however, that is separate from
`the claimed system memory.
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`If we --
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`JUDGE MOORE: Mr. Haag?
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`MR. HAAG: Yes.
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`IPR2018-01334
`Patent 8,838,949 B2
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`JUDGE MOORE: Thank you. Judge Moore again. Could you
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`explain to me how your construction accounts for the term hardware in the
`claim? How does hardware play into it? How is that accounted for in your
`construction?
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`MR. HAAG: Sure. So I think there are a couple of points to make
`on that. The first is that the Petitioner had originally advanced a plain
`meaning construction of hardware, the term hardware and hardware buffer.
`That did not prevail. And neither side is saying that you were giving
`hardware its plain and ordinary meeting. So but we need to give some
`meaning to hardware.
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`So the meaning given to hardware is that it's physically -- the
`hardware buffer is physically separate from the claimed system memory.
`There are separate pieces of hardware. That's the meaning given to the term
`hardware and hardware buffer in Petitioner's construction.
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`If we can turn back --
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`JUDGE GALLIGAN: Counsel, this is Judge Galligan. To follow up
`on Judge Moore's question, the Federal Circuit in its decision asked us to
`consider, the parties and us to consider how there might be a difference in
`hardware and software, for instance. And in terms of the hardware buffer or
`software buffer.
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`And can -- well, you read the decision, I just had it up, but Dr.
`Rinard has testimony in Paragraph 15 of his declaration where he explains
`there are, and he cites Exhibit 2013, there are instances of software buffers.
`They are flexible but they're maybe not as fast as a hardware buffer. And in
`a hardware buffer there are disadvantages.
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`So why shouldn't we look at this evidence and say, well, there's a
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`distinction there? And I don't want to do a negative construction
`necessarily, but if a hardware buffer is something different from a software
`buffer, first do you have evidence to -- that goes against the testimony in
`Paragraph 15 of Dr. Rinard's report?
`
`And also, is the intermediate storage area, the ISA of Svensson and
`Bauer, is that just a software buffer or is that different from what Dr. Rinard
`is describing as a software buffer?
`
`MR. HAAG: So let me, let me try to answer those questions. First
`is there any evidence against what Dr. Rinard had to say? And this relates to
`Patent Owner's argument that the '949 patent requires efficient scatter
`loading through a hardware buffer that's permanent and that is not allocated
`by software.
`
`But even if that efficiency is required, a permanent, dedicated buffer
`distinct from any system memory is not necessary to achieve that goal. And
`this is something that Dr. Lin addressed in his declaration as Exhibit 1027 at
`Paragraphs 18 to 26.
`
`And as Petitioner's expert explained, and again this is in Exhibit
`1027, if anything it's the separation between the hardware buffer and the
`claimed system memory that allows for this efficiency in moving data
`segments from the hardware buffer to the system memory.
`
`Now, system memory is usually, and this again, the point that Dr.
`Rinard was making and the Patent Owner made related to the efficiency.
`They're saying it's more efficient if it's dedicated and it's not a temporary
`buffer or allocated by software.
`
`
`
`15
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`IPR2018-01334
`Patent 8,838,949 B2
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`But the point that we're making and the point that Dr. Lin made in
`
`his declaration is that RAM internal to a processor chip works at or near the
`speed of the processor so it would be faster than external DRAM. And
`external DRAM is typically slow. And that means that if you have a buffer
`or a hardware buffer in internal RAM, copying data segments from that
`internal RAM to the external DRAM would, like the use of the permanent
`buffer that Patent Owner describes, be faster and be more efficient, just like
`what Patent Owner describes.
`
`So there's no getting an efficiency of the type that Dr. Rinard and
`Patent Owner describes, and that's the point that Professor Lin was making
`in his declaration.
`
`Now, and then you asked a question about the intermediate storage
`area in Svensson, but I forgot what that was. If you could remind me what
`your question was there?
`
`JUDGE GALLIGAN: Yeah, I was just wondering if the
`intermediate storage area in Svensson would be a soft -- I mean, you say it's
`a hardware buffer and I take that. Would it -- is it the kind of software
`buffer, though, that Dr. Rinard is describing in Paragraph 15? And I don't
`mean for you to guess at what Dr. Rinard is saying. I'm saying given his
`testimony the difference between a hardware buffer and software buffer,
`would the ISA, which is allocated at runtime or when the slave is -- when
`the secondary processor boots up, is that a software buffer as the evidence in
`Exhibit 2013 would indicate?
`
`MR. HAAG: So I'm having a little bit of a hard time saying that it is
`a software buffer. I mean, there is not --
`
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`JUDGE GALLIGAN: And I put you -- this is Judge Galligan -- I
`
`put you in a bad position there. I'm just trying to figure out if there's a, you
`know, if -- I'm trying to tease out the distinction there --
`
`MR. HAAG: Sure.
`
`JUDGE GALLIGAN: -- between software buffer and hardware
`buffer and that's, kind of, what I'm getting at. So I guess from your
`perspective what would you say to say the intermediate storage area, ISA, of
`Svensson and Bauer is not a software buffer? How about that?
`
`MR. HAAG: So without question the intermediate storage area of
`Svensson is allocated at runtime. And that's described in Svensson. That's a
`point that Patent Owner made. That's a point that we agree with.
`
`Now, it happens to be permanently allocated so it is a piece of
`hardware that is permanently allocated for serving that one purpose. And
`there's also in Svensson at Column 8, Lines 29 through 32 it talks about the
`use of the loading system virtually anytime the processor is running.
`
`And so the point I'm making is that ISA is a permanent buffer.
`Whether you call it software or not it is a permanent buffer and it is a
`hardware buffer.
`
`JUDGE GALLIGAN: Sorry, and just -- this is Judge Galligan. You
`cited Column 8. Was it 29 to 32?
`
`MR. HAAG: Correct.
`
`JUDGE GALLIGAN: Okay. Oh, I see. It's the passage saying that
`"with the OS friendly bootloader described here one can load and execute
`new software in the slave processor virtually anytime the host processor is
`running." That one?
`
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`MR. HAAG: Yes. And the point we're making about that is that
`
`once that ISA is allocated it's never described as being deallocated, and it
`can be used for the loading process anytime the processor is running. That
`makes it a permanent buffer, the permanent part of our buffer.
`
`JUDGE GALLIGAN: Thanks, because that's another question I had.
`And I think Patent Owner disputed whether it was allocated or deallocated,
`but you're saying this passage here would indicate that once the ISA is
`allocated it exists or it remains allocated for the primary processor to push
`data to it throughout the lifecycle or throughout the runtime of the device is
`what you're saying, well, while the device is powered on?
`
`MR. HAAG: That is what we're saying and that once data gets into
`that ISA it can then be loaded to the DSP XRAM. And that's anytime the
`processor is running. And so it's the combination of that statement at
`Column 8, Lines 29 through 32 and the fact that there is no mention of the
`ISA either being temporary or being deallocated in Svensson or Bauer. It's
`those things that make it a permanent buffer.
`
`JUDGE GALLIGAN: Thanks. And this is Judge Galligan
`following up. Does Dr. Lin's testimony on the D -- I don't -- I read it, I don't
`recall seeing if either of them may have testimony that it's not deallocated?
`
`MR. HAAG: He does have testimony on that.
`
`JUDGE GALLIGAN: Okay.
`
`MR. HAAG: And I can --
`
`JUDGE GALLIGAN: If you could just point me to that I'd
`appreciate it. Thank you.
`
`MR. HAAG: Yeah. I mean, he does have testimony on that in
`Exhibits 1026 and 1027. And I can try to find that for you.
`
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`JUDGE GALLIGAN: You don't have to use your time here. If you
`
`want to bring it up in your rebuttal you can do that or have one of your
`colleagues --
`
`MR. HAAG: Okay.
`
`JUDGE GALLIGAN: -- look it up.
`
`MR. HAAG: Okay.
`
`JUDGE GALLIGAN: Thank you so much.
`
`MR. HAAG: Okay. Thank you, Your Honor. So if we can go back
`to Slide 22, I was going over passages from the specification and what, if
`anything, they distinguish relating to temporary buffers. And so again, I'm
`on Slide 22.
`
`First, some of the statements that were mentioned by the Patent
`Owner distinguish the claimed invention from prior art techniques that
`transfer the entire software image to a temporary buffer. And we see those
`statements here.
`
`And it's clear from the excerpted passages that what's being excluded
`is not temporary buffers per se. It's not all uses of temporary buffers. But
`instead, as an example in the second excerpt from Column 9, Lines 42 to 46,
`conventional techniques employing a temporary buffer for the entire image.
`
`And the first excerpt at 9, 37 to 41, says the same thing, that the
`loading takes place without an executable software image being stored in the
`hardware buffer.
`
`And the third excerpt, again, is consistent with that. So again, the
`point is that these are not distinguishing all uses of a hardware or a
`temporary buffer but instead only when that temporary buffer stores the
`entire executable image.
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`If we turn to Slide 23, the second distinction in the specification is
`
`somewhat similar to the first and it's reflected in the claim language itself.
`And I mentioned this a few moments ago, that Claim 1 requires the image
`header in each data segment being received separately rather than together.
`
`At Column 2, Line 16 in the background shown here, the patent
`mentions how the software image may include a header followed by
`multiple segments of code.
`
`And at 2, 25 to 28 the second quote we see here, the background
`mentions a temporary buffer into which each packet is received where each
`packet would have an associated packet header along with the payload.
`
`And the same applies to the '949 patent at 2, 45 to 54 where it refers
`to a packet header included in each packet communicated into the secondary
`processor and that the received packets are, again, processed to determine
`where to store the data.
`
`And again, the point I'm making is that the claim language requires a
`separate receipt of the image header in each data segment. And so to the
`extent that these portions of the specification are distinguishing anything it's
`the particular use of the temporary buffer that receives data segments with a
`header or receives them together.
`
`If we can turn to Slide 24, the Patent Owner cites Column 4, Lines
`43 to 47 from the specification and stating that the hardware buffer
`eliminates the intermediate step of buffering and uses -- and the use of a
`temporary buffer per se. This part of the specification needs to be read in
`light of the surrounding context. And if you do that, you'll notice two
`things.
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`IPR2018-01334
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`First, Column 4, Lines 43 to 47 at the top corner of Slide 24 begins
`
`with "in one exemplary aspect." That is it is not intended to be limiting.
`
`And second, immediately after discussing avoiding a temporary
`buffer it goes on to explain this and it uses the term "for instance."
`
`And the second quote here on Slide 24 shows that sentence, for
`instance, in one aspect rather than employing a packet-based communication
`in which the image is communicated
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