Intel Corporation
`v.
`Qualcomm Incorporated
`IPR2018-01334
`U.S. Patent No. 8,838,949
`
`Patent Owner’s Demonstrative Exhibits
`
`1
`
`
`v.
`Qualcomm Incorporated
`IPR2018-01334
`U.S. Patent No. 8,838,949
`
`Patent Owner’s Demonstrative Exhibits
`
`1
`
`
`
`U.S. Patent No. 8,838,949
`
`U.S. Patent No. 8,838,949
`Sep. 16, 2014
`
`US 8,838,949 B2
`ao) Patent No:
`a2) United States Patent
`(45) Date of Patent:
`Guptaet al.
`
`
`(54) DIRECT SCATTER LOADING OF
`(58)
`Field of
`
`
`EXECUTABLE SOFTWARE IMAGE FROM A
`CPC .....
`
`
`USPC .|
`Zera Copy Transport Flow
`PRIMARY PROCESSOR TO ONE OR MORE
`
`
`See app!
`SECONDARY PROCESSORIN A
`SECONDARY PROCESSOR
`PRIMARY PROCESSOR
`MULTI-PROCESSOR SYSTEM
`
`
`
`(75)
`Inventors: Nitin Gupta, San Diego, CA (US):
`66)
`Hardware Transport
`Daniel H. Kim, San Diego, CA (US);
`Meeopen ‘,
`Igor Malamant, San Diego, CA (US);
`(ie.
`USB
`Host}
`
`Steve Haehnichen, San Diego. CA (US)
`
`(73) Assignee: QUALCOMM Incorporated, San
`Diego, CA (US)
`
`
`307
`|
`System Memory a
`Data
`Segment 4
`
`5,978,589
`6,079,017
`
`7,447,846
`
`
`
`
`
`
`Mare
`Header
`
`Nont-veintile
`Memory
`
`ImageHeader
`Data
`Dats
`Scement 2
`ale
`Segment 3
`Dabs
`Seament 4
`Data
`Scement 3
`
`cPu
`
`2
`
`PO
`
`Ex. 1001, Fig. 3
`
`
`
`The Prior Art Used a Temporary Intermediate RAM
`Buffer at the Secondary Processor
`
`3
`
`Ex. 1001, 2:24-42 (emphasis added)
`
`
`
`The ‘949 Invention Eliminated
`the Temporary Intermediate RAM Buffer
`
`4
`
`Ex. 1001, 7:15-30; Fig. 3 (emphasis added)
`
`
`
`The ‘949 Invention Uses an Image Header
`Instead of Segment Headers
`
`5
`
`Ex. 1001, 7:39-50; 8:17-24; 10:3-14;
`Fig. 3 (emphasis added)
`
`
`
`Benefits of the ‘949 Zero Copy Approach Over the
`Use of a Temporary Intermediate RAM Buffer
`
`6
`
`Ex. 1001, Fig. 3; Ex. 1010, Fig. 1
`
`
`
`Consolidated Grounds
`
`•
`
`•
`•
`
`•
`
`Ground I (IPR2018-01334): Claims 1-9, 22, and 23 as obvious over Bauer, Svensson,
`and Kim
`Ground I (IPR2018-01335): Claims 10-15 as obvious over Bauer, Svensson, and Kim
`Ground II (IPR2018-01335): Claims 16 and 17 as obvious over Bauer, Svensson, Kim,
`and Zhao
`Ground I (IPR2018-01336): Claims 18-21 as obvious over Bauer, Svensson, Kim, and
`Lim
`
`7
`
`IPR2018-01334, Paper 3 at ii;
`IPR2018-01335, Paper 3 at ii-iii;
`IPR2018-01336, Paper 3 at ii.
`
`
`
`Patentability
`
`1) The Reference Combinations Do Not Load Each Received Data
`Segment Directly to System Memory
`2) The Reference Combinations Do Not Receive the Image Header and
`Each Data Segment Separately
`3) The Reference Combinations Do Not Teach Scatter Loading
`
`8
`
`Paper 16 at 50-71;
`Paper 25 at 17-35
`
`
`
`Patentability
`
`1) The Reference Combinations Do Not Load Each Received Data
`Segment Directly to System Memory
`2) The Reference Combinations Do Not Receive the Image Header and
`Each Data Segment Separately
`3) The Reference Combinations Do Not Teach Scatter Loading
`
`9
`
`Paper 16 at 50-58;
`Paper 25 at 17-26
`
`
`
`’949 Patent – Claim 1
`1. A multi-processor system comprising:
`a secondary processor comprising:
`system memory and a hardware buffer for receiving an
`image header and at least one data segment of an
`executable software image, the image header and each data
`segment being received separately, and
`a scatter loader controller configured:
`to load the image header; and
`to scatter load each received data segment based at least in
`part on the loaded image header, directly from the
`hardware buffer to the system memory;
`a primary processor coupled with a memory, the memory
`storing the executable software image for the secondary
`processor; and
`an interface communicatively coupling the primary processor
`and the secondary processor, the executable software image
`being received by the secondary processor via the interface.
`10
`
`Ex. 1001, Fig. 3; 12:60-13:10 (emphasis added)
`
`
`
`’949 Patent – Claim 10
`10. A method comprising:
`receiving at a secondary processor, from a primary processor
`via an inter-chip communication bus, an image header for an
`executable software image for the secondary processor that is
`stored in memory coupled to the primary processor, the
`executable software image comprising the image header and
`at least one data segment, the image header and each data
`segment being received separately;
`processing, by the secondary processor, the image header to
`determine at least one location within system memory to
`which the secondary processor is coupled to store each data
`segment;
`receiving at the secondary processor, from the primary
`processor via the inter-chip communication bus, each data
`segment; and
`scatter loading, by the secondary processor, each data segment
`[directly] to the determined at least one location within the
`system memory, and each data segment being scatter loaded
`based at least in part on the processed image header.
`11
`
`Ex. 1001, Fig. 3; 13:47-67 (emphasis added)
`
`
`
`’949 Patent – Claim 16
`16. An apparatus comprising:
`means for receiving at a secondary processor, from a primary
`processor via an inter-chip communication bus, an image
`header for an executable software image for the secondary
`processor that is stored in memory coupled to the primary
`processor, the executable software image comprising the
`image header and at least one data segment, the image header
`and each data segment being received separately;
`means for processing, by the secondary processor, the image
`header to determine at least one location within system
`memory to which the secondary processor is coupled to store
`each data segment;
`means for receiving at the secondary processor, from the
`primary processor via the inter-chip communication bus, each
`data segment; and
`means for scatter loading, by the secondary processor, each data
`segment directly to the determined at least one location within
`the system memory, and each data segment being scatter
`loaded based at least in part on the processed image header.
`12
`Ex. 1001, Fig. 3; 14:17-37 (emphasis added)
`
`
`
`’949 Patent – Claim 18
`18. A multi-processor system comprising:
`a primary processor coupled with a first non-volatile memory,
`the first non-volatile memory coupled to the primary
`processor and storing a file system for the primary processor
`and executable images for the primary processor and
`secondary processor;
`a secondary processor coupled with a second non-volatile
`memory, the secondary non-volatile memory coupled to the
`secondary processor and storing configuration parameters and
`file system for the secondary processor; and
`an interface communicatively coupling the primary processor
`and the secondary processor, an executable software image
`being received by the secondary processor via the interface,
`the executable software image comprising an image header
`and at least one data segment, the image header and each data
`segment being received separately, and the image header
`being used to scatter load each received data segment directly
`to a system memory of the secondary processor.
`
`13
`
`Ex. 1001, Fig. 3; 14:43-62 (emphasis added)
`
`
`
`’949 Patent – Claim 20
`20. A multi-processor system comprising:
`a primary processor coupled with a first non-volatile memory,
`the first non-volatile memory coupled to the primary
`processor and storing executable images and file systems for
`the primary and secondary processors;
`a secondary processor not directly coupled to the first non-
`volatile memory; and
`an interface communicatively coupling the primary processor
`and the secondary processor, an executable software image
`being [] received by the secondary processor via the interface,
`the executable software image comprising an image header
`and at least one data segment, the image header and each data
`segment being received separately, and the image header
`being used to scatter load each received data segment directly
`to a system memory of the secondary processor.
`
`14
`
`Ex. 1001, Fig. 3; 15:1-17 (emphasis added)
`
`
`
`’949 Patent – Claim 22
`22. A method comprising:
`sending, from a memory coupled to a primary processor, an
`executable software image for a secondary processor, via an
`interface communicatively coupling the primary processor
`and secondary processor, the executable software image
`comprising an image header and at least one data segment;
`receiving, at the secondary processor, the image header and
`each data segment of the executable software image, the
`image header and each data segment being received
`separately, and the image header being used to scatter load
`each received data segment directly to a system memory of
`the secondary processor; and
`executing, at the secondary processor, the executable software
`image.
`
`15
`
`Ex. 1001, Fig. 3; 16:1-15 (emphasis added)
`
`
`
`Loading Directly to System Memory
`
`16
`
`Ex. 1001, Fig. 3; 9:42-56 (emphasis added)
`
`
`
`Claim Construction – “System Memory”
`
`Patent Owner’s Proposed Construction:
`“memory that is addressable by the
`secondary processor”
`
`Petitioner’s Proposed Construction:
`“memory where an executable
`software image can be loaded and
`executed”
`
`Paper 16 at 9-12;
`Paper 21 at 6.
`
`17
`
`Ex. 1001, Fig. 3 (emphasis added)
`
`
`
`Claim Construction – “System Memory”
`
`Ex. 1001 at 2:12-34,
`cited by Paper 16 at 9.
`
`Ex. 1001 at 2:61-63; 5:48-51; 8:18-21; 9:37-41;
`cited by Paper 21 at pp. 5-6
`
`18
`
`
`
`Claim Construction – “System Memory”
`
`“[S]ystem memory… is the place where you load and run
`programs or where programs can be loaded and executed.”
`
`Ex. 2001 (Deposition of Dr. Lin) at 24:17-21.
`
`“[S]ystem memory is a type of memory that the
`processor needs to have the program loaded into in order
`for it to run.”
`
`Ex. 2005 (Dist. Ct. testimony of Dr. Lin) at 1162-1163.
`
`19
`
`
`
`Claim Construction – “Hardware Buffer”
`
`Patent Owner’s Proposed Construction:
`“a buffer within a hardware transport
`mechanism that receives data sent from
`the primary processor to the secondary
`processor”
`
`Petitioner’s Proposed Construction:
`“a buffer implemented in hardware”
`
`Patent Owner’s Alternate Construction:
`“a buffer that is not allocated by the
`secondary processor”
`
`Paper 16 at 14-15;
`Paper 21 at 8;
`Paper 25 at 11-13.
`
`20
`
`Ex. 1001, Fig. 3 (emphasis added)
`
`
`
`Claim Construction – “Hardware Buffer”
`
`Petitioner’s Proposed
`Construction: “a buffer
`implemented in hardware”
`
`Paper 21 at 8.
`
`is it possible to implement a buffer
`Q. Dr. Lin,
`without some type of physical storage medium?
`
`A. No.
`
`Ex. 2008 (Deposition of Dr. Lin), p. 41
`
`Q. Column 2, Lines 31 through 34 of the ‘949 patent
`states that “The temporary buffer would be someplace
`in the system memory such as in internal random
`access memory (RAM) or double data rate (DDR)
`memory, for example. Do you see that?
`
`A. Yes… I can agree that is a temporary buffer is
`implemented using random access memory, that is in
`hardware… [I]f the temporary buffer is implemented
`[in] double data rate memory I can agree that it is
`implemented in hardware.
`
`21
`
`Ex. 2008 (Deposition of Dr. Lin), p. 17
`
`
`
`Claim Construction – “Hardware Buffer”
`
`Patent Owner’s Proposed
`Construction: “a buffer
`within a hardware transport
`mechanism that receives
`data sent from the primary
`processor to the secondary
`processor”
`
`Patent Owner’s Alternate
`Construction: “a buffer
`that is not allocated by the
`secondary processor”
`
`Paper 16 at 14-15;
`Paper 25 at 11-13.
`
`Ex. 1001, 9:42-56 (emphasis added)
`
`22
`
`
`
`Petitioner’s Interpretation of Bauer/Svensson
`
`23
`
`IPR2018-01334, Paper 3 at 45;
`Paper 16 at 52-53.
`
`
`
`Svensson Uses a Temporary System Buffer
`
`24
`
`Paper 25 at 17.
`
`
`
`Svensson Uses a Temporary System Buffer
`
`Q. Dr. Lin, do you agree that in Svensson, code is
`loaded into the memories 108 and executed from
`the memories 108?
`..
`A. Yes, a portion of 108 could be used to load and
`execute programs.
`
`Ex. 2008 (Deposition of Dr. Lin), p. 53
`
`139. .. In the combination of Bauer and Svensson,
`the system memory includes both (i) the DSP
`XRAM, and (ii) the DSP SARAM and DARAM.
`Petitioner acknowledges that the DSP XRAM is
`system memory (Paper 3 at 45), and the DSP
`SARAM and DARAM is also system memory
`because it stores an operating system (OS) and
`other code executed by the DSP processor and it
`thus addressable by the DSP processor.
`
`Ex. 2007 (Declaration of Dr. Rinard), p. 73
`25
`
`Ex. 1010, Fig. 1
`
`
`
`Svensson Uses a Temporary System Buffer
`
`Ex. 1010, Fig. 2; 5:3-12; 21-32 (emphasis added)
`
`26
`
`
`
`Svensson Operates Exactly Like the
`Distinguished Prior Art
`
`’949 Patent -- Background
`
`Svensson
`
`Ex. 1001, 2:23-41(emphasis added)
`
`27
`
`Ex. 1010, 5:3-12; 21-28 (emphasis added)
`
`
`
`Svensson Copies the Image from a
`Temporary Buffer to RAM
`
`Svensson
`
`Ex. 1010, 2:43-44; 5:65-67; Fig. 2 (emphasis added)
`
`’949 Patent
`
`Ex. 1001, 5:31-35; 9:42-46 (emphasis added)
`
`28
`
`
`
`Dependent Claims 2 and 12
`
`2. The multi-processor system of claim 1 in which the scatter
`loader controller is configured to load the executable software
`image directly from the hardware buffer to the system
`memory of the secondary processor without copying data
`between the system memory locations on the secondary
`processor.
`
`12. The method of claim 10 further comprising loading the
`executable software image directly form a hardware buffer to
`the system memory of the secondary processor without
`copying data between system memory locations.
`
`Ex. 1001, 13:11-17; 14:3-6; Fig. 3; (emphasis added)
`
`29
`
`
`
`Patentability
`
`1) The Reference Combinations Do Not Load Each Received Data
`Segment Directly to System Memory
`2) The Reference Combinations Do Not Receive the Image Header and
`Each Data Segment Separately
`3) The Reference Combinations Do Not Teach Scatter Loading
`
`30
`
`Paper 16 at 61-69;
`Paper 25 at 31-35.
`
`
`
`’949 Patent – Claim 1
`1. A multi-processor system comprising:
`a secondary processor comprising:
`system memory and a hardware buffer for receiving an
`image header and at least one data segment of an
`executable software image, the image header and each data
`segment being received separately, and
`a scatter loader controller configured:
`to load the image header; and
`to scatter load each received data segment based at least in
`part on the loaded image header, directly from the
`hardware buffer to the system memory;
`a primary processor coupled with a memory, the memory
`storing the executable software image for the secondary
`processor; and
`an interface communicatively coupling the primary processor
`and the secondary processor, the executable software image
`being received by the secondary processor via the interface.
`31
`
`Ex. 1001, Fig. 4; 12:60-13:10 (emphasis added)
`
`
`
`Claim Construction – “Image Header”
`
`Agreed Construction: “a header
`associated with the entire image that
`specifies where the data segments are to
`be placed in the system memory”
`
`Board’s Suggested Construction:
`“having information that can be used to
`determine the placement of the at least
`one data segment in the system
`memory”
`• Fails to capture requirement
`that an “Image Header” be
`associated with an entire image
`
`Paper 16 at 12-14; Paper 21 at 6;
`Paper 10 at 8 (emphasis added)
`
`32
`
`Ex. 1001, Fig. 3 (emphasis added)
`
`
`
`Claim Construction – “Image Header”
`
`Agreed Construction: “a header
`associated with the entire image that
`specifies where the data segments are to
`be placed in the system memory”
`
`Board’s Suggested Construction:
`“having information that can be used to
`determine the placement of the at least
`one data segment in the system
`memory”
`
`Paper 16 at 12-14; Paper 21 at 6;
`Paper 10 at 8 (emphasis added)
`
`33
`
`Ex. 1001, Fig. 3 (emphasis added)
`
`
`
`Claims Require Multiple Data Segments
`
`63. .. [B]ecause scatter loading
`requires at least two data segments
`(otherwise there is no scattering of the
`data segments), the claims can be met
`only by at least two data segments.
`
`Ex. 2007, Declaration of Dr. Rinard, p. 65
`
`A. Scatter loading is usually defined as
`scatter loading data in accordance to
`some specification of locations, and
`those locations don’t have to be
`contiguous.
`Ex. 2001, Deposition of Dr. Lin, p. 19
`
`34
`
`Ex. 1001, Fig. 3 (emphasis added)
`
`
`
`Bauer Refers to Svensson’s Block Loader
`
`Ex. 1009 at ¶ 31 (emphasis added), Figs. 1A-1C
`
`“Bauer does not explicitly describe the loading process from the
`primary processor to the secondary processor in much detail.”
`
`35
`
`Paper 3 at 33; Ex. 1002 at ¶ 121
`
`
`
`Svensson Teaches a Block Loader
`
`36
`
`Ex. 1009, 6:18-25; Fig. 3
`(emphasis added)
`
`
`
`Svensson/Bauer Combination Would
`Transfer Data in Svensson’s Block Format
`
`Paper 16, p. 43
`
`37
`
`Ex. 1009, Fig. 3
`
`
`
`Svensson/Bauer Would Not Transfer
`Header and Data Separately
`
`Ex. 1010, 6:32-37; 6:54-57, Fig. 3 (emphasis added)
`
`156. Thus, the POSA would be motivated to keep the intermediate storage
`area full and send information to the intermediate storage area in fewer
`large transfers rather than more small transfers, consistent with the express
`teaching of Svensson.
`
`Ex. 2007 (Declaration of Dr. Rinard), 156.
`
`38
`
`
`
`Kim Does Not Use an “Image Header”
`
`128. .. Kim only discloses blocks of data, with
`each block having its own header. See, e.g., Ex.
`1012 at 4:13-21. Kim does not disclose an image
`header associated with the entire image.
`
`Ex. 2007, Declaration of Dr. Rinard, p. 65
`
`39
`
`Ex. 1012, Fig. 3 (emphasis added)
`
`
`
`Kim is Directed to a Different Problem
`
`.. [A] POSA would recognize that Kim is
`162.
`directed to solving a problem of overloading a
`system management processor
`attempting to
`process many
`simultaneous
`requests
`in
`a
`distributed system. Kim solves this problem by
`distributing the
`image data
`throughout
`the
`distributed system and directing requests
`to
`different components of the distributed system.
`The separation of block headers from blocks is to
`enable this distribution.
`It does not enable more
`efficient memory usage.
`
`Ex. 2007, Declaration of Dr. Rinard, p. 83
`
`40
`
`Ex. 1012, Fig. 2
`
`
`
`Kim is Directed to a Different Problem
`
`.. [A] POSA would recognize that Kim is
`162.
`directed to solving a problem of overloading a
`system management processor attempting to process
`many simultaneous requests in a distributed system.
`Kim solves this problem by distributing the image
`data throughout the distributed system and directing
`requests to different components of the distributed
`system. The separation of block headers from blocks
`is to enable this istribution. It does not enable more
`efficient memory usage.
`
`41
`
`Ex. 1012, p. 6; Fig. 2
`
`
`
`The POSA Would Not Rely on Kim’s Prior Art
`
`162. .. [A] POSA would recognize that Kim is directed to solving a
`problem of overloading a system management processor attempting
`to process many simultaneous requests in a distributed system. Kim
`solves this problem by distributing the image data throughout the
`distributed system and directing requests to different components of
`the distributed system. The separation of block headers from blocks
`is to enable this istribution.
`It does not enable more efficient
`memory usage.
`
`Paper 21 (Petitioner’s Reply), p. 47 (emphasis added)
`
`162. .. [A] POSA would recognize that Kim is directed to solving
`a problem of overloading a system management processor
`attempting to process many simultaneous requests in a distributed
`system. Kim solves this problem by distributing the image data
`throughout
`the distributed system and directing requests to
`different components of the distributed system. The separation of
`block headers from blocks is to enable this istribution.
`It does
`not enable more efficient memory usage.
`
`42
`
`Ex. 1012, p. 6; see also Ex. 25 at 35
`
`
`
`Patentability
`
`1) The Reference Combinations Do Not Load Each Received Data
`Segment Directly to System Memory
`2) The Reference Combinations Do Not Receive the Image Header and
`Each Data Segment Separately
`3) The Reference Combinations Do Not Teach Scatter Loading
`
`43
`
`Paper 16 at 58-61;
`Paper 25 at 29-31.
`
`
`
`’949 Patent – Claim 1
`1. A multi-processor system comprising:
`a secondary processor comprising:
`system memory and a hardware buffer for receiving an
`image header and at least one data segment of an
`executable software image, the image header and each data
`segment being received separately, and
`a scatter loader controller configured:
`to load the image header; and
`to scatter load each received data segment based at least in
`part on the loaded image header, directly from the
`hardware buffer to the system memory;
`a primary processor coupled with a memory, the memory
`storing the executable software image for the secondary
`processor; and
`an interface communicatively coupling the primary processor
`and the secondary processor, the executable software image
`being received by the secondary processor via the interface.
`44
`
`Ex. 1001, Fig. 3; 12:60-13:10 (emphasis added)
`
`
`
`Petitioner’s Interpretation of Bauer
`
`IPR2018-01334, Paper 3 at 47;
`Ex. 1009, Figs. 1A-1C.
`
`45
`
`
`
`Bauer Has No Disclosure of Scatter Loading
`
`46
`
`Ex. 1009, para. 37 (emphasis added)
`and Figs. 1A-1C
`
`
`
`Bauer Has No Disclosure of Scatter Loading
`
`A. .. [Paragraph 37 of Bauer is] talking about the
`sections and how they’re arranged within an image
`and they’re talking about the section information
`entries and how they’re arranged within the section
`information portion of the image.
`
`Ex. 2001 (Deposition of Dr. Lin), p. 70
`
`.. Paragraph 37 of Bauer merely discloses
`149.
`that data sections may be arbitrarily placed in the
`binary data image 100 of Figs. 1A-1C. There is no
`disclosure about how data sections are loaded or
`placed in the XRAM (i.e., the purported “system
`memory”) of the DSP device.
`
`Ex. 2007 (Declaration of Dr. Rinard), p. 77
`
`47
`
`Ex. 1009, Figs. 1A-1C
`
`
`
`Claim 16 Means-Plus-Function Limitations
`
`means for processing, by the secondary
`processor, the image header to determine
`at lease one location within system
`memory to which the secondary
`processor is coupled to store each data
`segment;
`
`“The corresponding structure identified in
`the specification is a modem processor
`coupled to a system memory, as described in
`the ‘949 patent at 3:9-12, 4:58-5:43, 5:59-
`6:39, 7:70-10:44. 8:50-56, and 9:27-41, and
`as shown in Figs. 1-3.”
`
`means for scatter loading, by the
`secondary processor, each data segment
`directly to the determined at least one
`location within the system memory, and
`each data segment being scatter loaded
`based at least in part on the processed
`image header.
`
`“The corresponding structure identified in
`the specification is a modem processor
`coupled to a system memory, as described in
`the ‘949 patent at Abstract, 1:24-33, 4:10-15,
`4:58-5:43, 5:59-6:39, 7:60-10:44, 8:21-30,
`8:62-67, 9:3-8, 9:16-56, 10:13-18 and 10:27-
`32, and as shown in Figs. 1-3.””
`
`Ex. 1001, 14:26-29; 14:33-37.
`
`48
`
`Ex. 2007, Declaration of Dr. Rinard, pp. 37, 39.
`
`
`
`Case No. IPR2018-01334
`Patent No. 8,838,949
`
`
`
`CERTIFICATE OF SERVICE
`
`
`The undersigned hereby certifies that a copy of the foregoing Patent Owner’s
`
`Demonstrative Exhibits was served on December 9, 2019 by email, as follows:
`
`David L. Cavanaugh (Registration No. 36,476)
`David.Cavanaugh@wilmerhale.com
`
`Thomas E. Anderson (Registration No. 37,063)
`Tom.Anderson@wilmerhale.com
`
`Joseph H. Haag (Registration No. 42,612)
`Joseph.Haag@wilmerhale.com
`
`
`Date: December 9, 2019
`
`
`/ Joseph M. Sauer /
`Joshua R. Nightingale, Reg. No. 47,919
`JONES DAY
`901 Lakeside Ave
`Cleveland, OH 44114
`
`Counsel for Patent Owner
`
`
`
Accessing this document will incur an additional charge of $.
After purchase, you can access this document again without charge.
Accept $ Charge
Still Working On It
This document is taking longer than usual to download. This can happen if we need to contact the court directly to obtain the document and their servers are running slowly.
Give it another minute or two to complete, and then try the refresh button.
A few More Minutes ... Still Working
It can take up to 5 minutes for us to download a document if the court servers are running slowly.
Thank you for your continued patience.
This document could not be displayed.
We could not find this document within its docket. Please go back to the docket page and check the link. If that does not work, go back to the docket and refresh it to pull the newest information.
Your account does not support viewing this document.
You need a Paid Account to view this document. Click here to change your account type.
Your account does not support viewing this document.
Set your membership
status to view this document.
With a Docket Alarm membership, you'll
get a whole lot more, including:
- Up-to-date information for this case.
- Email alerts whenever there is an update.
- Full text search for other cases.
- Get email alerts whenever a new case matches your search.
One Moment Please
The filing “” is large (MB) and is being downloaded.
Please refresh this page in a few minutes to see if the filing has been downloaded. The filing will also be emailed to you when the download completes.
Your document is on its way!
If you do not receive the document in five minutes, contact support at support@docketalarm.com.
Sealed Document
We are unable to display this document, it may be under a court ordered seal.
If you have proper credentials to access the file, you may proceed directly to the court's system using your government issued username and password.
Access Government Site
