UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
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`INTEL CORPORATION, LLC,
`Petitioner,
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`v.
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`QUALCOMM INCORPORATED,
`Patent Owner.
`____________
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`Case IPR2018-01334
`Patent 8,838,949 B2
`___________
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`Record of Oral Hearing
`Held: December 12, 2019
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`Before TREVOR M. JEFFERSON, DANIEL J. GALLIGAN, and
`AARON W. MOORE, Administrative Patent Judges.
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`____________
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
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`INTEL CORPORATION, LLC,
`Petitioner,
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`v.
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`QUALCOMM INCORPORATED,
`Patent Owner.
`____________
`
`Case IPR2018-01334
`Patent 8,838,949 B2
`___________
`
`Record of Oral Hearing
`Held: December 12, 2019
`____________
`
`Before TREVOR M. JEFFERSON, DANIEL J. GALLIGAN, and
`AARON W. MOORE, Administrative Patent Judges.
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`Case IPR2018-01334
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`APPEARANCES:
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`ON BEHALF OF THE PETITIONER:
`
`
`JOSEPH F. HAAG, ESQUIRE
`Wilmer Hale
`950 Page Mill Road
`Palo Alto, CA 94304
`
`THOMAS E. ANDERSON, ESQUIRE
`Wilmer Hale
`1875 Pennsylvania Avenue, NW
`Washington, D.C. 20006
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`
`
`ON BEHALF OF THE PATENT OWNER:
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`DAVID B. COCHRAN, ESQUIRE
`JOSEPH M. SAUER, ESQUIRE
`Jones Day
`North Point
`901 Lakeside Avenue
`Cleveland, OH 44114
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`The above-entitled matter came on for hearing on Thursday, December
`12, 2019, commencing at 9:01 a.m., at the U.S. Patent and Trademark
`Office, 600 Dulany Street, Alexandria, Virginia.
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`P R O C E E D I N G S
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`JUDGE JEFFERSON: Okay, good morning. Judge Galligan, can
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`you hear us?
`JUDGE GALLIGAN: Yes, I can hear you, can you hear and see me?
`JUDGE JEFFERSON: Yes, we can.
`JUDGE GALLIGAN: Great, good morning. This is an oral argument
`for IPR2018-1334 -- 01334 and it involves U.S. Patent Number 8,838,949.
`Petitioner is Intel and patent owner is Qualcomm and cases IPR2018-1335
`and 1336 have been consolidated with this proceeding.
`I am Administrative Patent Judge Galligan and before you in the
`hearing room are Administrative Patent Judges Jefferson and Moore.
`May I have appearances of counsel starting with petitioner please?
`MR. HAAG: Good morning, Your Honors. Joseph Haag --
`JUDGE GALLIGAN: Please step up to the podium and make sure
`the light’s illuminated, thank you.
`MR. HAAG: Good morning, Your Honors. Joseph Haag from
`Wilmer Hale representing the petitioner Intel. With me today is Tom
`Anderson also from Wilmer Hale. Dave Cavanaugh also from Wilmer Hale
`and then from my client Intel is Brad Waugh. Thank you.
`JUDGE GALLIGAN: Thank you. Patent owner?
`MR. COCHRAN: Good morning, Your Honors. Dave Cochran from
`Jones Day on behalf of Qualcomm. With me is my colleague Joe Sauer who
`is also from Jones Day. And with us from Qualcomm, the client, we have
`Ron Zhang, Yi Tang, Ken Vu and Jan Shen.
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`JUDGE GALLIGAN: Good morning.
`MR. COCHRAN: Morning.
`JUDGE GALLIGAN: Good morning, thank you. In this oral hearing,
`each party has been allotted one hour of argument time and petitioner bears
`the burden of proving unpatentability and will proceed first. Petitioner may
`reserve rebuttal time. Patent owner will proceed after petitioner and may
`reserve sur rebuttal time.
`And I would just remind the parties as you proceed please identify any
`slides and any pages of the record with specificity so that I can follow along
`and also it will make for a clearer record. I have all access to anything but I
`won’t see what you’re displaying on the screen there.
`Petitioner, how much time would you like to reserve for your rebuttal?
`MR. HAAG: 15 minutes please.
`JUDGE GALLIGAN: Thank you. And, patent owner, how much
`time would you like for sur rebuttal?
`MR. COCHRAN: Likewise, 15 minutes.
`JUDGE GALLIGAN: Thank you. And Judge Jefferson has
`graciously volunteered to run the clock in the hearing room so I believe
`that’s the case, sorry if I’m speaking out of turn.
`JUDGE JEFFERSON: Yes.
`JUDGE GALLIGAN: Thank you. And with that, petitioner, you may
`begin.
`MR. HAAG: Thank you, Your Honors. Joseph Haag again from
`Wilmer Hale for the petitioner Intel.
`On Slide 2, I would like to give you a brief road map of the topics I
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`intend to cover today. And I’m going to start with a brief overview of the
`949 patent and an overview of the prior art at issue in this IPR. And I’m
`then going to get into obviousness issues and some of the disputed issues in
`this matter.
`So I’d like to turn now to the 949 patent and if we go to Slide 5, we
`see challenged Claim 1 of the 949 patent. It includes a secondary processor
`in purple that has a system memory that’s shown in red and a hardware
`buffer that’s shown in light blue.
`It also requires in gray that the image header and each data segment
`are received separately by the hardware buffer and then Claim 1 also
`requires a scatter loader controller which we have colored yellow to load the
`image header and scatter load each received data segment into system
`memory.
`The claim also requires a primary processor that’s shown in green
`here with a memory that’s shown in orange as well as an interface that’s
`shown in blue that couples the primary and secondary processors.
`The other claims are generally similar to Claim 1, but broader at least
`in some respects. For instance Claim 1 is the only independent claim that
`requires a hardware buffer and scatter loading directly from the hardware
`buffer to system memory.
`And I’m going to focus mostly on Claim 1 for the issues here today
`because I think all the issues in dispute or almost all the issues in dispute
`relate to Claim 1 with the exception of a couple dependent claims.
`Slide 65 shows Figure 3 from the 949 patent with some highlighting
`and some annotations. In short, the 949 patent relates to a secondary
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`processor that receives from a primary processor an image header and then it
`requires the separate receipt of the data segments of the image which are
`then scatter loaded into the secondary processor’s system memory.
`And on the left here, in Figure 3 is the primary processor, that’s
`colored in green up at the very top and on the right with the purple coloring
`is the secondary processor.
`The primary processor includes a memory that’s shown down towards
`the bottom here in which an executable image, that’s with an image header
`and a data segment, originally exist and for example that’s before booting up
`is what I mean in this context. And that’s shown blown up in the left, the
`image header data segment one, data segment two and data segment three
`from that non-volatile memory.
`The secondary processor on the right includes a system memory and
`the goal is to get the data segments of the executable image from the non-
`volatile memory, the primary processor on the left into the proper locations
`in the system memory of the secondary processor on the right.
`And in the operation and this is shown in Claim 1 which we just went
`over. The secondary processor first receives the image header from the
`primary processor and that image header is then used to load each data
`segment of the executable image into the proper location in the system
`memory on the right.
`I’m going to turn now to a brief overview of the key prior art at issue
`and I’m going to begin by discussing the two key references from our
`obviousness combination, that’s the Svensson reference and then the Bauer
`reference and I’m going to start with Svensson.
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`And on Slide 9 we see some basic information about Svensson. One
`quick background point about Svensson, it relates to a bootloader for loading
`software from a host processor to a client processor.
`On Slide 10, we see Figure 1 from the Svensson reference and at the
`top above the dashed line it shows a primary processor in green and that says
`an ARM processor. And below the dashed line, it shows a secondary
`processor that’s in purple and labeled secondary processor as the DSP.
`The two processors are coupled by an interface and that’s shown here
`its labeled interface and it’s shown in dark blue. The primary processor
`includes a non-volatile memory, that’s in orange toward the top labeled
`memory and the secondary processor includes an intermediate storage area,
`that’s shown in light blue as a hardware buffer and we have labeled that
`here.
`And a system memory that’s the DSP XRAM shown in red and we
`have labeled that in red as system memory as well. So that’s below the
`dashed line here. And these are the basic structural components of the 949
`patent claims as well.
`If we turn to Slide 11, we see Figure 3 from the Svensson reference
`and this figure shows a file structure used by Svensson, most importantly or
`most relevant for our issues, it shows header with a length and a destination
`address that’s shown in yellow here and that destination address is where a
`data segment can be loaded in system memory.
`I’m going to turn now to the Bauer reference and that’s the second
`reference in our cited combination and I’m on Slide 12 right now.
`Importantly, the Bauer and Svensson references have the same inventors,
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`they’re assigned to the same company and teach the same multi-processor
`system. So in many respects, the two references are quite similar.
`And if we turn to Slide 13, on -- we show -- we have Figure 1 from
`Svensson on the left, that’s the figure we looked at earlier and Figure 2 from
`Bauer on the right. And as you can see, these two figures are identical aside
`from the reference numbers used in them. So both Bauer and Svensson
`disclose the same multi-processor system. The primary processor, the
`secondary processor, memory, hardware buffer and system memory.
`If we turn to Slide 14, it shows Figures 1A through 1C from Bauer on
`the right and it shows on the left smaller Figure 3 from the Svensson
`reference. Bauer discloses an improved file format over that disclosed in the
`Svensson reference.
`And more particularly, in Bauer Figure 1A we see a header 102 and
`section information 104. That section information 104 includes a load
`address for each data segment as shown in Figure 1C at the bottom. So
`towards the bottom highlighted in yellow we see load address one and load
`address two, that’s numerals 110-1 and 110- 2.
`Slide 15 shows paragraph 31 of the Bauer reference and this
`paragraph explains that the file format of Bauer can be used in many
`applications. It goes on to say and this is highlighted towards the bottom,
`that the program loaders from Svensson can be used with Bauer’s file
`format.
`Now, part of the reason I’m mentioning this is because the Svensson
`reference discloses more detail about the hardware components and the
`loader used.
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`Bauer shows that same figure that we looked at earlier with the
`hardware components but relates more to an improved file system, that’s the
`file system or file format we see on Slide 14 in Figures 1A through 1C. I’m
`going to turn now to --
`JUDGE MOORE: So is that the motivation to combine here, that
`Bauer’s file format is being described as something that can be used with
`Svensson?
`MR. HAAG: So that is one motivation to combine, yes. I mean, the
`other is that these two references are by the same inventors, the same
`company and as we look on Slide 13, we can see that the figures in them are
`the same, they’re very similar in many respects.
`JUDGE MOORE: But so is, standing alone, the same inventorship a
`motivation to combine?
`MR. HAAG: I don’t think just standing alone it would be, no. But
`when you have a cross reference that we see here and it’s what we see in
`Slide 31 that explicitly says hey, you can use this file system, this is from
`Bauer, paragraph 31 from Bauer. You can use this file system with the
`loader shown in Svensson, that is a pretty good motivation to combine.
`JUDGE MOORE: Does it tell --
`MR. HAAG: And I’ll show you -- I'm sorry, Your Honor.
`JUDGE MOORE: Please finish, I’m sorry.
`MR. HAAG: I was going to say I’ll show you some testimony later, I
`don’t think here is a dispute about a motivation to combine these two
`references. I think the only dispute is what exactly the combination would
`be if they were combined.
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`The reason I say that is because Dr. Rinard, the patent owner’s expert
`admitted that these two references would be combined.
`JUDGE MOORE: I thought one of their arguments was that
`petitioner just treats these two as the same which would -- which I
`interpreted to mean that they say that you had to establish a motivation to
`combine them, where you were just saying, you were just grouping them
`together.
`MR. HAAG: I don’t think and the patent owner can correct me if I'm
`wrong in this but I don’t think there is a dispute about whether the two
`references would be combined. I think it’s only how they would be
`combined. That is something that the patent owner does dispute, the manner
`in which they would be combined.
`And as for the issue about the references to Bauer and Svensson
`combined, that was something that was brought up by the patent owner and
`we did define that to mean Bauer alone or the two references combined.
`And we did when we used that term, we did go on to specifically cite
`which reference we are relying on by number and by paragraph or line
`numbers. And I don’t think that the patent owner has pointed out anything
`that they’re confused about in what we are relying on from the references.
`So if I go back to Kim, it discloses a multiprocessor system with a
`primary processor and secondary processors. And as we explained in our
`petition, Figure 1 shows a primary processor, system management processor
`11 and secondary processors for example as main processors 13.
`If we go to Slide 17, it shows Figure 3 from Kim with actually a fair
`amount of highlighting on it. This figure shows the separate receipt of a
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`header from a program block and that’s the part of Kim that we are relying
`on is this, for the separate receipt feature of the claims.
`And in particular, steps 305 and 306 in blue teach the transmission by
`a primary processor and receipt by a secondary processor of a header. And
`then step 309, this is in pink in the lower left, it reads transmit program
`block. That shows at a later time the transmission of a program block that’s
`a data bock to the secondary processor. So that’s the separate receipt of a
`header from a data segment.
`And if we go on to Slide 19, we’ve briefly shown which references we
`rely on for each limitation from Claim and the analysis is quite similar for
`the other challenged claims.
`If we turn to Slide 20, it shows the limitations from Claim 1 that are
`not in dispute and in the upper portion it shows labels from Figure 1 of
`Svensson for some of these undisputed limitations.
`There is no dispute that Bauer and Svensson teach a multi-processor
`system, a secondary processor comprising system memory, a primary
`processor coupled with the memory, the memory storing the executable
`software image for the secondary processor and an interface coupling the
`primary and secondary processors and across which the executable image is
`received by the secondary processors. So those are claim limitations that are
`not in dispute.
`I’m going to go now, and I’m on Slide 23, to some of the disputed
`issues and I’m going to start, Your Honor, Judge Moore, with the issue you
`brought up about motivation to combine. And after that I’m going to get
`into some of the claim construction issues and then some of the other issues
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`that are in dispute.
`So as I mentioned earlier, I’m on Slide 25 now and this relates to the
`motivation to combine issue. The first thing to realize is that there really is
`no dispute about whether Svensson and Bauer would be combined by a
`person of ordinary skill in the art. Such a person would and the patent
`owner does not dispute this and I’m going to briefly explain why.
`On Slide 25, we see that Bauer and Svensson share the same general
`multi-processor system and have some figures in common. We see Figure 1
`and Figure 2 from Bauer and Svensson here. And Bauer and Svensson are
`closely related. As I mentioned, they’re filed just a few months apart. They
`have the same inventors, same assignee and much of the same disclosure.
`And, Your Honor, to the specific point about whether there is an issue
`about whether it’d be obvious to combine Bauer and Svensson, on Slide 26,
`we see that patent owners expert, Dr. Rinard agreed that a person of ordinary
`skill in the art would be motivated to combine Bauer and Svensson.
`So that, Your Honor, is why I say there is no dispute on this particular
`issue about whether the two would be combined. Again, it’s about what
`exactly would be used from each of the references in the combination.
`On Slide 27, we see paragraph 31 of Bauer and it explains that the file
`format of Bauer can be used in many applications. It also says a program
`loader can read the stored information and process it and then it goes on to
`say in yellow toward the bottom that the program loader from Svensson,
`that’s the other reference we rely on can be used with the file format from
`Bauer.
`And on Slide 28, we see the file structures of Svensson on the left and
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`Bauer on the right given the close interrelatedness of the two references, a
`person of ordinary skill in the art would be motivated to use the file structure
`of Bauer in combination with Svensson’s loader as we see in the previous
`slide.
`Now, part of the reason why we are relying on both of these
`references, I mentioned that there is more detail in Svensson on some issues
`and more detail in Bauer on other issues, but Bauer also teaches the separate
`receipt feature. That’s not something we have alleged it shown by the
`Svensson reference.
`And then what we have relied on for the image header is it comes
`from Bauer and it’s the combination of the header and section information
`and I think that’s what Your Honors found ended up being an image header
`in the institution decision as well.
`We made an obviousness argument for combining the header and
`section information. Whether that’s an obviousness argument or an
`anticipation, I don’t think that’s an issue that’s disputed between the parties
`at least that’s not something that was disputed by patent owner in his patent
`owner response or sur reply.
`So that takes us to what the real dispute is about the combination of
`Bauer and Svensson and that’s whether a person of ordinary skill in the art
`would transfer an image in Bauer’s file format using Svensson’s program
`loader.
`Patent owner contends and we don’t agree with this, but the patent
`owner contends that a person of ordinary skill in the art would only be
`motivated to use Bauer’s file format for the image as originally stored in the
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`memory of the primary processor.
`And then they say you would need to convert that Bauer image file
`format from the non-volatile memory into Svensson’s file format for the
`loading process. So what they’re saying is you would convert to Svensson’s
`file format and use that in the intermediate storage area shown in Svensson
`and Bauer. And that’s something that we do not agree with.
`JUDGE MOORE: Does Bauer say where in Svensson you would use
`its file format if you were to combine it?
`MR. HAAG: It actually says and let me see if I can find that. So I’m
`on Slide 31, Your Honor, and this is looking at Bauer. And Bauer sets forth
`this file format as I mentioned in Figures 1A through 1C.
`And towards the bottom of paragraph 36 from Bauer you can see that
`it can be used in any of the memories that may store an image in the file
`format. That’s any of the memories shown.
`And on Slide 32 here, you can see that patent owner’s expert, Dr.
`Rinard, again that’s patent owners expert, admits that Bauer’s file format can
`be stored in any of the memories 206, 208, 211 and that includes the
`intermediate storage area. So the answer is it can be used in of those
`memories.
`And there are a number of reasons why we disagree with the patent
`owner’s argument here. In part because Bauer explicitly instructs to use
`Svensson’s program loader with Bauer’s file format and we see that in
`paragraph 31 which I have copied on Slide 30 and we talked about his
`earlier.
`There would be no reason to convert to Svensson's file format before
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`loading and there is nothing in Bauer that suggests that that is something that
`should be done.
`As I mentioned earlier, on Slide 31, it indicates that any of the
`memories in Figure 2 of Bauer can store the file format shown in Figures 1A
`through 1C so that means Bauer’s file format can be used in any of those
`memories. That includes the intermediate storage area.
`JUDGE MOORE: Does Svensson do the zero copy technique that’s
`talked about in the patent?
`MR. HAAG: Does Svensson do the zero copy technique? I think that
`depends on with exactly you mean by the zero copy technique. If what you
`mean by that is does it load from a hardware buffer, does it directly load
`from a hardware buffer to system memory, my answer is yes.
`But the point I’m making, Your Honor, on the slides that we have
`gone over is there is no reason to convert from Bauer’s file format in the
`non-volatile memory 206 into Svensson’s file format in the intermediate
`storage area.
`And that’s what patent owner’s contention is. And as I mentioned
`earlier on Slide 32, patent owner’s expert admitted that Bauer’s file format
`can be used in any of the memories.
`Now on slide 33, Bauer explicitly teaches in paragraph 43 that its
`header and section information format simplifies organization and makes
`memory loading efficient.
`That indicates this format would indeed be used for loading purposes
`in combination with Svensson. So how or what is one of the reasons it
`would be more efficient?
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`We see that here on Slide 34 and this shows paragraph 30 from Bauer.
`Patent owner argues that its conversion theory is supported by Bauer’s
`teaching to read various portions of Bauer’s image from non-volatile
`memory without any suggestion to first load the header and section
`information separately from section data.
`But Bauer explains and we see this in paragraph 30 here that his file
`format can be used so that the loader retrieves the section information 102,
`the header and section information, that’s what includes the load addresses
`for the data segments before it reads the data segments.
`That’s one of the ways that Bauer makes things more efficient is that
`the header and section information can be read over into the intermediate
`storage area before the data segments that allows the use of the section
`information to load because it has the addresses for where to load the data
`segments to load the data segments.
`And that’s entirely consistent with the use of Bauer’s file format in the
`intermediate storage area, not the use of Svensson’s file format in the
`intermediate storage area when the two references are combined.
`I’m on Slide 35 and I’m going to turn now to some of the claim
`construction issues that are in dispute. And the first two terms I will discuss
`for claim construction are system memory and hardware buffer and they
`relate in part to the next argument I have got on my list that’s grayed out,
`that’s where, whether Bauer and Svensson disclose a system memory and a
`hardware buffer. And so I’m going to talk about system memory and
`hardware buffer first and then briefly a couple other claim construction
`issues.
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`So on Slide 36, we see the competing constructions for system
`memory. We propose that either no construction is necessary or that it
`simply means memory where an executable software image can be loaded
`and executed.
`The patent owner seeks to construe it to mean memory that is
`addressable by the secondary processor which we think is overly broad and
`can be virtually any memory whether it actually is system memory or not.
`And there are number of problems that we have with the patent
`owner’s construction. First, the patent owner doesn’t cite any intrinsic
`evidence to support its construction. That is the 949 patent never indicates
`the system memory is any addressable memory. The 949 patent doesn’t
`even use that term, addressable.
`Second, the patent owner’s construction is so broad that it could cover
`non-volatile memory such as flash memory and read only memory
`addressable by a processor even though a person of ordinary skill in the art
`would not consider either type to be system memory.
`Now, in the case of flash memory, it is actually I think theoretically
`possible that it could be used as system memory but not in a typical system.
`In a typical system, flash memory is used for long term storage. It’s not
`used for the loading and execution of code and that’s what we mean by flash
`memory not being system memory. That’s not a typical usage at all of flash
`memory.
`JUDGE MOORE: So read only memory can’t be system memory or
`it can be?
`MR. HAAG: Read only memory -- code isn’t loaded into read only --
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`you can’t load code into read only memory. It’s only, you can only read to
`it.
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`JUDGE MOORE: Well, you do at some point I guess.
`MR. HAAG: So that makes it and that makes it hard to use as system
`memory.
`JUDGE MOORE: You do load code into it or can load code into the
`ROM at some point, right?
`MR. HAAG: True, at some point in time. Just --
`JUDGE MOORE: Just not on the fly, or it doesn’t go in and out.
`MR. HAAG: Yeah.
`JUDGE MOORE: It’s there.
`MR. HAAG: Correct. It’s there which means it’s loaded at one point
`in time. But when the system or the computer system is in operation, you
`don’t load code into the ROM, it’s already there.
`JUDGE GALLIGAN: Counsel, getting back to one of Judge Moore’s
`earlier questions about the zero, whether the prior art, whether Svensson
`talks about the zero copy transfer of the 949 or describes it, and I’m going to
`ask patent owner these questions as well.
`The patent owner’s case really seems to be that the 949 patent
`describes a drawback of a using a temporary buffer. You have to allocate it
`and then you have to use the temporary buffer to then store things into the
`system memory.
`And I think there is a, the patent certainly says that. It says there in
`the prior art you use a temporary buffer and what they allege is that that’s
`what the prior art is doing and their claim is different. And I have been
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`struggling with this.
`What would, what is patent -- what is petitioner’s response to that and
`I guess I would say where in the claim is that distinction not reflected or why
`does Svensson differentiate from the prior art problem for instance that’s
`identified?
`MR. HAAG: I think there are two issues here, Your Honor, so let me
`try to address both of them. The first thing is I’m looking at my Slide 48
`now to actually, you know, put a finer point on this.
`So what are we saying is the system memory in Svensson or Bauer for
`that matter since the figure is the same? And we see that here on Slide 48
`that the system memory is the DSP XRAM and we have identified the
`intermediate storage area as the hardware buffer and we have highlighted
`both of those here.
`So the first point, Your Honor, is that we have identified a hardware
`buffer that is separate from what we have identified as the claimed system
`memory. We have identified the DSP XRAM as the claimed system
`memory. We have identified the hardware buffer. The intermediate storage
`area is the hardware buffer. So those are separate things.
`JUDGE GALLIGAN: And just, and right -- and just a quick question
`on that. What patent owner or sorry, petitioner does not dispute that the
`intermediate storage area in Svensson and Bauer is allocated by the
`secondary processor at the time that the program loader is operating,
`correct?
`MR. HAAG: That is what it, that is what the reference says, correct,
`
`yes.
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`JUDGE GALLIGAN: Great, thank you.
`MR. HAAG: But nothing in Svensson or Bauer ever says that code is
`executed from that intermediate storage area. That intermediate storage area
`is used for the purpose of copying.
`In fact, when you look at Svensson and Bauer, it says that code is
`copied from that intermediate storage area to the system memory. And
`that’s the same as the hardware buffer in the patent. So the other point I
`want to make, Your Honor, a couple other points but this goes back to the
`question you asked a couple questions ago.
`Nothing in Svensson or Bauer ever says that once code is loaded into
`the system memory, the DSP XRAM that it’s copied from location to
`location. That’s something I think that the patent is trying to, the 949 patent
`is trying to get away from.
`But nothing ever says that and this is something that Dr. Rinard agrees
`with, patent owners expert agrees. Nothing in the references ever say you
`load to that DSP XRAM what we have identified as a system memory and
`then copy from one location to another. Nothing says that.
`The other point I want to make, Your Honor, is that what Your Honor
`said in the institution decision is something that we agree with and that’s that
`although the SA RAM and D, you said -- you see nothing in Claim 1 that
`prohibits the claimed hardware buffer from being part of some system
`memory. Rather Claim 1 requires system memory and a hardware buffer.
`We agree with that.
`The petitioner maps the XRAM 210 or 110 to the claimed system
`memory and we have called the intermediate storage area the hardware
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`buffer. Nothing in the claims prohibits that.
`JUDGE GALLIGAN: And I guess on that point, patent owner would,
`I’m not going to speak for patent owner but from its briefing I understand its
`position to be you’re mapping the hardware buffer to the very thing that we
`differentiated in the prior at.
`MR. HAAG: Yep. And that’s not --
`JUDGE GALLIGAN: Which is a temporary buffer allocated at run
`time.
`MR. HAAG: And that’s not something we agree with. I think what
`the patent is distinguishing is copying an entire
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