Paper 10
`Trials@uspto.gov
`571-272-7822 Entered: March 18, 2019
`
`
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`INTEL CORPORATION,
`Petitioner,
`
`v.
`
`QUALCOMM INCORPORATED,
`Patent Owner.
`
`____________
`
`Case IPR2018-01334
`Patent 8,838,949 B2
`____________
`
`
`
`
`
`Before TREVOR M. JEFFERSON, DANIEL J. GALLIGAN, and
`AARON W. MOORE, Administrative Patent Judges.
`
`
`GALLIGAN, Administrative Patent Judge.
`
`
`
`
`
`
`
`DECISION
`Institution of Inter Partes Review
`35 U.S.C. § 314
`
`
`
`
`Trials@uspto.gov
`571-272-7822 Entered: March 18, 2019
`
`
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`INTEL CORPORATION,
`Petitioner,
`
`v.
`
`QUALCOMM INCORPORATED,
`Patent Owner.
`
`____________
`
`Case IPR2018-01334
`Patent 8,838,949 B2
`____________
`
`
`
`
`
`Before TREVOR M. JEFFERSON, DANIEL J. GALLIGAN, and
`AARON W. MOORE, Administrative Patent Judges.
`
`
`GALLIGAN, Administrative Patent Judge.
`
`
`
`
`
`
`
`DECISION
`Institution of Inter Partes Review
`35 U.S.C. § 314
`
`
`
`
`
`IPR2018-01334
`Patent 8,838,949 B2
`
`
`I. INTRODUCTION
`
`Intel Corporation (“Petitioner”) filed a Petition requesting inter partes
`
`review of claims 1–9, 22, and 23 of U.S. Patent No. 8,838,949 B2 (“the ’949
`
`patent,” Ex. 1001). Paper 3 (“Pet.”). Qualcomm Incorporated (“Patent
`
`Owner”) filed a Preliminary Response. Paper 7 (“Prelim. Resp.”). Under
`
`37 C.F.R. § 42.4(a), we have authority to determine whether to institute
`
`review.
`
`The standard for instituting an inter partes review is set forth in
`
`35 U.S.C. § 314(a), which provides that an inter partes review may not be
`
`instituted unless the information presented in the Petition and the
`
`Preliminary Response shows “there is a reasonable likelihood that the
`
`petitioner would prevail with respect to at least 1 of the claims challenged in
`
`the petition.”
`
`After considering the Petition, the Preliminary Response, and
`
`associated evidence, we institute an inter partes review as to all challenged
`
`claims and on all grounds raised in the Petition.
`
`A. Related Matters
`
`As required by 37 C.F.R. § 42.8(b)(2), each party identifies various
`
`judicial or administrative matters that would affect or be affected by a
`
`decision in this proceeding. Pet. 2–3; Paper 4, 2. Among those related
`
`matters are IPR2018-01335 and IPR2018-01336, each of which involves
`
`different claims of the ’949 patent.
`
`B. Real Parties in Interest
`
`Petitioner identifies itself and Apple Inc. as real parties in interest.
`
`Pet. 2.
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`C. The ’949 Patent and Illustrative Claim
`
`The ’949 patent generally relates to loading software from one
`
`processor to another in a multi-processor system. Ex. 1001, at [57]. One
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`example disclosed in the ’949 patent involves loading modem image
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`executable data by first retrieving and processing an image header, which
`
`“includes information used to identify where the modem image executable
`
`data is to be eventually placed into the system memory of the secondary
`
`processor.” Ex. 1001, 8:9–21. Figure 3 of the ’949 patent is reproduced
`
`below.
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`Patent 8,838,949 B2
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`Figure 3 shows “operational flow for an exemplary loading process for
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`loading an executable image from a primary processor to a secondary
`
`processor according to one aspect of the present disclosure.” Ex. 1001,
`
`4:10–13. Referring to various components depicted in Figure 3, the ’949
`
`patent discloses the following:
`
`The header information is used by the secondary processor 302
`to program the scatter loader/direct memory access controller
`304 receive address when receiving the actual executable data.
`Data segments are then sent from system memory 307 to the
`primary hardware transport mechanism 308. The segments are
`then sent from the hardware transport mechanism 308 of the
`primary processor 301 to a hardware transport mechanism 309
`of
`the
`secondary processor 302 over an
`inter-chip
`communication bus 310 (e.g., a HS-USB cable.) The first
`segment transferred may be the image header, which contains
`information used by the secondary processor to locate the data
`segments into target locations in the system memory of the
`secondary processor 305. The image header may include
`information used to determine the target location information for
`the data.
`
`Ex. 1001, 8:21–35.
`
`Challenged claims 1 and 22 are independent claims, and claim 1 is
`
`reproduced below.
`
`1.
`
`A multi-processor system comprising:
`a secondary processor comprising:
`system memory and a hardware buffer for receiving
`an image header and at least one data segment of an
`executable software image, the image header and each
`data segment being received separately, and
`a scatter loader controller configured:
`to load the image header; and
`to scatter load each received data segment
`based at least in part on the loaded image header,
`directly from the hardware buffer to the system
`memory;
`
`
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`4
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`IPR2018-01334
`Patent 8,838,949 B2
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`a primary processor coupled with a memory, the memory
`storing the executable software image for the secondary
`processor; and
`an interface communicatively coupling the primary
`processor and the secondary processor, the executable software
`image being received by the secondary processor via the
`interface.
`
`
`D. References
`
`Petitioner relies upon the following references:
`
`Bauer
`
`US 2006/0288019 A1 Dec. 21, 2006
`
`Ex. 1009
`
`Svensson
`
`US 7,356,680 B2
`
`Apr. 8, 2008
`
`Ex. 1010
`
`Kim
`
`Korean Publication 10-
`2002-0036354
`
`May 16, 2002
`
`Exs. 1011,
`10121
`
`E. Asserted Ground of Unpatentability
`
`Petitioner asserts claims 1–9, 22, and 23 of the ’949 patent are
`
`unpatentable under 35 U.S.C. § 103 as obvious over the combined teachings
`
`of Bauer, Svensson, and Kim. Pet. 23–75.
`
`
`
`II. ANALYSIS
`
`A. Claim Construction
`
`In an inter partes review for a petition filed before November 13,
`
`2018, a claim in an unexpired patent shall be given its broadest reasonable
`
`construction in light of the specification of the patent in which it appears.
`
`37 C.F.R. § 42.100(b) (2018); see Changes to the Claim Construction
`
`Standard for Interpreting Claims in Trial Proceedings Before the Patent Trial
`
`
`1 In this Decision, we cite Exhibit 1012, which is the English translation of
`Kim provided by Petitioner.
`
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`and Appeal Board, 83 Fed. Reg. 51,340 (Oct. 11, 2018) (amending
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`37 C.F.R. § 42.100(b) effective November 13, 2018). In applying a broadest
`
`reasonable construction, claim terms generally are given their ordinary and
`
`customary meaning, as would be understood by one of ordinary skill in the
`
`art in the context of the entire disclosure. See In re Translogic Tech., Inc.,
`
`504 F.3d 1249, 1257 (Fed. Cir. 2007). This presumption may be rebutted
`
`when a patentee, acting as a lexicographer, sets forth an alternate definition
`
`of a term in the specification with reasonable clarity, deliberateness, and
`
`precision. In re Paulsen, 30 F.3d 1475, 1480 (Fed. Cir. 1994).
`
`1. Image Header
`
`Petitioner argues the term “image header” means “a header associated
`
`with the entire image that specifies where the data segments are to be placed
`
`in the system memory.” Pet. 17 (citing Ex. 1001, 7:50–52, 8:18–21, 9:23–
`
`24, 10:6, claim 10; Ex. 1008, 3; Ex. 1002 ¶ 77). Patent Owner does not
`
`address Petitioner’s proposed construction, but Petitioner notes that Patent
`
`Owner agreed to this proposed construction in an investigation involving the
`
`’949 patent at the International Trade Commission (“ITC”).2 Pet. 17 (citing
`
`Ex. 1008, 3).
`
`For the purpose of deciding whether to institute inter partes review on
`
`the present record, we need not determine the full scope of this term. See
`
`Nidec Motor Corp. v. Zhongshan Broad Ocean Motor Co., 868 F.3d 1013,
`
`1017 (Fed. Cir. 2017) (only those claim terms in controversy need to be
`
`construed, and only to the extent necessary to resolve the controversy).
`
`Rather, to determine whether Petitioner has made a sufficient unpatentability
`
`
`2 In re Certain Mobile Elec. Devices and Radio Frequency and Processing
`Components Thereof, Inv. No. 337-TA-1065.
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`showing for purposes of institution, we need only determine whether the
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`scope of this term encompasses elements found in the prior art.
`
`Nevertheless, to provide guidance to the parties during trial, we note that
`
`Petitioner’s proposed construction is problematic for at least three reasons.
`
`First, this definition does not explain what a “header” itself is or what data
`
`must be present for something to be considered a header, if any at all. The
`
`significance of this issue will become evident in the discussion below
`
`concerning the teachings of the prior art. Second, Petitioner’s proposed
`
`construction recites “data segments,” suggesting that plural data segments
`
`are required, but the claims recite “at least one data segment” and, therefore,
`
`are met by only a single data segment. Third, requiring the image header to
`
`“specif[y] where the data segments are to be placed in the system memory”
`
`appears to narrow the term unduly. Claim 1, for example, recites “a scatter
`
`loader controller configured . . . to scatter load each received data segment
`
`based at least in part on the loaded image header.” The ’949 patent discloses
`
`that “[t]he image header includes information used to identify where the
`
`modem image executable data is to be eventually placed into the system
`
`memory of the secondary processor 305.” Ex. 1001, 8:18–21. The ’949
`
`patent further discloses the following: “In one aspect, the target locations
`
`are not predetermined, but rather are determined by software executing in
`
`the secondary processor as part of the scatter loading process. Information
`
`from the image header may be used to determine the target locations.” Ex.
`
`1001, 8:36–40. The claims and the specification of the ’949 patent,
`
`therefore, contemplate image headers that provide information used to
`
`determine where to load data in memory, even if the image headers do not
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`“specif[y] where the data segments are to be placed in the system memory.”
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`Thus, the image header is perhaps better described as having information
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`that can be used to determine the placement of the at least one data segment
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`in the system memory.
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`Based on the foregoing, we are not persuaded Petitioner’s proposed
`
`construction of “image header” is the broadest reasonable interpretation
`
`consistent with the specification of the ’949 patent. Petitioner’s proposed
`
`construction is merely one example of such an image header. See, e.g.,
`
`Ex. 1001, 7:50–52 (describing “one aspect” in which “[t]he image header
`
`also specifies the destination address of the image in target memory”).
`
`Thus, we do not adopt Petitioner’s proposed construction. For purposes of
`
`this Decision, however, we determine that Petitioner’s proposed construction
`
`falls within the broadest reasonable interpretation of “image header.”
`
`During the trial, the parties are encouraged to address this issue further if
`
`they deem it relevant to the disputed issues.
`
`2. Remaining Terms
`
`For purposes of this Decision, we do not find it necessary to construe
`
`expressly any other claim terms. See, e.g., Nidec, 868 F.3d at 1017 (“[W]e
`
`need only construe terms ‘that are in controversy, and only to the extent
`
`necessary to resolve the controversy’ . . . .” (quoting Vivid Techs., Inc. v.
`
`Am. Sci. & Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir. 1999))).
`
`B. Principles of Law
`
`A patent claim is unpatentable under 35 U.S.C. § 103(a) if the
`
`differences between the claimed subject matter and the prior art are such that
`
`the subject matter, as a whole, would have been obvious at the time the
`
`invention was made to a person having ordinary skill in the art to which said
`
`subject matter pertains. KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 406
`
`
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`(2007). The question of obviousness is resolved on the basis of underlying
`
`factual determinations including: (1) the scope and content of the prior art;
`
`(2) any differences between the claimed subject matter and the prior art;
`
`(3) the level of ordinary skill in the art; and (4) any secondary
`
`considerations, if in evidence.3 Graham v. John Deere Co., 383 U.S. 1, 17–
`
`18 (1966).
`
`C. Alleged Obviousness over Bauer, Svensson, and Kim
`(Claims 1–9, 22, and 23)
`
`Petitioner asserts claims 1–9, 22, and 23 of the ’949 patent are
`
`unpatentable under 35 U.S.C. § 103 as obvious over the combined teachings
`
`of Bauer, Svensson, and Kim. Pet. 23–75. For purposes of determining
`
`whether to institute, we focus on Petitioner’s contentions with respect to
`
`claim 1, and, in our analysis of claim 1, we address all of the arguments
`
`made in the Preliminary Response.
`
`1. Svensson
`
`Svensson describes a multi-processor system in which data are sent
`
`from a host processor to a client processor. Ex. 1010, at [57]. Figure 1 of
`
`Svensson is reproduced below.
`
`
`3 Patent Owner does not present arguments or evidence of such secondary
`considerations in the Preliminary Response.
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`Figure 1 depicts multi-processor system 100 having host processor 102 and
`
`client processor 104. Ex. 1010, 3:49–50. Client processor 104 is the
`
`processor for a digital signal processor (DSP) device. Ex. 1010, 3:54–58.
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`As Svensson explains, “[m]ost commercially available DSP devices include
`
`on-chip memories, and as indicated in FIG. 1, the DSP includes ‘internal’
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`single-access RAM (SARAM) and dual-access RAM (DARAM) 108, as
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`well as an ‘external’ RAM (XRAM) 110.” Ex. 1010, 3:64–4:1. Svensson
`
`explains that “XRAM 110 is invisible to, i.e., not accessible by, the CPU
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`102,” whereas CPU 102 can access “internal” SARAM and DARAM 108.
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`Ex. 1010, 4:5–8, 4:13–14. DSP processor 104 can access both RAMs 108
`
`and 110. Ex. 1010, 4:7–8.
`
`Because host processor 102 cannot access XRAM 110, Svensson
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`discloses a technique for sending data from host processor 102 to be stored
`
`in XRAM 110. Ex. 1010, Fig. 2, 4:15–6:11, 7:7–8. Svensson’s Figure 2 is
`
`reproduced below.
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`Figure 2 is a flow chart of Svensson’s bootloader operation. Ex. 1010, 3:34,
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`4:15–19. In step 212, a block of memory in “internal” memory 108 is
`
`reserved as an intermediate storage area (ISA) for data that are being sent
`
`from the host to the invisible memory of the client processor. Ex. 1010,
`
`5:21–28. After the host transfers data to the ISA (step 216), the host tells the
`
`client the ISA has been loaded and indicates whether more data are coming
`
`(step 218). Ex. 1010, 5:53–63. The client then copies the data from the ISA
`
`to its “invisible” memory (step 220) and responds to the host when copying
`
`is finished (step 222). Ex. 1010, 5:63–6:3. “If there is more code and/or
`
`data to load (Step 224), this cycle of copying and messaging (Steps 216-224)
`
`can be repeated as many times as required.” Ex. 1010, 6:4–6.
`
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`2. Bauer
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`Bauer discloses the file format depicted in Figures 1A, 1B, and 1C,
`
`which are reproduced below.
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`
`
`Figure 1A shows the format for a data image, Figure 1B shows the header of
`
`the data image, and Figure 1C shows the section information of the data
`
`image. Ex. 1009 ¶¶ 21–23. As shown in Figure 1A, binary data image 100
`
`has header 102, section information 104, and section data 106. Ex. 1009
`
`¶ 32. Each section of data in section data 106 has a section information
`
`entry in section information 104, two of which are depicted in Figure 1C as
`
`entries 104-1 and 104-2. Ex. 1009 ¶ 34. Each section information entry
`
`indicates the length (108) and load address (110) for its respective section
`
`data. Ex. 1009 ¶ 34. Additional information about a section may be
`
`included in extra information element 112. Ex. 1009 ¶ 34.
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`According to Bauer, “[h]aving all section information entries 104
`
`collected together in the image 100 advantageously simplifies system
`
`navigation through the image, and having all section data arranged in a
`
`sequence makes it possible to optimize loading of the sections.” Ex. 1009
`
`¶ 38. Bauer explains that “[t]here are many possible applications of this
`
`format and its individually coded sections,” including “[o]bject code and
`
`data . . . with a program loader reading the stored information and
`
`processing stored sections accordingly.” Ex. 1009 ¶ 31. “One example of
`
`such a program loader is described in U.S. patent application Ser. No.
`
`11/040,798 filed on Jan. 22, 2005, by M. Svensson et al. for ‘Operating-
`
`System-Friendly Bootloader.’” Ex. 1009 ¶ 31. This is the application that
`
`issued as Svensson. Svensson’s Figure 1 depicts the same multi-processor
`
`system as Bauer’s Figure 2, which Bauer says “can advantageously use a
`
`binary image 100 having the format depicted in FIGS. 1A, 1B, 1C.”
`
`Ex. 1009 ¶ 35; compare Ex. 1010, Fig. 1, with Ex. 1009, Fig. 2.
`
`3. Kim
`
`Kim discloses a system in which a system startup loader in a system
`
`management processor provides program blocks to multiple other processors
`
`in a system. Ex. 1012, 4:8–21, Fig. 1. Figure 3 of Kim is reproduced below.
`
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`Figure 3 is a flowchart showing a procedure for loading program blocks
`
`from the system startup loader to other processors in the system. Ex. 1012,
`
`5:9–11. In step S304, the booter in a processor requests program block
`
`header information, which the system startup loader provides in step S305.
`
`Ex. 1012, 5:18–21. When the header is received, the booter requests a
`
`program block in step S307, which the system startup loader provides in step
`
`S309. Ex. 1012, 5:21–24. If there are more blocks to be received, the
`
`booter returns to step S304. Ex. 1012, 6:2–4.
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`4. Independent Claim 1
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`a. Overview of Petitioner’s Contentions
`
`Independent claim 1 is directed to a “multi-processor system” having
`
`“a secondary processor,” “a primary processor,” and “an interface
`
`communicatively coupling the primary processor and the secondary
`
`processor.” Figure 2 of Bauer is reproduced below.
`
`
`
`Figure 2 of Bauer depicts multi-processor system 200 having host
`
`processor 202 and client processor 204. Ex. 1009 ¶ 35. In Figure 2, host
`
`processor 202 is an advanced RISC (reduced instruction set computer)
`
`machine (ARM) central processing unit (CPU), and client processor 204 is a
`
`DSP CPU. Ex. 1009 ¶ 35.
`
`In its obviousness contentions, Petitioner argues a person of ordinary
`
`skill in the art would have been motivated to combine the teachings of Bauer
`
`and Svensson because, among other reasons, Bauer expressly cites
`
`Svensson’s program loader as an example of a program loader that can use
`
`the file format disclosed in Bauer. Pet. 24 (citing Ex. 1009 ¶ 31; Ex. 1002
`
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`¶¶ 103–104); see Ex. 1009 ¶ 31 (“One example of such a program loader is
`
`described in U.S. patent application Ser. No. 11/040,798 filed on Jan. 22,
`
`2005, by M. Svensson et al. for ‘Operating-System-Friendly Bootloader.’”).
`
`Based on the interrelatedness of the references, Petitioner refers to the
`
`teachings of “Bauer and Svensson combined.” Pet. 24–25.
`
`Referring to Bauer’s Figure 2, which depicts the same multi-processor
`
`system as Svensson’s Figure 1, Petitioner contends the DSP device teaches
`
`the claimed “secondary processor” and the ARM device teaches the claimed
`
`“primary processor.” Pet. 26–27, 50. Petitioner argues that the non-volatile
`
`memory coupled to the ARM CPU stores executable software for the DSP
`
`device and, therefore, that the combination of Bauer and Svensson teaches
`
`“a primary processor coupled with a memory, the memory storing the
`
`executable software image for the secondary processor.” Pet. 50–51 (citing
`
`Ex. 1009 ¶¶ 11, 31, 35–36, Fig. 2; Ex. 1010, 3:49–63, 4:3–8, 4:9–14, 6:12–
`
`15, Figs. 1, 3; Ex. 1002 ¶¶ 152–153). Petitioner further argues Figure 2 of
`
`Bauer and Figure 1 of Svensson show these two processors coupled by an
`
`interface and that the combination of Bauer and Svensson, therefore, teaches
`
`“an interface communicatively coupling the primary processor and the
`
`secondary processor, the executable software image being received by the
`
`secondary processor via the interface.” Pet. 51–52 (citing Ex. 1009 ¶ 36,
`
`Fig. 2; Ex. 1010, 4:3–5, 4:9–14, Fig. 1; Ex. 1002 ¶¶ 154–155); see Ex. 1009
`
`¶ 36 (“The arrows in FIG. 2 indicate access paths, e.g., busses and direct
`
`memory access (DMA) paths, between the CPUs and the memories . . . .”).
`
`Claim 1 also recites that the secondary processor comprises the
`
`following: “system memory and a hardware buffer for receiving an image
`
`header and at least one data segment of an executable software image, the
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`image header and each data segment being received separately,” and “a
`
`scatter loader controller configured: to load the image header; and to scatter
`
`load each received data segment based at least in part on the loaded image
`
`header, directly from the hardware buffer to the system memory.”
`
`Petitioner contends DSP XRAM 210 teaches “system memory” and
`
`intermediate storage area in DSP SARAM and DARAM 208 teaches “a
`
`hardware buffer.” Pet. 27 (citing Ex. 1009 ¶¶ 35–36, Fig. 2; Ex. 1010, 3:54–
`
`58, 3:64–4:5, Fig. 1; Ex. 1002 ¶ 110). Petitioner argues the subject matter
`
`reciting “a hardware buffer for receiving an image header and at least one
`
`data segment of an executable software image, the image header and each
`
`data segment being received separately” would have been obvious based on
`
`the combined teachings of Bauer and Svensson. Pet. 27–39. Petitioner
`
`additionally argues that receiving an image header and a data segment
`
`separately would have been obvious based on the combined teachings of
`
`Bauer, Svensson, and Kim. Pet. 39–44. Petitioner argues the subject matter
`
`recited for the claimed “scatter loader controller” would have been obvious
`
`based on the combined teachings of Bauer and Svensson, relying primarily
`
`on Svensson’s disclosure of the DSP device loading data from the
`
`intermediate storage area to the DSP XRAM. See Pet. 44–49. We further
`
`address Petitioner’s contentions, as well as Patent Owner’s arguments,
`
`below.
`
`b. Image Header
`
`Petitioner notes that, in Bauer, section information 104, rather than
`
`header 102, specifies the destination addresses for each section of data.
`
`Pet. 34 (citing Ex. 1009 ¶¶ 32–34, Figs. 1A–1C; Ex. 1002 ¶ 123). Petitioner
`
`argues, therefore, that Bauer does not teach the claimed “image header”
`
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`17
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`IPR2018-01334
`Patent 8,838,949 B2
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`under Petitioner’s construction of “a header associated with the entire image
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`that specifies where the data segments are to be placed in the system
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`memory.” Pet. 34. Petitioner argues, however, that it would have been
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`obvious to a person of ordinary skill in the art to provide the address
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`information in the header for various reasons, including that such a
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`modification would have been obvious to try based on the limited number of
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`locations to put the destination addresses. Pet. 34–36. Patent Owner argues
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`Petitioner’s “obvious to try” rationale is deficient because Petitioner does
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`not identify a recognized problem or need in the art that allegedly would
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`have been addressed by the proposed modification. Prelim. Resp. 16–21.
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`On this record, we are persuaded that the combination of Bauer and
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`Svensson renders obvious an “image header.” There is no dispute, at this
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`stage of the proceeding, that Bauer’s section information 104 is “associated
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`with the entire image” and “specifies where the data segments are to be
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`placed in the system memory,” two attributes of Petitioner’s proposed
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`interpretation. Bauer discloses that “[e]ach section in the section data 106
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`has a respective ‘section information’ entry in the section information 104”
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`and that each section information entry has a load address for the section,
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`designated in Figure 1C as elements 110-1 and 110-2. Ex. 1009 ¶ 34,
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`Fig. 1C. Bauer also discloses that “[h]aving all section information
`
`entries 104 collected together in the image 100 advantageously simplifies
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`system navigation through the image” (Ex. 1009 ¶ 38), thereby teaching that
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`the section information is associated with the entire image. Thus, the only
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`difference between Bauer’s section information and Petitioner’s proposed
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`construction of “image header” is the label applied, namely whether it is a
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`“header” or not. As discussed in the claim construction section above,
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`Patent 8,838,949 B2
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`Petitioner’s proposed construction of “image header” does not define what a
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`header is. On this record, it is not clear why section information 104 itself is
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`not an image header. It is also unclear, on this record, how the particular
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`label applied to content creates any patentable distinction over a system that
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`is capable of receiving that content.
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`In any event, Petitioner’s proposed modification appears to involve
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`little more than applying the label “header” to Bauer’s header 102 and
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`section information 104 collectively. In several instances, Bauer’s
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`disclosure itself effectively treats these two data segments as one entity. For
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`example, Bauer discloses the following:
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`Other arrangements [of the file format] are possible, of
`course. It is important only that the header and section
`information can be read before the rest of an image. The
`locations of the header and section information can be anywhere
`in the image, provided it is possible to access the header and
`section information before the rest of the image.
`
`Ex. 1009 ¶ 29. Bauer further discloses that “[i]nformation about the sections
`
`is located in a header and section information at, for example, the beginning
`
`of the image, and so the information about the sections can be retrieved
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`before the sections are read.” Ex. 1009 ¶ 30. According to Bauer, therefore,
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`header and section information are required to deal properly with the data in
`
`the image, but the particular labels applied to these sections of data are not
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`important.
`
`The Supreme Court has stated that, in evaluating obviousness, “[w]hat
`
`matters is the objective reach of the claim. If the claim extends to what is
`
`obvious, it is invalid under § 103.” KSR, 550 U.S. at 419. Bauer’s section
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`information 104 has the attributes ascribed to “image header” under
`
`Petitioner’s proposed interpretation, even if it is not labeled a “header.”
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`Bauer also expressly states that “[o]ther arrangements” of its file format are
`
`possible, provided that “header and section information can be read before
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`the rest of an image.” Ex. 1009 ¶ 29. On this record, we are persuaded by
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`Petitioner’s contention that a person of ordinary skill in the art “would have
`
`found it obvious to modify Bauer and Svensson combined to provide, in the
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`header rather than in the separate section information or elsewhere, the
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`destination addresses specifying where the data segments are to be placed in
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`the system memory.” Pet. 34; Ex. 1002 ¶ 124.
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`c. Receiving Image Header and Each Data Segment Separately
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`Claim 1 recites “a hardware buffer for receiving an image header and
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`at least one data segment of an executable software image, the image header
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`and each data segment being received separately.” As discussed above,
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`Petitioner asserts the intermediate storage area in DSP SARAM and
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`DARAM 208 teaches “a hardware buffer,” which we discuss further below.
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`Petitioner contends Bauer discloses that its file format can hold executable
`
`data and object code, thereby teaching “an executable software image.”
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`Pet. 28 (citing Ex. 1009 ¶¶ 30–32; Ex. 1002 ¶ 113); see Ex. 1009 ¶ 31
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`(“There are many possible applications of this format and its individually
`
`coded sections. . . . It can also be used as a file format in which executable
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`files are stored . . . .”). Bauer’s file format stores data in section data 106.
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`Ex. 1009 ¶ 32 (“The section data 106 includes the data of the one or more
`
`sections included in the image 100.”), Fig. 1A. As discussed above, we are
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`persuaded the combination of Bauer and Svensson renders obvious an
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`“image header.”
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`Petitioner contends that the subject matter of receiving the image
`
`header and each data segment separately would have been obvious to a
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`person of ordinary skill in the art based on the combined teachings of Bauer
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`and Svensson. Pet. 37–39. In particular, Petitioner relies on Bauer’s
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`disclosure that “[i]nformation about the sections is located in a header and
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`section information at, for example, the beginning of the image, and so the
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`information about the sections can be retrieved before the sections are
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`read.” Ex. 1009 ¶ 30 (emphasis added), cited in Pet. 37. Citing the
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`testimony of its declarant, Dr. Lin, Petitioner argues that a person of
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`ordinary skill in the art
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`would understand from Bauer and Svensson combined that
`“retrieving” the header and section information containing the
`destination addresses in Bauer before the data segments are
`read and processed means that the secondary processor’s
`hardware buffer (intermediate storage area) receives the header
`and section information separately from (and before) the data
`segments are transferred.
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`Pet. 37–38 (citing Ex. 1002 ¶ 131). Petitioner argues that, based on Bauer
`
`and Svensson’s disclosure of transferring data between processors in blocks,
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`it “would have been obvious to a [person of ordinary skill in the art] to have
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`the secondary processor’s hardware buffer (intermediate storage area)
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`receive the modified image header separately from the data segments.” Pet.
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`38 (citing Ex. 1010, 5:28–36, 5:53–6:33, 6:67–7:2, Fig. 2; Ex. 1009 ¶¶ 27,
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`43, Figs. 1A–1C; Ex. 1002 ¶ 132).
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`Patent Owner argues that “Petitioner’s argument misinterprets Bauer.
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`Although Bauer uses the term ‘retrieving,’ it is evident that it is describing
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`‘reading’—not ‘receiving’—the header/section information before the
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`sections of the image.” Prelim. Resp. 25. In support of its contention,
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`Patent Owner cites various passages in which Bauer discloses reading
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`header and section information before the data segments. Prelim. Resp. 25–
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`21
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`26 (citing Ex. 1009 ¶¶ 28, 29). Although Bauer discloses reading section
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`and header information before data segments, it also expressly uses the term
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`“retrieved” in paragraph 30, quoted above. Petitioner cites Dr. Lin’s
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`testimony that retrieving section and header information before data
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`segments means receiving section and header data separately from the data
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`segments. Ex. 1002 ¶ 131, cited in Pet. 37–38. Based on the evidence of
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`record at this stage of the proceeding, we are persuaded by Petitioner’s
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`contention that Bauer’s disclosure of retrieving the header and section
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`information before the data segments teaches receiving the header and
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`section information separately from the data segments. Pet. 37–38; Ex. 1002
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`¶ 131.
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`Patent Owner also argues that Bauer’s disclosure of reading header
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`and section information before the rest of the image (Ex. 1009 ¶ 29) “makes
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`no mention of Bauer’s intermediate storage area—the ‘hardware buffer,’ as
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`alleged by Petitioner—reading or receiving anything.” Prelim. Resp. 26.
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`Although this may be true as to Bauer alone, Petitioner relies on Bauer’s
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`disclosure in combination with Svensson’s disclosure of transferring data
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`from one processor to a second processor by first transferring data to the
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`intermediate storage area in the second processor. See Pet. 37–39.
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`Petitioner’s combination is expressly suggested in Bauer, which identifies
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`Svensson’s program loader as one in which Bauer’s file format can be used.
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`Ex. 1009 ¶ 31 (“One example of such a program loader is described in U.S.
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`patent application Ser. No. 11/040,798 filed on Jan. 22, 2005, by M.
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`Svensson et al. for ‘Operating-System-Friendly Bootloader.’”).
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`On this record, we are persuaded by Petitioner’s contention that the
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`subject matter of “receiving an image header and at least one data segment
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`22
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`IPR2018-01334
`Patent 8,83
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