IPR2018-01334
`U.S. Patent No. 8,838,949
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`IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`Intel Corporation
`Petitioner
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`v.
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`Qualcomm Incorporated
`Patent Owner
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`IPR2018-013341
`U.S. Patent No. 8,838,949
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`PETITIONER’S REPLY
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`1 IPR2018-01335 and IPR2018-01336 have been consolidated with the instant
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`proceeding.
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`IPR2018-01334
`U.S. Patent No. 8,838,949
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`I.
`II.
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`TABLE OF CONTENTS
`INTRODUCTION ........................................................................................... 1
`PATENT OWNER’S PROPOSED CONSTRUCTIONS SHOULD BE
`REJECTED ...................................................................................................... 3
`A.
`“System Memory” ................................................................................. 3
`B.
`“Image Header” ..................................................................................... 6
`C.
`“Hardware Buffer” ................................................................................ 8
`D.
`“Scatter Loader Controller” ................................................................. 11
`E. Means-Plus-Function Limitations ....................................................... 13
`III. CLAIMS 1-23 ARE OBVIOUS .................................................................... 15
`A.
`Patent Owner Cannot Escape Invalidity Based On The
`Petitioner’s Use Of The Phrase “Bauer and Svensson
`Combined” ........................................................................................... 17
`Petitioner Has Established That A POSITA Would Have Been
`Motivated To Combine Bauer And Svensson ..................................... 19
`Petitioner Has Established That It Would Have Been Obvious
`To Transfer An Image In Bauer’s File Format To A System
`Memory Of A Secondary Processor Using Svensson’s Program
`Loader .................................................................................................. 21
`Bauer in Combination with Svensson Meets the “System
`Memory” Requirements ...................................................................... 31
`The Combination of Bauer And Svensson Teaches The “Scatter
`Loading” Limitations ........................................................................... 36
`The Combination Of Bauer And Svensson Alone Or With Kim
`Teaches The Secondary Processor Receiving The Image Header
`And Each Data Segment Separately .................................................... 42
`The Combination of Bauer and Svensson Teaches a “Hardware
`Buffer” ................................................................................................. 47
`The Combination of Bauer and Svensson Teaches a “Scatter
`Loader Controller” ............................................................................... 49
`Dependent Claims 2 and 12 are Obvious ............................................ 52
`I.
`IV. CONCLUSION .............................................................................................. 54
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`G.
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`H.
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`i
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`B.
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`C.
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`D.
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`E.
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`F.
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`IPR2018-01334
`U.S. Patent No. 8,838,949
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`I.
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`INTRODUCTION
`In its Petitions, Intel Corporation (“Petitioner”) explained in detail how each
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`challenged claim is invalid in view of Bauer in combination with Svensson (for
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`claims 1-15 and 22-23), or alternatively, in view of the combination of Bauer and
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`Svensson with one or more of Kim (for claims 1-23), Zhao (for claims 16 and 17),
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`and Lim (for claims 18-21). And after considering the arguments that Qualcomm
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`Incorporated (“Patent Owner”) advanced in its Preliminary Responses, the Board
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`found that Petitioner had established a reasonable likelihood that the challenged
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`claims are invalid, and instituted inter partes review on all challenged grounds.
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`In its Response, Patent Owner just repeats many of the same arguments that
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`it previously raised in its Preliminary Responses, and that the Board considered
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`and rejected in its Institution Decisions. Those arguments should be rejected again
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`here, along with Patent Owners new arguments, none of which has merit.
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`First, for many of its arguments, Patent Owner rests on proposed claim
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`constructions for certain terms (e.g., “system memory,” “hardware buffer,” “scatter
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`loader controller”) that are inconsistent with the terms’ plain meanings and find no
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`support in the intrinsic record. Patent Owner cannot avoid invalidity based on such
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`improper attempts to re-write the claims.
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`Second, Patent Owner argues that a POSITA would not have been motivated
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`to combine the asserted prior art references, including Bauer and Svensson. But as
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`1
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`IPR2018-01334
`U.S. Patent No. 8,838,949
`explained in the Petitions, and as the Board recognized in its Institution Decisions,
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`compelling record evidence demonstrates that such a motivation existed—
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`including because Bauer and Svensson share the same inventors and much of the
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`same disclosure, and Bauer explicitly references Svensson as disclosing a program
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`loader that can read and process information contained in Bauer’s disclosed file
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`format. Ex. 1009 at [0031].
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`Finally, Patent Owner argues that, even if combined, the references still fail
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`to teach certain limitations of the challenged claims. As an initial matter, however,
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`many of those arguments hinge on the untenable proposed constructions referenced
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`above—and should be rejected for that reason alone. Moreover, Patent Owner’s
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`remaining arguments largely rely on attempts to restrict the prior art references in a
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`manner that simply cannot be squared with the express disclosures of the
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`references themselves. As Intel’s expert, Dr. Bill Lin, has confirmed, when
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`considered from the perspective of a person of ordinary skill in the art (POSITA),
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`the asserted prior art references teach all limitations of the challenged claims.
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`In sum, because Patent Owner has failed to rebut Petitioner’s compelling
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`evidence establishing that each challenged claim is invalid, the claims should be
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`found unpatentable and cancelled.
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`2
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`II.
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`IPR2018-01334
`U.S. Patent No. 8,838,949
`PATENT OWNER’S PROPOSED CONSTRUCTIONS SHOULD BE
`REJECTED
`Attempting to avoid the prior art, Patent Owner proffers constructions that
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`effectively seek to re-write—and narrow—the scope of the challenged claims.
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`Because none of those proposed constructions is grounded in the intrinsic record or
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`otherwise consistent with the broadest reasonable interpretation of the terms, each
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`should be rejected. See 37 C.F.R. § 42.100(b).2
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`A.
`“System Memory”
`Patent Owner asserts that the term “system memory” in independent claims
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`1, 10, 16, 18, 20, and 22 (and dependent claims 2, 4, 5, 8, and 12) should be
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`interpreted to mean “memory that is addressable by the secondary processor.”
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`POR at 9. Petitioner did not ask to construe this term, the Board found it
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`unnecessary in its Institution Decisions to construe this term, 1334 DI at 8; 1335
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`DI at 15; 1336 DI at 8, and Patent Owner itself did not seek a construction of
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`“system memory” in the district court or ITC litigations. See Ex. 1008; Ex. 1024.
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`Nevertheless, to the extent to Board decides to construe this term, Patent Owner’s
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`proposed construction should be rejected for two reasons.
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`2 Because the Board only applies the Phillips standard to IPR petitions filed on or
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`after November 13, 2018, that standard does not apply here.
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`3
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`IPR2018-01334
`U.S. Patent No. 8,838,949
`First, Patent Owner asserts that its proposed construction reflects the plain
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`meaning of “system memory”; yet, it tellingly fails to cite any intrinsic evidence in
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`support of that assertion beyond generic statements in the patent referring to
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`“system memory.” That is because Patent Owner’s construction does not reflect
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`plain meaning; instead, Patent Owner essentially seeks to convert the requirement
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`for “system memory” into just “memory,” such that the limitation could be met by
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`any type of memory addressable by a processor.3 Ex. 1023 [Lin Reply Decl.] ¶11.
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`That improper attempt to re-write the claims should be rejected. See, e.g.,
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`Callicrate v. Wadsworth Mfg., Inc., 427 F.3d 1361, 1369 (Fed. Cir. 2005) (holding
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`that it is improper to read out a limitation of the claims); Unique Concepts, Inc. v.
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`Brown, 939 F.2d 1558, 1562 (Fed. Cir. 1991) (“All the limitations of a claim must
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`be considered meaningful.”).
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`3 For example, Patent Owner’s construction is so broad that it could cover non-
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`volatile memory such as flash memory and read only memory (ROM) addressable
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`by a processor—even though a POSITA would not have considered either to be a
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`type of system memory. System memory is where an executable software image
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`can be loaded and executed. This cannot be done with a non-volatile memory like
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`a flash memory or read only memory (ROM). Ex. 1023 [Lin Reply Decl.] ¶11.
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`4
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`IPR2018-01334
`U.S. Patent No. 8,838,949
`Second, Patent Owner’s proposed construction fails to specify what sets a
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`“system memory” apart from other memories—i.e., that a system memory is where
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`an executable software image can be loaded and executed, as both parties’ experts
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`agree. Ex. 1022 [Rinard Dep.] at 61:9-14 (“Q. Do you agree with Dr. Lin that
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`system memory is memory where programs can be loaded and executed by a
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`processor? A. That’s one of the things that system memory does, that you can do
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`with system memory....”); Ex. 2001 [Lin Dep.] at 25:10-12 (testifying “a system
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`memory would be a portion of the memory where programs could be loaded and
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`executed”); Ex. 1023 [Lin Reply Decl.] ¶12.
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`This is also the same meaning used in the ’949 patent, which consistently
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`describes system memory as the memory where programs (e.g., scatter loaded data
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`segments of an executable software image) are loaded and executed. Ex. 1001,
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`2:61-63 (describing “loading the executable software image directly from the
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`hardware buffer to the system memory”);4 id., 5:48-51 (“The modem Boot ROM
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`code 126 may then jump into that modem executable image 132 and start
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`executing the main modem program from the modem processor RAM 112 [i.e.,
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`system memory]”); id., 8:18-21 (referring to “where the modem image executable
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`data is to be eventually placed into the system memory of the secondary processor
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`4 Emphasis added throughout unless otherwise indicated.
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`5
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`U.S. Patent No. 8,838,949
`305”); id., 9:37-41 (“[T]he executable software image is loaded into the system
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`memory of the secondary processor ….”); id., claim 22 (requiring “scatter
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`load[ing] each received data segment directly to a system memory of the
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`secondary processor; and executing, at the secondary processor, the executable
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`software image”). Indeed, the entire purpose of loading an “executable software
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`image” to target locations in “system memory” in the ’949 patent is so that the
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`executable software image can be executed. Ex. 1023 [Lin Reply Decl.], ¶13.
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`Therefore, because Patent Owner has failed to identify any legitimate basis
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`to depart from that understanding here, to the extent the Board construes the term,
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`it should be defined to mean “memory where an executable software image can be
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`loaded and executed.” Ex. 1023 [Lin Reply Decl.] ¶14.
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`B.
`“Image Header”
`Patent Owner agreed in the district court and ITC litigations that “image
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`header” means “a header associated with the entire image that specifies where the
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`data segments are to be placed in the system memory,” and Patent Owner has
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`adopted the same construction in this proceeding. POR at 12-13; Ex. 1008 at 10;
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`Ex. 1024 at 25. Although Petitioner agrees that construction should apply here,
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`1334 Pet. at 17, the Board has identified three potential issues with this agreed-
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`upon construction.
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`6
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`IPR2018-01334
`U.S. Patent No. 8,838,949
`First, the Board noted that the proposed construction does not provide a
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`separate definition for a “header.” 1334 DI at 7; 1335 DI at 7; 1336 DI at 7. But
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`no party sought a separate construction of that term in either of the litigations (or
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`here) because the term has a well-known plain meaning. See Ex. 1008; Ex. 1024;
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`Ex. 1023 [Lin Reply Decl.] ¶16. Thus, whether the prior art discloses the “header”
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`portion of the limitation is a pure factual issue.
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`Second, the Board found that the “at least one data segment” language of the
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`challenged claims can be met by an executable software image containing just a
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`single data segment, but suggested the plural term “data segments” in the agreed-to
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`construction might require multiple data segments. 1334 DI at 7; 1335 DI at 7;
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`1336 DI at 7. Petitioner agrees that the claims can be met by a single data
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`segment, but disagrees that the agreed-to construction requires multiple data
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`segments. Rather, the plural term simply reflects that if a secondary processor in
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`the claimed system receives multiple data segments, the “image header” must
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`scatter load all of them (plural). In other words, the plural term “data segments” in
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`the agreed-to construction refers to all data segments of an image, whether the
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`image has one or more than one data segment. That said, if the Board believes that
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`clarification is needed, consistent with that understanding, Petitioner would support
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`changing “data segments” in the proposed construction to “one or more data
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`segments.”
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`7
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`IPR2018-01334
`U.S. Patent No. 8,838,949
`Third, the Board stated that the agreed-to construction is unduly narrow to
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`the extent it requires the “image header” to specify where data segments are to be
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`placed in system memory. 1334 DI at 7; 1335 DI at 7; 1336 DI at 7. Petitioner
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`respectfully believes that this requirement is consistent with the ’949 patent’s
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`description of an “image header.” E.g., Ex. 1001, 8:18-21 (“The image header
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`includes information used to identify where the modem image executable data is to
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`be eventually placed into the system memory of the secondary processor 305.”);
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`see 1334 Pet. at 17.
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`Petitioner has shown how the prior art teaches an “image header” under the
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`agreed-upon construction—i.e., a construction that specifies where data segments
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`are to be placed in system memory. 1334 Pet. at 26-35. However, if the Board
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`affirms its initial conclusion that “the image header is perhaps better described as
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`having information that can be used to determine the placement of the at least one
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`data segment in the system memory,” 1334 DI at 8; 1335 DI at 8; 1336 DI at 8, the
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`prior art will even more clearly meet the “image header” limitation under that
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`broader definition.
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`C.
`“Hardware Buffer”
`Patent Owner asserts that the term “hardware buffer” (claims 1, 2, 8, and 12)
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`should be interpreted to mean “a buffer within a hardware transport mechanism
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`that receives data sent from the primary processor to the secondary processor.”
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`8
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`IPR2018-01334
`U.S. Patent No. 8,838,949
`POR at 14. Petitioner did not construe this term, the Board found it unnecessary to
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`construe this term, 1334 DI at 8; 1335 DI at 15; 1336 DI at 8, and Patent Owner
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`did not seek a construction of this term in the district court or ITC proceeding. See
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`Ex. 1008; Ex. 1024. In any event, if the Board decides to construe this term, Patent
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`Owner’s proposed construction should be rejected for two reasons.
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`First, Patent Owner has failed to offer evidence even remotely suggesting
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`that a POSITA would have understood the plain meaning of a “hardware buffer” to
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`require a buffer residing in a “hardware transport mechanism.” Nor has Patent
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`Owner identified any instance in which the intrinsic evidence purports to define a
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`“hardware buffer” in such a specialized, non-plain meaning manner—because
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`there is no such instance.
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`To the contrary, the language of claim 1 merely requires the “hardware
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`buffer” to be part of the “secondary processor”—without requiring it to exist in any
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`specific place within that processor, and without even mentioning a “hardware
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`transport mechanism.” Ex. 1001, claim 1 (“a secondary processor comprising … a
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`hardware buffer”). Further, the specification only uses the term “hardware buffer”
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`twice—(1) when repeating the language of claim 1, Ex. 1001, 2:58-61 (“a
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`secondary processor having … a hardware buffer”), and (2) when describing how,
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`in one embodiment, the “entire” executable software image is not stored in the
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`hardware buffer. Ex. 1001, 9:37-41 (“In one aspect, the executable software image
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`9
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`IPR2018-01334
`U.S. Patent No. 8,838,949
`is loaded into the system memory of the secondary processor without an entire
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`executable software image being stored in the hardware buffer of the secondary
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`processor.”). As such, Patent Owner has no intrinsic support for its attempt to
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`interpret the term “hardware buffer” as requiring a buffer residing in a “hardware
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`transport mechanism.”
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`Second, Patent Owner’s construction relies entirely on the fact that Figure 3
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`of the ’949 patent shows a “Hardware Buffer” within a “Hardware Transport
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`Mechanism.” POR at 14-15. But the specification expressly states that Figure 3 is
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`merely “exemplary,” and Patent Owner has identified no evidence suggesting that
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`the inventors intended to limit the “hardware buffer” of claim 1 to that single
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`example. Ex. 1001, 7:60-63 (“In one aspect of the present disclosure, the loading
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`process is divided into two stages, as illustrated in the exemplary flow shown in
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`FIG. 3.”). Therefore, it would be error to restrict a “hardware buffer” to that
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`embodiment. See Phillips v. AWH Corp., 415 F.3d 1303, 1323 (Fed. Cir. 2005)
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`(“[A]lthough the specification often describes very specific embodiments of the
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`invention, we have repeatedly warned against confining the claims to those
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`embodiments.”). Moreover, the location of the buffer does not characterize the
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`buffer itself, so it does not make sense to construe it in that manner. Ex. 1023 [Lin
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`Reply Decl.] ¶24.
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`10
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`IPR2018-01334
`U.S. Patent No. 8,838,949
`As such, Patent Owner’s unjustified construction should be rejected, and the
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`term “hardware buffer” should be given its ordinary meaning of “a buffer
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`implemented in hardware.” Ex. 1023 [Lin Reply Decl.] ¶25.
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`D.
`“Scatter Loader Controller”
`Patent Owner asserts that the term “scatter loader controller” (claims 1 and
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`2) should be interpreted to mean “a component of a hardware transport mechanism
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`that scatter loads data received from the primary processor directly into the system
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`memory of the secondary processor.” POR at 15. Once again, Petitioner did not
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`construe this term, the Board did not find it necessary to construe this term, 1334
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`DI at 8; 1335 DI at 15; 1336 DI at 8, and Patent Owner did not request a
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`construction of this term in the district court or ITC litigations. See Ex. 1008; Ex.
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`1024.
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`Petitioner continues to believe that no construction of this term is needed.
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`But to the extent the Board decides to construe this term, Patent Owner’s proposed
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`definition should be rejected for the following reasons.
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`First, Patent Owner has offered no evidence that a POSITA would have
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`understood that the plain meaning of a “scatter loader controller” requires a
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`component to necessarily reside in a “hardware transport mechanism.” Nor is
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`Petitioner aware of any such evidence. Rather, a “scatter loader controller” is
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`IPR2018-01334
`U.S. Patent No. 8,838,949
`simply a controller that performs scatter loading, such as “scatter load[ing] each
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`received data segment,” as recited in claim 1. Ex. 1023 [Lin Reply Decl.] ¶28.
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`Second, the plain language of claim 1 does not support Patent Owner’s
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`proposed construction. The claim simply requires the “scatter loader controller” to
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`be part of the “secondary processor,” without identifying any specific location
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`where it must sit within the secondary processor, and without any mention of a
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`“hardware transport mechanism.” Ex. 1001, claim 1 (“a secondary processor
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`comprising … a scatter loader controller”). That is, the location of the scatter
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`loader controller does not characterize the scatter loader controller itself. Ex. 1023
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`[Lin Reply Decl.] ¶29.
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`Third, nothing in the specification purports to define or otherwise require
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`the claimed “scatter loader controller” to have the narrow meaning that Patent
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`Owner proposes here (but did not propose in either litigation). See Ex. 1008; Ex.
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`1024. And although Figure 3 shows controller 304 in a box labelled “Hardware
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`Transport Mechanism,” it would be error to limit the claims to that single
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`“exemplary” embodiment for the same reasons discussed above for the “hardware
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`buffer” limitation. Phillips, 415 F.3d at 1323.
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`Petitioner respectfully submits that it is not necessary to construe the term
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`“scatter loader controller,” and that claim 1 sufficiently sets forth what the scatter
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`U.S. Patent No. 8,838,949
`loader controller must do—i.e., “load the image” and “scatter load each received
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`data segment.”5 Ex. 1001, claim 1.
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`E. Means-Plus-Function Limitations
`In the IPR2018-01335 proceeding, Petitioner proposed constructions for four
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`means-plus-function terms recited in claim 16. 1335 Pet. at 18-22. In its
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`Institution Decision, the Board agreed that each of these terms is a means-plus-
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`function limitation and agreed with Petitioner’s identification of the claimed
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`function. 1335 DI at 13.
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`For the “means for processing …” and “means for scatter loading …”
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`clauses, however, the Board found that the cited portions of the specification
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`included insufficient structure to perform the claimed functions. 1335 DI at 14.
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`5 Neither the parties nor the Board in its institution decisions proposed construing
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`“scatter loader controller” as a means-plus-function term. Nor is such a
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`construction required, because controllers, including those that perform scatter
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`loading, are conventional computer components with known structures. Telcordia
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`Techs., Inc. v. Cisco Sys., Inc., 612 F.3d 1365, 1376–77 (Fed.Cir.2010) (holding
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`that “controller ” was sufficient disclosure because “[t]he record shows that an
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`ordinary artisan would have recognized the controller as an electronic device with
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`a known structure”).
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`IPR2018-01334
`U.S. Patent No. 8,838,949
`The Board encouraged the parties to address this issue, including the impact on this
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`proceeding if the Board determines that the ’949 specification provides inadequate
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`corresponding structure for the recited functions. 1335 DI at 14-15. Petitioner
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`addresses these issues below.
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`First, Patent Owner disagrees with the Board and supports Petitioner’s
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`proposed constructions—which are the same constructions that Patent Owner
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`proposed in the ITC proceeding. POR at 18-21; Ex. 1008 at 4-6. Upon
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`consideration of the Board’s articulated concerns, Petitioner agrees that the ’949
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`specification fails to disclose sufficient structure to perform the recited functions—
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`which is the same position that Apple took for these terms in the ITC investigation.
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`Ex. 1008 at 4-6.
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`Second, despite these deficiencies, Petitioner agrees with Patent Owner that
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`“[n]one of the arguments Qualcomm makes [in its Response] to distinguish the
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`prior art requires construction of these [means-plus-function] limitations.” POR at
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`17. Accordingly, the Board can address in this proceeding whether claim 16 is
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`invalid in view of the asserted prior art. See Apple Inc. v. Valencell Inc., No.
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`IPR2017-00315, Paper 45 at 47 (P.T.A.B. May 31, 2018) (“Although we agree that
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`IPR2018-01334
`U.S. Patent No. 8,838,949
`the proposed substitute claims are indefinite, we consider Petitioner’s arguments
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`that the proposed substitute claims are unpatentable over the prior art.”).6
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`III. CLAIMS 1-23 ARE OBVIOUS
`As the Board preliminarily found, Petitioner has demonstrated that the
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`challenged claims7 are unpatentable in view of the combination of Svensson and
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`Bauer, or alternatively, in view of the combination of Bauer and Svensson with one
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`or more of Kim, Zhao, and Lim:
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`(1) Svensson teaches a multi-processor system in which a program loader
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`can transfer an executable software image from a memory of a primary processor
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`to system memory of a secondary processor via an intermediate hardware buffer;
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`(2) Bauer discloses an executable software image format for use with
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`Svensson’s system that contains one or more data segments and a header portion
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`6 Although Apple Inc. v. Valencell Inc. addresses proposed substitute claims, it is
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`instructive because—like here, where the Patent Owner concedes that none of its
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`arguments turn on the means-plus-function terms—the Board was able to apply the
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`prior art to the (otherwise indefinite) claims.
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`7 The Board did not reach a preliminary conclusion as to claim 16 because it of its
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`questions about the sufficiency of the corresponding structure, as noted above.
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`1335 DI at 13-15. See supra, §II.E.
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`15
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`IPR2018-01334
`U.S. Patent No. 8,838,949
`specifying where each data segment should be loaded for execution, and also
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`teaches having a secondary processor receive the header portion separately from
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`the data segments;
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`(3) Kim confirms that having a processor separately receive the header
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`and data segment portions of an executable software image was known in the prior
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`art; and
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`(4) Zhao and Lim confirm that conventional components such as modem
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`processors and primary processor file systems were known. 1334 DI at 29; 1335
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`DI at 37; 1336 DI at 31. Therefore, each challenged claim should be cancelled as
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`obvious.
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`In its Response, Patent Owner advances a host of arguments, none of which
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`has merit. For example, Patent Owner argues that a POSITA would not have been
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`motivated to combine Svensson and Bauer—even though the references share the
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`same inventors and much of the same disclosure, and Bauer expressly states that
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`its invention was specifically designed for use with Svensson’s system. Patent
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`Owner also maintains that, even if combined, the prior art still fails to teach
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`multiple limitations. But many of those arguments depend on flawed claim
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`construction positions that fail for the reasons stated above (and under which
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`Petitioner has established invalidity in any event). And Patent Owner’s other
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`16
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`U.S. Patent No. 8,838,949
`arguments depend on an incomplete and inaccurate reading of the asserted prior art
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`references that simply cannot be squared with the references’ actual disclosures.
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`Accordingly, because Patent Owner has presented no reason for the Board to
`
`depart from its preliminary conclusion that the challenged claims are obvious in
`
`view of the asserted prior art, the Board should reach the same conclusion here and
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`find that the claims are not patentable.
`
`A.
`
`Patent Owner Cannot Escape Invalidity Based On The
`Petitioner’s Use Of The Phrase “Bauer and Svensson Combined”
`Patent Owner argues that Petitioner has failed to demonstrate invalidity
`
`because the Petitions refer to Bauer and Svensson collectively using the phrase
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`“Bauer and Svensson combined.” POR at 35-37. But as the Board previously
`
`found, and as explained in the Petitions, that label is merely shorthand used to
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`reflect the fact that Bauer and Svensson contain significant overlap in their
`
`disclosures. 1334 DI at 16 (Board observing that “[b]ased on the interrelatedness
`
`of the references, Petitioner refers to the teachings of ‘Bauer and Svensson
`
`combined’”); 1334 Pet. at 24-25 (explaining shorthand use of term).
`
`Moreover, despite Patent Owner’s claims to the contrary, the Petitions
`
`identify the specific disclosures that Petitioner is relying on from each reference, as
`
`well as their key respective differences, as Patent Owner elsewhere admits in its
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`Response—i.e., that Bauer does not describe the multiprocessor system with the
`
`same level of detail as Svensson, and that Svensson does not disclose the improved
`
`17
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`IPR2018-01334
`U.S. Patent No. 8,838,949
`file format introduced in Bauer. E.g., 1334 Pet. at 24-25 (“Bauer does not describe
`
`the multiprocessor system with the same level of detail as Svensson.”); id. at 30-31
`
`(describing the multi-processor system “as described in Svensson, using Bauer’s
`
`file format”); id. at 33 (explaining how “Bauer expressly cites to Svensson as one
`
`example of a program loader that can load data using the invention described in
`
`Bauer.”); POR at 61 (“Recognizing that ‘Bauer does not explicitly describe the
`
`loading process from the primary processor to the secondary processor in much
`
`detail’ (Paper 3 at 33), Petitioner generally relies on Svensson as disclosing how
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`data would be loaded in the described multi-processor system.”).
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`In addition, each time the petitions use the phrase “Bauer and Svensson
`
`combined,” the petitions cite specific disclosures from Bauer, Svensson, or Bauer
`
`and Svensson, so that Patent Owner knows exactly what Petitioner relies on as
`
`teaching each claim limitation. E.g., 1334 Petition at 25-26 (using term “Bauer
`
`and Svensson combined” for the preamble of claim 1 and citing specific
`
`disclosures from each reference); id. at 26-27 (using term “Bauer and Svensson
`
`combined” and citing specific disclosures for each reference for the “secondary
`
`processor” limitation); id. at passim.
`
`Thus, Patent Owner has identified no legitimate basis to conclude that
`
`Petitioner somehow attempted to hide its true positions, or otherwise failed to meet
`
`its disclosure obligations, with respect to the prior art.
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`18
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`

`

`B.
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`IPR2018-01334
`U.S. Patent No. 8,838,949
`Petitioner Has Established That A POSITA Would Have Been
`Motivated To Combine Bauer And Svensson
`Patent Owner suggests that a POSITA would not have been motivated to
`
`combine Bauer and Svensson in the manner that Petitioner has proposed. POR at
`
`37. That argument fails for several reasons.
`
`First, Bauer and Svensson are closely interrelated; as Petitioner previously
`
`explained, the two references were filed just four months apart, and they both share
`
`the same inventors, same assignee, same figures, and much of the same disclosure.
`
`1334 Pet. at 23-25. This significant overlap alone weighs strongly in favor of
`
`finding a motivation to combine the two references. See, e.g., Plantronics, Inc. v.
`
`Aliph, Inc., 724 F.3d 1343, 1354 (Fed. Cir. 2013) (“[M]otivation to combine may
`
`be found explicitly or implicitly in … the ‘interrelated teachings of multiple
`
`patents.’”) (quoting Perfect Web Techs., Inc. v. InfoUSA, Inc., 587 F.3d 1324,
`
`1328-29 (Fed. Cir. 2009) (quoting KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398,
`
`418-21, (2007))).
`
`Second, Patent Owner’s lack of motivation to combine arguments are
`
`particularly untenable given that Bauer explicitly describes its file format as an
`
`improvement over Svensson’s format, and explicitly states that the new file format
`
`can be used with Svensson’s program loader and multi-processor system. 1334
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`Pet. at 23-24; Ex. 1009, cover ¶¶27, 31-36, 43, Figs. 1A-1C, 2; Ex. 1010, cover,
`
`Fig. 1, 3:49-4:8; Ex. 1002, ¶¶102-04; DI at 15 (“Bauer expressly cites Svensson’s
`
`19
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`IPR2018-01334
`U.S. Patent No. 8,838,949
`program loader as an example of a program loader that can use the file format
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`disclosed in Bauer.”); POR at 37 (Patent Owner admitting “it is conceivable that
`
`the POSA would be motivated to combine Bauer and Svensson”).
`
`Indeed, it is difficult to imagine a more compelling basis to find that a
`
`motivation to combine references exists than where the references themselves
`
`suggest the combination—as is the case here. See Bayer Pharma AG v. Watson
`
`Labs., Inc., 874 F.3d 1316, 1328-29 (Fed. Cir. 2017) (finding “prior art was
`
`explicit in the suggestion to make such a combination” and that “[t]he repeated
`
`suggestion … [was] strong evidence of a motivation to make the claimed
`
`combination.”).
`
`
`
`Finally, Patent Owner’s argument is undermined by its own expert, Dr.
`
`Rinard, who testified that a person of ordinary skill in the art would have combined
`
`these two references:
`
`Q. Do you agree with me that a person of ordinary skill in the
`
`art would co