Paper 10
`Trials@uspto.gov
`571-272-7822 Entered: March 18, 2019
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`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`
`
`
`
`INTEL CORPORATION,
`Petitioner,
`
`v.
`
`QUALCOMM INCORPORATED,
`Patent Owner.
`
`____________
`
`Case IPR2018-01336
`Patent 8,838,949 B2
`____________
`
`
`Before TREVOR M. JEFFERSON, DANIEL J. GALLIGAN, and
`AARON W. MOORE, Administrative Patent Judges.
`
`GALLIGAN, Administrative Patent Judge.
`
`
`
`
`
`
`DECISION
`Institution of Inter Partes Review
`35 U.S.C. § 314
`
`
`
`
`Trials@uspto.gov
`571-272-7822 Entered: March 18, 2019
`
`
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`
`
`
`
`INTEL CORPORATION,
`Petitioner,
`
`v.
`
`QUALCOMM INCORPORATED,
`Patent Owner.
`
`____________
`
`Case IPR2018-01336
`Patent 8,838,949 B2
`____________
`
`
`Before TREVOR M. JEFFERSON, DANIEL J. GALLIGAN, and
`AARON W. MOORE, Administrative Patent Judges.
`
`GALLIGAN, Administrative Patent Judge.
`
`
`
`
`
`
`DECISION
`Institution of Inter Partes Review
`35 U.S.C. § 314
`
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`
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`IPR2018-01336
`Patent 8,838,949 B2
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`I. INTRODUCTION
`Intel Corporation (“Petitioner”) filed a Petition requesting inter partes
`review of claims 18–21 of U.S. Patent No. 8,838,949 B2 (“the ’949 patent,”
`Ex. 1201). Paper 3 (“Pet.”). Qualcomm Incorporated (“Patent Owner”)
`filed a Preliminary Response. Paper 7 (“Prelim. Resp.”). Under 37 C.F.R.
`§ 42.4(a), we have authority to determine whether to institute review.
`The standard for instituting an inter partes review is set forth in
`35 U.S.C. § 314(a), which provides that an inter partes review may not be
`instituted unless the information presented in the Petition and the
`Preliminary Response shows “there is a reasonable likelihood that the
`petitioner would prevail with respect to at least 1 of the claims challenged in
`the petition.”
`After considering the Petition, the Preliminary Response, and
`associated evidence, we institute an inter partes review as to all challenged
`claims and on all grounds raised in the Petition.
`A. Related Matters
`As required by 37 C.F.R. § 42.8(b)(2), each party identifies various
`judicial or administrative matters that would affect or be affected by a
`decision in this proceeding. Pet. 2–3; Paper 4, 2. Among those related
`matters are IPR2018-01334 and IPR2018-01335, each of which involves
`different claims of the ’949 patent.
`B. Real Parties in Interest
`Petitioner identifies itself and Apple Inc. as real parties in interest.
`Pet. 2.
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`C. The ’949 Patent and Illustrative Claim
`The ’949 patent generally relates to loading software from one
`processor to another in a multi-processor system. Ex. 1201, at [57]. One
`example disclosed in the ’949 patent involves loading modem image
`executable data by first retrieving and processing an image header, which
`“includes information used to identify where the modem image executable
`data is to be eventually placed into the system memory of the secondary
`processor.” Ex. 1201, 8:9–21. Figure 3 of the ’949 patent is reproduced
`below.
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`Figure 3 shows “operational flow for an exemplary loading process for
`loading an executable image from a primary processor to a secondary
`processor according to one aspect of the present disclosure.” Ex. 1201,
`4:10–13. Referring to various components depicted in Figure 3, the ’949
`patent discloses the following:
`The header information is used by the secondary processor 302
`to program the scatter loader/direct memory access controller
`304 receive address when receiving the actual executable data.
`Data segments are then sent from system memory 307 to the
`primary hardware transport mechanism 308. The segments are
`then sent from the hardware transport mechanism 308 of the
`primary processor 301 to a hardware transport mechanism 309
`of
`the
`secondary processor 302 over an
`inter-chip
`communication bus 310 (e.g., a HS-USB cable.) The first
`segment transferred may be the image header, which contains
`information used by the secondary processor to locate the data
`segments into target locations in the system memory of the
`secondary processor 305. The image header may include
`information used to determine the target location information for
`the data.
`Ex. 1201, 8:21–35.
`Challenged claims 18 and 20 are independent claims, and claim 18 is
`reproduced below.
`18. A multi-processor system comprising:
`a primary processor coupled with a first non-volatile
`memory, the first non-volatile memory coupled to the primary
`processor and storing a file system for the primary processor and
`executable images for the primary processor and secondary
`processor;
`a secondary processor coupled with a second non-volatile
`memory, the second non-volatile memory coupled to the
`secondary processor and storing configuration parameters and
`file system for the secondary processor; and
`an interface communicatively coupling the primary
`processor and the secondary processor, an executable software
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`image being received by the secondary processor via the
`interface, the executable software image comprising an image
`header and at least one data segment, the image header and each
`data segment being received separately, and the image header
`being used to scatter load each received data segment directly to
`a system memory of the secondary processor.
`
`
`D. References
`Petitioner relies upon the following references:
`US 2006/0288019 A1 Dec. 21, 2006
`Bauer
`
`Lim
`
`US 7,203,829 B2
`
`Apr. 10, 2007
`
`Svensson
`
`US 7,356,680 B2
`
`Apr. 8, 2008
`
`Kim
`
`Korean Publication 10-
`2002-0036354
`
`May 16, 2002
`
`Ex. 1209
`
`Ex. 1214
`
`Ex. 1210
`
`Exs. 1211,
`12121
`
`E. Asserted Ground of Unpatentability
`Petitioner asserts claims 18–21 of the ’949 patent are unpatentable
`under 35 U.S.C. § 103 as obvious over the combined teachings of Bauer,
`Svensson, Kim, and Lim. Pet. 26–75.
`
`
`II. ANALYSIS
`A. Claim Construction
`In an inter partes review for a petition filed before November 13,
`2018, a claim in an unexpired patent shall be given its broadest reasonable
`construction in light of the specification of the patent in which it appears.
`37 C.F.R. § 42.100(b) (2018); see Changes to the Claim Construction
`
`
`1 In this Decision, we cite Exhibit 1212, which is the English translation of
`Kim provided by Petitioner.
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`Standard for Interpreting Claims in Trial Proceedings Before the Patent Trial
`and Appeal Board, 83 Fed. Reg. 51,340 (Oct. 11, 2018) (amending
`37 C.F.R. § 42.100(b) effective November 13, 2018). In applying a broadest
`reasonable construction, claim terms generally are given their ordinary and
`customary meaning, as would be understood by one of ordinary skill in the
`art in the context of the entire disclosure. See In re Translogic Tech., Inc.,
`504 F.3d 1249, 1257 (Fed. Cir. 2007). This presumption may be rebutted
`when a patentee, acting as a lexicographer, sets forth an alternate definition
`of a term in the specification with reasonable clarity, deliberateness, and
`precision. In re Paulsen, 30 F.3d 1475, 1480 (Fed. Cir. 1994).
`1. Image Header
`Petitioner argues the term “image header” means “a header associated
`with the entire image that specifies where the data segments are to be placed
`in the system memory.” Pet. 17–18 (citing Ex. 1201, 7:50–52, 8:18–21,
`9:23–24, 10:6, claim 10; Ex. 1208, 3; Ex. 1202 ¶ 77). Patent Owner does
`not address Petitioner’s proposed construction, but Petitioner notes that
`Patent Owner agreed to this proposed construction in an investigation
`involving the ’949 patent at the International Trade Commission (“ITC”).2
`Pet. 18 (citing Ex. 1208, 3).
`For the purpose of deciding whether to institute inter partes review on
`the present record, we need not determine the full scope of this term. See
`Nidec Motor Corp. v. Zhongshan Broad Ocean Motor Co., 868 F.3d 1013,
`1017 (Fed. Cir. 2017) (only those claim terms in controversy need to be
`construed, and only to the extent necessary to resolve the controversy).
`
`
`2 In re Certain Mobile Elec. Devices and Radio Frequency and Processing
`Components Thereof, Inv. No. 337-TA-1065.
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`Rather, to determine whether Petitioner has made a sufficient unpatentability
`showing for purposes of institution, we need only determine whether the
`scope of this term encompasses elements found in the prior art.
`Nevertheless, to provide guidance to the parties during trial, we note that
`Petitioner’s proposed construction is problematic for at least three reasons.
`First, this definition does not explain what a “header” itself is or what data
`must be present for something to be considered a header, if any at all. The
`significance of this issue will become evident in the discussion below
`concerning the teachings of the prior art. Second, Petitioner’s proposed
`construction recites “data segments,” suggesting that plural data segments
`are required, but the claims recite “at least one data segment” and, therefore,
`are met by only a single data segment. Third, requiring the image header to
`“specif[y] where the data segments are to be placed in the system memory”
`appears to narrow the term unduly. Claim 18, for example, recites “the
`image header being used to scatter load each received data segment directly
`to a system memory of the secondary processor.” The ’949 patent discloses
`that “[t]he image header includes information used to identify where the
`modem image executable data is to be eventually placed into the system
`memory of the secondary processor 305.” Ex. 1201, 8:18–21. The ’949
`patent further discloses the following: “In one aspect, the target locations
`are not predetermined, but rather are determined by software executing in
`the secondary processor as part of the scatter loading process. Information
`from the image header may be used to determine the target locations.” Ex.
`1201, 8:36–40. The claims and the specification of the ’949 patent,
`therefore, contemplate image headers that provide information used to
`determine where to load data in memory, even if the image headers do not
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`“specif[y] where the data segments are to be placed in the system memory.”
`Thus, the image header is perhaps better described as having information
`that can be used to determine the placement of the at least one data segment
`in the system memory.
`Based on the foregoing, we are not persuaded Petitioner’s proposed
`construction of “image header” is the broadest reasonable interpretation
`consistent with the specification of the ’949 patent. Petitioner’s proposed
`construction is merely one example of such an image header. See, e.g.,
`Ex. 1201, 7:50–52 (describing “one aspect” in which “[t]he image header
`also specifies the destination address of the image in target memory”).
`Thus, we do not adopt Petitioner’s proposed construction. For purposes of
`this Decision, however, we determine that Petitioner’s proposed construction
`because within the broadest reasonable interpretation of “image header.”
`During the trial, the parties are encouraged to address this issue further if
`they deem it relevant to the disputed issues.
`2. Remaining Terms
`For purposes of this Decision, we do not find it necessary to construe
`expressly any other claim terms. See, e.g., Nidec, 868 F.3d at 1017 (“[W]e
`need only construe terms ‘that are in controversy, and only to the extent
`necessary to resolve the controversy’ . . . .” (quoting Vivid Techs., Inc. v.
`Am. Sci. & Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir. 1999))).
`B. Principles of Law
`A patent claim is unpatentable under 35 U.S.C. § 103(a) if the
`differences between the claimed subject matter and the prior art are such that
`the subject matter, as a whole, would have been obvious at the time the
`invention was made to a person having ordinary skill in the art to which said
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`subject matter pertains. KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 406
`(2007). The question of obviousness is resolved on the basis of underlying
`factual determinations including: (1) the scope and content of the prior art;
`(2) any differences between the claimed subject matter and the prior art;
`(3) the level of ordinary skill in the art; and (4) any secondary
`considerations, if in evidence.3 Graham v. John Deere Co., 383 U.S. 1, 17–
`18 (1966).
`C. Alleged Obviousness over Bauer, Svensson, Kim, and Lim
`(Claims 18–21)
`Petitioner asserts claims 18–21 of the ’949 patent are unpatentable
`under 35 U.S.C. § 103 as obvious over the combined teachings of Bauer,
`Svensson, and Kim. Pet. 26–75. For purposes of determining whether to
`institute, we focus on Petitioner’s contentions with respect to independent
`claim 18, and, in our analysis of claim 18, we address all of the arguments
`made in the Preliminary Response.
`1. Svensson
`Svensson describes a multi-processor system in which data are sent
`from a host processor to a client processor. Ex. 1210, at [57]. Figure 1 of
`Svensson is reproduced below.
`
`
`3 Patent Owner does not present arguments or evidence of such secondary
`considerations in the Preliminary Response.
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`Figure 1 depicts multi-processor system 100 having host processor 102 and
`client processor 104. Ex. 1210, 3:49–50. Client processor 104 is the
`processor for a digital signal processor (DSP) device. Ex. 1210, 3:54–58.
`As Svensson explains, “[m]ost commercially available DSP devices include
`on-chip memories, and as indicated in FIG. 1, the DSP includes ‘internal’
`single-access RAM (SARAM) and dual-access RAM (DARAM) 108, as
`well as an ‘external’ RAM (XRAM) 110.” Ex. 1210, 3:64–4:1. Svensson
`explains that “XRAM 110 is invisible to, i.e., not accessible by, the CPU
`102,” whereas CPU 102 can access “internal” SARAM and DARAM 108.
`Ex. 1210, 4:5–8, 4:13–14. DSP processor 104 can access both RAMs 108
`and 110. Ex. 1210, 4:7–8.
`Because host processor 102 cannot access XRAM 110, Svensson
`discloses a technique for sending data from host processor 102 to be stored
`in XRAM 110. Ex. 1210, Fig. 2, 4:15–6:11, 7:7–8. Svensson’s Figure 2 is
`reproduced below.
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`Figure 2 is a flow chart of Svensson’s bootloader operation. Ex. 1210, 3:34,
`4:15–19. In step 212, a block of memory in “internal” memory 108 is
`reserved as an intermediate storage area (ISA) for data that are being sent
`from the host to the invisible memory of the client processor. Ex. 1210,
`5:21–28. After the host transfers data to the ISA (step 216), the host tells the
`client the ISA has been loaded and indicates whether more data are coming
`(step 218). Ex. 1210, 5:53–63. The client then copies the data from the ISA
`to its “invisible” memory (step 220) and responds to the host when copying
`is finished (step 222). Ex. 1210, 5:63–6:3. “If there is more code and/or
`data to load (Step 224), this cycle of copying and messaging (Steps 216-224)
`can be repeated as many times as required.” Ex. 1210, 6:4–6.
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`2. Bauer
`Bauer discloses the file format depicted in Figures 1A, 1B, and 1C,
`which are reproduced below.
`
`
`Figure 1A shows the format for a data image, Figure 1B shows the header of
`the data image, and Figure 1C shows the section information of the data
`image. Ex. 1209 ¶¶ 21–23. As shown in Figure 1A, binary data image 100
`has header 102, section information 104, and section data 106. Ex. 1209
`¶ 32. Each section of data in section data 106 has a section information
`entry in section information 104, two of which are depicted in Figure 1C as
`entries 104-1 and 104-2. Ex. 1209 ¶ 34. Each section information entry
`indicates the length (108) and load address (110) for its respective section
`data. Ex. 1209 ¶ 34. Additional information about a section may be
`included in extra information element 112. Ex. 1209 ¶ 34.
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`According to Bauer, “[h]aving all section information entries 104
`collected together in the image 100 advantageously simplifies system
`navigation through the image, and having all section data arranged in a
`sequence makes it possible to optimize loading of the sections.” Ex. 1209
`¶ 38. Bauer explains that “[t]here are many possible applications of this
`format and its individually coded sections,” including “[o]bject code and
`data . . . with a program loader reading the stored information and
`processing stored sections accordingly.” Ex. 1209 ¶ 31. “One example of
`such a program loader is described in U.S. patent application Ser. No.
`11/040,798 filed on Jan. 22, 2005, by M. Svensson et al. for ‘Operating-
`System-Friendly Bootloader.’” Ex. 1209 ¶ 31. This is the application that
`issued as Svensson. Svensson’s Figure 1 depicts the same multi-processor
`system as Bauer’s Figure 2, which Bauer says “can advantageously use a
`binary image 100 having the format depicted in FIGS. 1A, 1B, 1C.”
`Ex. 1209 ¶ 35; compare Ex. 1210, Fig. 1, with Ex. 1209, Fig. 2.
`3. Kim
`Kim discloses a system in which a system startup loader in a system
`management processor provides program blocks to multiple other processors
`in a system. Ex. 1212, 4:8–21, Fig. 1. Figure 3 of Kim is reproduced below.
`
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`Figure 3 is a flowchart showing a procedure for loading program blocks
`from the system startup loader to other processors in the system. Ex. 1212,
`5:9–11. In step S304, the booter in a processor requests program block
`header information, which the system startup loader provides in step S305.
`Ex. 1212, 5:18–21. When the header is received, the booter requests a
`program block in step S307, which the system startup loader provides in step
`S309. Ex. 1212, 5:21–24. If there are more blocks to be received, the
`booter returns to step S304. Ex. 1212, 6:2–4.
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`4. Lim
`Lim is directed to initializing a coprocessor in a system having a main
`processor and a coprocessor. Ex. 1214, [57], 1:21–25. Lim discloses
`various memories coupled to the main processor and the coprocessor that
`can store boot programs and file systems. See, e.g., Ex. 1214, 5:47–58. 6:2–
`7, 6:39–42, Figs. 1, 3.
`
`5. Independent Claim 18
`a. Primary Processor
`Independent claim 18 is directed to a “multi-processor system” having
`“a primary processor coupled with a first non-volatile memory, the first non-
`volatile memory coupled to the primary processor and storing a file system
`for the primary processor and executable images for the primary processor
`and secondary processor.” Figure 2 of Bauer is reproduced below.
`
`Figure 2 of Bauer depicts multi-processor system 200 having host
`processor 202 and client processor 204. Ex. 1209 ¶ 35. In Figure 2, host
`processor 202 is an advanced RISC (reduced instruction set computer)
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`machine (ARM) central processing unit (CPU), and client processor 204 is a
`DSP CPU. Ex. 1209 ¶ 35. As noted above, Svensson’s Figure 1 and
`Bauer’s Figure 2 depict the same multi-processor system.
`In its obviousness contentions, Petitioner argues a person of ordinary
`skill in the art would have been motivated to combine the teachings of Bauer
`and Svensson because, among other reasons, Bauer expressly cites
`Svensson’s program loader as an example of a program loader that can use
`the file format disclosed in Bauer. Pet. 27 (citing Ex. 1209 ¶ 31; Ex. 1202
`¶¶ 101–102); see Ex. 1209 ¶ 31 (“One example of such a program loader is
`described in U.S. patent application Ser. No. 11/040,798 filed on Jan. 22,
`2005, by M. Svensson et al. for ‘Operating-System-Friendly Bootloader.’”).
`Based on the interrelatedness of the references, Petitioner refers to the
`teachings of “Bauer and Svensson combined.” Pet. 27–28.
`Referring to Bauer’s Figure 2, Petitioner contends the ARM device
`coupled to non-volatile memory 206 teaches the claimed “primary processor
`coupled with a first non-volatile memory” and the DSP device teaches the
`claimed “secondary processor.” Pet. 30. Citing various teachings of Bauer
`and Svensson, including Svensson’s disclosure of an “internal file system of
`the host” (Ex. 1210, 7:49–50), Petitioner argues the combination of Bauer
`and Svensson teaches the first non-volatile memory “storing a file system for
`the primary processor.” Pet. 30–31 (citing Ex. 1209 ¶¶ 3, 109; Ex. 1210,
`7:47–51; Ex. 1202 ¶ 109). Dr. Lin testifies as follows:
`The person of ordinary skill in the art would also understand that
`the file system would need to remain in memory regardless of
`whether power is applied, and thus would need to be stored in a
`non-volatile memory coupled to the primary processor (such as
`disclosed in Bauer and Svensson combined), rather than to use a
`volatile memory. Accordingly, the person of ordinary skill in the
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`art would understand that Bauer and Svensson combined teaches
`a file system for the primary processor (ARM device) that would
`be stored in the first non-volatile memory.
`Ex. 1202 ¶ 109. On this record, we are persuaded that the combination of
`Bauer and Svensson teaches “a primary processor coupled with a first non-
`volatile memory, the first non-volatile memory coupled to the primary
`processor and storing a file system for the primary processor.”
`Petitioner argues that the non-volatile memory coupled to the ARM
`CPU stores executable software for the DSP device and, therefore, that the
`combination of Bauer and Svensson teaches the non-volatile memory storing
`executable images for the secondary processor. Pet. 31–32 (citing Ex. 1209
`¶¶ 11, 30–32, 35–36, Fig. 2; Ex. 1210, 1:11–15, 2:11–15, 4:9–28, 4:31–35,
`4:38–41, 6:12–15, 6:19–23, Figs. 1, 3; Ex. 1202 ¶¶ 110–112). For example,
`Svensson discloses the following:
`The SARAM and DARAM 108 [of the DSP device] can
`be loaded from the non-volatile memory 106 [of the ARM
`device] by the trivial “push” method. When code needs to be
`loaded to the XRAM 110 during boot, however, a bootloader
`solution is required because the XRAM 110 is invisible to, i.e.,
`not accessible by, the CPU 102 and so boot code cannot be
`pushed to the XRAM 110.
`Ex. 1210, 4:9–14 (emphasis added).
`Petitioner also argues that the non-volatile memory coupled to the
`ARM CPU stores executable software for the ARM device and, therefore,
`that the combination of Bauer and Svensson teaches the non-volatile
`memory storing executable images for the primary processor. Pet. 33 (citing
`Ex. 1210, 8:3–8, Fig. 1; Ex. 1202 ¶¶ 113–114). Svensson discloses that
`“[t]he host is fully running when the slave is booted or re-rebooted,” and
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`Svensson refers to “execution of the host processor software.” Ex. 1210,
`8:3–8. Dr. Lin testifies as follows:
`A person of ordinary skill in the art would understand from this
`teaching that the primary processor software, because it is
`executed,
`includes “executable
`images” for
`the primary
`processor, and further that the primary processor software would
`be stored in the first non-volatile memory coupled to the primary
`processor.
`Ex. 1202 ¶ 113.
`On this record, we are persuaded that the combination of Bauer and
`Svensson teaches “the first non-volatile memory coupled to the primary
`processor and storing . . . executable images for the primary processor and
`secondary processor.”
`Petitioner additionally argues that, “[t]o the extent the Patent Owner
`contends that Bauer and Svensson combined does not teach the first non-
`volatile memory ‘storing a file system for the primary processor,’ or ‘storing
`… executable images for the primary processor and secondary processor,’
`Lim expressly teaches these features.” Pet. 33–34; see id. at 34–39
`(explaining obviousness contention based on Lim’s teachings). At this stage
`of the proceeding, Patent Owner does not make this argument. See
`generally Prelim. Resp. Nevertheless, we have reviewed Petitioner’s
`contentions relying on Lim for this claim limitation, and we find them
`persuasive on this record.
`On this record, therefore, we are persuaded by Petitioner’s contention
`that the subject matter of “a primary processor coupled with a first non-
`volatile memory, the first non-volatile memory coupled to the primary
`processor and storing a file system for the primary processor and executable
`images for the primary processor and secondary processor” would have been
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`obvious based on the combined teachings of Bauer and Svensson and also
`based on the combined teachings of Bauer, Svensson, and Lim.
`b. Secondary Processor
`Independent claim 18 further recites “a secondary processor coupled
`with a second non-volatile memory, the second non-volatile memory
`coupled to the secondary processor and storing configuration parameters and
`file system for the secondary processor.” Citing Lim’s disclosure of storing
`initialization information, including a boot program and a file system, for a
`coprocessor in a flash memory, Petitioner argues Lim teaches a “second
`non-volatile memory coupled to the secondary processor and storing
`configuration parameters and file system for the secondary processor.”
`Pet. 39–41 (citing Ex. 1214, 1:42–47, 2:3–13, 5:23–25, 5:43–6:7, 6:28–30,
`7:27–33, 7:41–47, 7:53–55, 10:12–18, 11:10–16, Figs. 1, 3; Ex. 1202
`¶¶ 125–127). For example, Lim discloses the following:
`The embodiments of the present invention remove a flash
`memory for storing initialization information of a coprocessor
`from a system, the system including a main processor and the
`coprocessor, and stores
`initialization
`information of
`the
`coprocessor in either another memory of the coprocessor, or a
`memory of the main processor, such that the system initialization
`is established. The memory can be either one of a ROM, a RAM,
`first and second flash memories, and similar devices. The
`initialization information can be either one of a boot program
`module, a loader program, a boot loader program, and a tiny
`flash file system of the coprocessor.
`Ex. 1214, 5:47–58 (emphases added). Lim further discloses that
`“[i]nitialization information of the auxiliary device, for example, a boot
`program, a loader program, a boot-loader program, and tiny flash file
`systems, can be stored in an internal ROM of the coprocessor.” Ex. 1214,
`6:2–5. Dr. Lin testifies as follows:
`
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`A person of ordinary skill in the art would understand from
`Lim’s teaching that the initialization information includes, in
`addition to a file system, “configuration parameters” for the
`secondary processor (coprocessor). In particular, the person of
`ordinary skill in the art would understand that the initialization
`information, such as the boot, loader and boot-loader programs,
`includes data needed to configure and initialize the secondary
`processor during the boot process. The person of ordinary skill
`in the art would understand this well-known type of data to be
`“configuration parameters.”
`Ex. 1202 ¶ 128.
`Petitioner argues a person of ordinary skill in the art would have been
`motivated to combine the teachings of Bauer and Svensson with Lim’s
`teachings of storing configuration parameters and a file system for a
`secondary processor in a non-volatile memory coupled to the secondary
`processor because the person of ordinary skill in the art
`would . . . have understood that (1) configuration parameters
`were necessary to configure and initialize a processor during the
`boot process as taught by Lim, and (2) file systems were
`necessary to control how file formats such as COFF [(Common
`Object File Format)] and ELF [(Executable and Linking
`Format)] are stored and retrieved from memory as taught by
`Bauer and Svensson combined.
`Pet. 44 (citing Ex. 1202 ¶ 133).
`On this record, we are persuaded Petitioner has presented sufficient
`reasons to combine the teachings of Bauer, Svensson, and Lim, and we are
`persuaded Petitioner has shown sufficiently for the purposes of institution
`that the combination of Bauer, Svensson, and Lim teaches “a secondary
`processor coupled with a second non-volatile memory, the second non-
`volatile memory coupled to the secondary processor and storing
`configuration parameters and file system for the secondary processor.”
`
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`c. Interface
`Independent claim 18 further recites “an interface communicatively
`coupling the primary processor and the secondary processor, an executable
`software image being received by the secondary processor via the interface.”
`Petitioner argues Figure 2 of Bauer and Figure 1 of Svensson show the ARM
`device and the DSP device coupled by an interface and that the combination
`of Bauer and Svensson, therefore, teaches “an interface communicatively
`coupling the primary processor and the secondary processor.” Pet. 50–51
`(citing Ex. 1209 ¶ 36, Fig. 2; Ex. 1210, 4:3–5, Fig. 1; Ex. 1202 ¶ 144); see
`Ex. 1209 ¶ 36 (“The arrows in FIG. 2 indicate access paths, e.g., busses and
`direct memory access (DMA) paths, between the CPUs and the
`memories . . . .”). As discussed above, Petitioner argues that the
`combination of Bauer and Svensson teaches storing executable images for
`the DSP device (secondary processor) in non-volatile memory 206 (first
`non-volatile memory). See Pet. 31–32. Petitioner further argues that the
`combination of Bauer and Svensson teaches receiving an executable
`software image at the secondary processor via the interface between the
`ARM device and the DSP device. Pet. 51 (citing Ex. 1209 ¶¶ 11, 31, 35–36,
`Fig. 2; Ex. 1210, 4:1–3, 4:9–14, 4:22–26, 5:21–37, 5:53–6:15, Figs. 1–3; Ex.
`1202 ¶ 145). For example, Svensson discloses that “[t]he SARAM and
`DARAM 108 [of the DSP device] can be loaded from the non-volatile
`memory 106 [of the ARM device] by the trivial ‘push’ method.” Ex. 1210,
`4:9–10.
`On this record, we are persuaded by Petitioner’s contention that the
`subject matter of “an interface communicatively coupling the primary
`processor and the secondary processor, an executable software image being
`
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`received by the secondary processor via the interface” would have been
`obvious based on the combined teachings of Bauer and Svensson.
`d. Image Header
`Petitioner further contends the subject matter reciting “the executable
`software image comprising an image header and at least one data segment”
`would have been obvious based on the combination of Bauer and Svensson.
`Pet. 31–32, 46–50. In particular, Petitioner contends Bauer discloses that its
`file format can hold executable data and object code, thereby teaching an
`“executable software image.” Pet. 31–32 (citing Ex. 1209 ¶¶ 30–32;
`Ex. 1202 ¶ 110); see Ex. 1209 ¶ 31 (“There are many possible applications
`of this format and its individually coded sections. . . . It can also be used as a
`file format in which executable files are stored . . . .”). Bauer’s file format
`stores data in section data 106. Ex. 1209 ¶ 32 (“The section data 106
`includes the data of the one or more sections included in the image 100.”),
`Fig. 1A.
`As to the claimed “image header,” Petitioner notes that, in Bauer,
`section information 104, rather than header 102, specifies the destination
`addresses for each section of data. Pet. 47 (citing Ex. 1209 ¶¶ 32–34, Figs.
`1A–1C; Ex. 1202 ¶ 138). Petitioner argues, therefore, that Bauer does not
`teach the claimed “image header” under Petitioner’s construction of “a
`header associated with the entire image that specifies where the data
`segments are to be placed in the system memory.” Pet. 47. Petitioner
`argues, however, that it would have been obvious to a person of ordinary
`skill in the art to provide the address information in the header for various
`reasons, including that such a modification would have been obvious to try
`based on the limited number of locations to put the destination addresses.
`
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`Pet. 48–50. Patent Owner argues Petitioner’s “obvious to try” rationale is
`deficient because Petitioner does not identify a recognized problem or need
`in the art that allegedly would have been addressed by the proposed
`modification. Prelim. Resp. 18–22.
`On this record, we are persuaded that the combination of Bauer and
`Svensson renders obvious an “image header.” There is no dispute, at this
`st
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