`
`DOCKET NO.: 0107131.00568US3
`Filed on behalf of Intel Corporation
`By:
`(David.Cavanaugh@wilmerhale.com)
`David L. Cavanaugh, Reg. No. 36,476
`(Tom.Anderson@wilmerhale.com)
`Thomas E. Anderson, Reg. No. 37,063
`(Joseph.Haag@wilmerhale.com)
`Joseph H. Haag, Reg. No. 42,612
`(Evelyn.Mak@wilmerhale.com)
`Evelyn C. Mak, Reg., No. 50,492
`Wilmer Cutler Pickering Hale and Dorr LLP
`1875 Pennsylvania Avenue, N.W.
`Washington, DC 20006
`TEL: (202) 663-6000
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________________________________________
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________________________________________
`Intel Corporation
`Petitioner
`
`v.
`Patent Owner of
`U.S. Patent No. 8,838,949 to Gupta et al.
`
`Trial No. IPR2018-001336
`PETITION FOR INTER PARTES REVIEW OF
`U.S. PATENT NO. 8,838,949
`UNDER 35 U.S.C. § 312 AND 37 C.F.R. § 42.104
`
`
`
`
`

`

`U.S. Patent No. 8,838,949
`Petition for Inter Partes Review
`TABLE OF CONTENTS
`
`V. 
`
`I. 
`INTRODUCTION ........................................................................................... 1 
`II.  MANDATORY NOTICES ............................................................................. 2 
`A. 
`Real Party-in-Interest ............................................................................ 2 
`B. 
`Related Matters ..................................................................................... 2 
`C. 
`Counsel .................................................................................................. 3 
`D. 
`Service Information ............................................................................... 3 
`III.  CERTIFICATION OF GROUNDS FOR STANDING .................................. 3 
`IV.  OVERVIEW OF CHALLENGE AND RELIEF REQUESTED .................... 3 
`Prior Art Patents and Printed Publications ............................................ 4 
` 
`B. 
`Grounds for Challenge .......................................................................... 5 
`TECHNOLOGY BACKGROUND ................................................................. 5 
`A.  Multi-Processor Systems ....................................................................... 5 
`1. 
`Processor-To-Processor Communications .................................. 5 
`2. 
`Processor Software Code ............................................................ 6 
`3. 
`Characteristics of Memory .......................................................... 6 
`Storing, Loading, and Executing Processor Software
`Code ....................................................................................................... 7 
`1. 
`Storing the Software Code in Memory ....................................... 7 
`2. 
`Loading and Executing Multi-Segmented Software
`Images ......................................................................................... 7 
`Sharing Memory in Multi-Processor Systems ............................ 8 
`3. 
`Boot Loading ......................................................................................... 8 
`C. 
`VI.  OVERVIEW OF THE ʼ949 PATENT ............................................................ 9 
`A.  Alleged Problem of the Prior Art ........................................................ 10 
`B. 
`Purported Solution of the ’949 Patent ................................................. 11 
`C. 
`Prosecution History of the ’949 Patent ............................................... 13 
`VII.  LEVEL OF ORDINARY SKILL IN THE ART ........................................... 16 
`VIII.  CLAIM CONSTRUCTION .......................................................................... 17 
`
`B. 
`
`i
`
`

`

`U.S. Patent No. 8,838,949
`Petition for Inter Partes Review
`“image header” (claims 18 and 20) ..................................................... 17 
`A. 
`IX.  OVERVIEW OF PRINCIPAL PRIOR ART REFERENCES ...................... 18 
`A. 
`Svensson (Ex-1210) ............................................................................ 18 
`B. 
`Bauer (Ex-1209) .................................................................................. 20 
`C. 
`Kim (Ex-1211) (Including English Translation (Ex-
`1212)) .................................................................................................. 21 
`Lim (Ex-1214) ..................................................................................... 23 
`D. 
`SPECIFIC GROUNDS FOR PETITION ...................................................... 26 
`A.  Ground 1: Claims 18-21 Are Rendered Obvious By The
`Combination Of Bauer, Svensson, Kim, And Lim ............................. 26 
`1. 
`Reference to “Bauer and Svensson Combined” ....................... 26 
`2. 
`Claim 18 .................................................................................... 28 
`3. 
`Claim 19 .................................................................................... 66 
`4. 
`Claim 20 .................................................................................... 68 
`5. 
`Claim 21 .................................................................................... 74 
`XI.  CONCLUSION ............................................................................................. 75 
`
`
`X. 
`
`ii
`
`

`

`U.S. Patent No. 8,838,949
`Petition for Inter Partes Review
`Petitioner Intel Corporation respectfully requests Inter Partes Review of
`
`claims 18-21 of U.S. Patent No. 8,838,949 (the “’949 patent”) (Ex-1201) pursuant
`
`to 35 U.S.C. §§ 311-319 and 37 C.F.R. § 42.1 et seq.
`
`I.
`
`INTRODUCTION
`The ’949 patent discloses a particular technique for “scatter loading” an
`
`executable software image from a primary processor to a secondary processor in a
`
`multi-processor system. The general concept of scatter loading a software image
`
`and the specific details proposed by the ’949 patent, however, were neither novel
`
`nor non-obvious at the time of the purported invention. This Petition presents two
`
`key pieces of prior art—Bauer and Kim—that were not before the Patent Office
`
`during prosecution and that disclose exactly what the Examiner found missing
`
`from the prior art of record.
`
`The Patent Owner obtained the ’949 patent only by adding claim limitations
`
`to distinguish a prior art Svensson PCT reference. The Patent Owner argued that
`
`Svensson PCT did not disclose a secondary processor that (1) received separately
`
`an image header and data segments of a software image; and (2) scatter loaded
`
`each data segment directly from the secondary processor’s hardware buffer to its
`
`system memory based on the image header. This Petition explains how Bauer and
`
`Kim disclose these two alleged points of novelty of the ’949 patent.
`
`1
`
`

`

`U.S. Patent No. 8,838,949
`Petition for Inter Partes Review
`These new references—in combination with Svensson, the U.S. counterpart
`
`to Svensson PCT—present new art and a new combination that the Examiner never
`
`had a chance to consider. As explained below and in the accompanying
`
`declaration of Professor Bill Lin, this new art shows that the challenged claims of
`
`the ’949 patent were obvious at the time of the purported invention and should be
`
`canceled.
`
`II. MANDATORY NOTICES
`A. Real Party-in-Interest
`Intel Corporation (“Petitioner”) is a real party-in-interest and submits this
`
`inter partes review petition (“Petition”) for review of certain claims of the ’949
`
`patent. Petitioner also identifies Apple Inc. (“Apple”) as a real party-in-interest.
`
`B. Related Matters
`The following litigation matter would affect or be affected by a decision in
`
`this proceeding: Qualcomm Inc. v. Apple Inc., Case No. 3:17-cv-1375 (S.D. Cal.).
`
`The ’949 patent was asserted in, but subsequently withdrawn from, this
`
`proceeding: In re Certain Mobile Elec. Devices and Radio Frequency and
`
`Processing Components Thereof, Inv. No. 337-TA-1065 (Int’l Trade Comm’n)
`
`(“Related ITC Case”).
`
`Petitioner is also concurrently filing (1) a Petition for Inter Partes Review of
`
`claims 1-9 and 22-23 of the ’949 patent (IPR2018-01334) and (2) a Petition for
`
`2
`
`

`

`U.S. Patent No. 8,838,949
`Petition for Inter Partes Review
`Inter Partes Review of claims 10-17 of the ’949 patent (IPR2018-01335), and
`
`requests that the petitions be assigned to the same Board.
`
`C. Counsel
`Lead Counsel: David L. Cavanaugh (Registration No. 36,476)
`
`Backup Counsel: Thomas E. Anderson (Registration No. 37,063); Joseph H.
`
`Haag (Registration No. 42,612); Evelyn C. Mak (Registration No. 50,492)
`
`Petitioner also plans to file pro hac vice applications for Joseph J. Mueller
`
`and Nina S. Tallon, both counsel of record in the pending litigation.
`
`D.
`Service Information
`Email: David.Cavanaugh@wilmerhale.com;
`Tom.Anderson@wilmerhale.com;
`Joseph.Haag@wilmerhale.com;
`Evelyn.Mak@wilmerhale.com
`Post and hand delivery: Wilmer Cutler Pickering Hale and Dorr LLP
`1875 Pennsylvania Avenue, N.W.
`Washington, DC 20006
`
`Telephone: 202-663-6000 Facsimile: 202-663-6363
`
`III.
`
`CERTIFICATION OF GROUNDS FOR STANDING
`Petitioner certifies pursuant to Rule 42.104(a) that the patent for which
`
`review is sought is available for inter partes review and that Petitioner is not
`
`barred or estopped from requesting an inter partes review challenging the patent
`
`claims on the grounds identified in this Petition.
`
`IV.
`
`OVERVIEW OF CHALLENGE AND RELIEF REQUESTED
`
`3
`
`

`

`U.S. Patent No. 8,838,949
`Petition for Inter Partes Review
`Pursuant to Rules 42.22(a)(1) and 42.104(b)(1)-(2), Petitioner challenges
`
`claims 18-21 of the ʼ949 patent.
`
`
`
`Prior Art Patents and Printed Publications
`Petitioner relies upon the following patents and printed publications:
`
`1.
`
`U.S. Patent Application Publication No. 2006/0288019 to Bauer et al.
`
`(“Bauer”) (Ex-1209) was filed Oct. 14, 2005 and published Dec. 21, 2006, and is
`
`therefore prior art to the ʼ949 patent under pre-AIA 35 U.S.C. § 102(a), (b), and
`
`(e).
`
`2.
`
`U.S. Patent No. 7,356,680 to Svensson et al. (“Svensson”) (Ex-1210)
`
`was filed Jan. 22, 2005 and issued Apr. 8, 2008, and is therefore prior art to the
`
`ʼ949 patent under pre-AIA 35 U.S.C. § 102(a), (b), and (e).
`
`3.
`
`Korean Patent Application Publication No. 10-2002-0036354 to Kim
`
`(“Kim”) (Ex-1211) was filed Nov. 9, 2000 and published May 16, 2002, and is
`
`therefore prior art to the ’949 patent under pre-AIA 35 U.S.C. § 102(a) and (b). A
`
`certified English language translation of Kim is provided as Ex-1212.1
`
`4.
`
`U.S. Patent No. 7,203,829 to Lim (“Lim”) (Ex-1214) was filed Jun.
`
`10, 2004 and issued Apr. 10, 2007, and is therefore prior art to the ʼ949 patent
`
`under pre-AIA 35 U.S.C. § 102(a), (b), and (e).
`
`
`1 Citations to Kim in this Petition are to the English translation (Ex-1212).
`
`4
`
`

`

`U.S. Patent No. 8,838,949
`Petition for Inter Partes Review
`
`B. Grounds for Challenge
`Petitioner requests cancellation of claims 18-21 as being unpatentable under
`
`35 U.S.C. § 103. This Petition is supported by the Declaration of Professor Bill
`
`Lin (Ex-1202). This Petition demonstrates that there is a reasonable likelihood that
`
`Petitioner will prevail with respect to at least one challenged claim and that each of
`
`the challenged claims is unpatentable for the reasons cited herein. See 35 U.S.C. §
`
`314(a).
`
`V.
`
`TECHNOLOGY BACKGROUND
`A. Multi-Processor Systems
`1. Processor-To-Processor Communications
`The ’949 patent generally relates to communications between processors in a
`
`multi-processor system. For example, a mobile telephone may include a
`
`“baseband” processor (or “modem” processor) and an “application” processor. Ex-
`
`1201, 1:41-44. The baseband/modem and application processors typically
`
`communicate with each other by sending data over a “bus”—sometimes referred to
`
`as an “interface.” It was well known to use standardized buses to enable
`
`compatibility between processors in multi-processor devices such as mobile
`
`telephones, including High Speed Synchronous Interface (HSI), Universal Serial
`
`Bus (USB), USB High Speed Inter-Chip (HSIC), Mobile Industry Processor
`
`Interface (MIPI), Secure Digital Input/Output (SDIO), Universal Asynchronous
`
`5
`
`

`

`U.S. Patent No. 8,838,949
`Petition for Inter Partes Review
`Receiver-Transmitter (UART), Serial Peripheral Interface (SPI), and Inter-
`
`Integrated Circuit (I2C). Ex-1201, 5:35-43; Ex-1213, ¶32. Ex-1202, ¶¶29-35.
`
`2. Processor Software Code
`A processor operates by executing different types of software code. When a
`
`processor is initially powered up, it typically executes “boot code” that instructs
`
`the processor to perform certain initialization operations. After the processor
`
`boots, it typically executes “program code” that instructs the processor to perform
`
`various designated operations. Ex-1202, ¶¶36-37.
`
`3. Characteristics of Memory
`Software code must be stored in a memory accessible to the processor so
`
`that it can be read and executed. There are two types of memory—non-volatile (or
`
`persistent) and volatile memory. Non-volatile memory (e.g., read-only memory
`
`(ROM), electrically erasable programmable ROM (EEPROM), and flash memory)
`
`is suitable for long-term storage. However, it typically costs more, provides lower
`
`performance (e.g., operates slower), and requires more space than volatile memory.
`
`In contrast, volatile memory (e.g., random access memory (RAM), dynamic RAM
`
`(DRAM), and static RAM (SRAM)) is suitable for short-term storage. It allows
`
`for code and other data to be quickly stored and retrieved from memory, thereby
`
`increasing system performance. A data buffer, which is often some portion of
`
`6
`
`

`

`U.S. Patent No. 8,838,949
`Petition for Inter Partes Review
`volatile memory, is typically used as a temporary storage area that allows data to
`
`be moved from one location to another. Ex-1202, ¶¶38-41.
`
`B.
`
`Storing, Loading, and Executing Processor Software Code
`1. Storing the Software Code in Memory
`Initially, software code is typically stored in non-volatile memory, and then
`
`later transferred to volatile memory—known as “system memory.” Software code
`
`is typically packaged and stored in memory as a file or program called an
`
`“executable [software] image.” Executable images were well known in the prior
`
`art, including “multi-segmented” images that included (1) a header and/or one or
`
`more tables or other structures that contain information about the overall image,
`
`and (2) one or more segments containing code or other data used by the image—
`
`what the patent calls “data segments.”2 Ex-1201, 2:14-16, 4:34-42. Ex-1202,
`
`¶¶42-43.
`
`2. Loading and Executing Multi-Segmented Software Images
` A processor usually must load a multi-segmented software image into its
`
`system memory before the processor can execute that image. Most software
`
`images are designed to be loaded in multiple steps. The processor first reads
`
`
`2 In this Petition, references to “data” include code and/or data, and references to
`
`“data segment” include a segment containing code and/or data. Ex-1202, ¶43.
`
`7
`
`

`

`U.S. Patent No. 8,838,949
`Petition for Inter Partes Review
`information about the image in the headers and/or tables or other structures of the
`
`image, and then uses that information to load the data segments into memory and
`
`execute the image. Ex-1202, ¶44.
`
`“Scatter loading” is a well-known loading process in which one or more
`
`portions of an image are loaded (or “scattered”) into system memory. For an
`
`image having more than one data segment, the data segments can be stored either
`
`in contiguous or spread across non-contiguous memory locations. Many prior art
`
`image formats were designed for scatter loading by including information in the
`
`image about where each data segment of the image should be loaded in system
`
`memory for later execution. Ex-1201, 2:37-41, 4:34-42. Ex-1202, ¶45.
`
`3. Sharing Memory in Multi-Processor Systems
`To reduce costs and space requirements in a multi-processor system,
`
`program code for both processors may be stored in a single non-volatile memory.
`
`For example, an application processor may have direct access to non-volatile
`
`memory that stores program code for both the application and baseband/modem
`
`processors. The baseband/modem processor, on the other hand, may have direct
`
`access to only volatile memory. Upon power up, therefore, the application
`
`processor may have to transfer program code from its non-volatile memory to the
`
`baseband/modem processor’s volatile memory via a bus. Ex-1202, ¶¶46-48.
`
`C. Boot Loading
`
`8
`
`

`

`U.S. Patent No. 8,838,949
`Petition for Inter Partes Review
`When a multi-processor system is first powered on, one or more processors
`
`typically load and execute “boot code” (or “boot software”) to enable the
`
`processor(s) to begin to operate. The boot code is often stored in a processor’s
`
`non-volatile memory, and during boot up, the boot code is typically loaded and
`
`executed from the processor’s system memory. Ex-1201, 1:38-44, 1:51-56. Ex-
`
`1202, ¶¶49-50.
`
`The boot process often occurs in multiple stages. In a first stage, a primitive
`
`“boot loader” function usually loads and then executes a relatively small amount of
`
`boot code stored in an easily accessible local boot ROM. In one or more later
`
`stages, the processor then typically loads additional boot code (usually stored in a
`
`different, larger non-volatile memory). It was known in the prior art that a
`
`processor’s boot code could be stored in a non-volatile memory coupled to a
`
`different processor (especially for the later-stage boot code). Ex-1201, 2:9-13. Ex-
`
`1202, ¶¶51-52.
`
`VI.
`
`OVERVIEW OF THE ʼ949 PATENT
`
`9
`
`

`

`U.S. Patent No. 8,838,949
`Petition for Inter Partes Review
` The application that issued as the ’949 patent (Ex-1201) was filed on Mar.
`
`21, 2011, and claims priority to four provisional applications, the earliest of which
`
`was filed on Mar. 22, 2010.3 Ex-1202, ¶53.
`
`The ʼ949 patent is directed to a particular technique for scatter loading an
`
`executable software image from a memory connected to a primary processor to a
`
`memory connected to a secondary processor. Ex-1201, 1:24-33. Ex-1202, ¶54.
`
`A. Alleged Problem of the Prior Art
`According to the ’949 patent, prior art systems and methods for transferring
`
`software code between processors were inefficient. In particular, when retrieving
`
`an image for a modem processor from a non-volatile memory coupled to the
`
`application processor, prior art devices required copying the entire software image
`
`into one part of the modem processor’s system memory, and then copying the
`
`image into another part of system memory when loading it for execution. Ex-
`
`1201, 7:20-26. The ’949 patent describes this double copy (or “extra memory
`
`copy”) approach as inefficient. Id., 7:27-30; see also id., 2:1-54, 9:42-56, 11:11-
`
`
`3 In this Petition, Petitioner treats Mar. 22, 2010 as the effective filing date, but
`
`does not take any position regarding whether the ’949 patent is fully enabled by
`
`any of its provisional applications.
`
`10
`
`

`

`U.S. Patent No. 8,838,949
`Petition for Inter Partes Review
`24. However, this alleged problem was well-known in the prior art. Ex-1202,
`
`¶¶55-56.
`
`B.
`Purported Solution of the ’949 Patent
`The ’949 patent does not claim to invent a new type of processor, processor
`
`architecture, executable software image format, image header, or data segment.
`
`The patent also does not claim to invent the idea of scatter loading executable
`
`software images into system memory, including based on information contained in
`
`an image header. All those things were well known in the prior art. Ex-1202, ¶57.
`
`Indeed, the ’949 patent admits that many claimed features of the patent are
`
`prior art, including:
`
` multi-processor systems in which a primary processor uses non-volatile
`
`memory to store a software image (e.g., boot code) for a secondary
`
`processor, and where the software image is downloaded from the primary
`
`processor to the secondary processor (e.g., to a volatile memory) (Ex-
`
`1201, 2:1-13);
`
` that a software image would often comprise a header and multiple
`
`segments of code (id., 2:14-16);
`
` that a transfer of a software image from a primary processor to a
`
`secondary processor may occur via a temporary (or intermediate) buffer
`
`(id., 2:17-37);
`
`11
`
`

`

`U.S. Patent No. 8,838,949
`Petition for Inter Partes Review
`
` that a software image could be scattered (i.e., scatter loaded) from a
`
`temporary buffer into the system (e.g., volatile) memory of a secondary
`
`processor (id., 2:35-41);
`
` that the primary processor and its non-volatile memory may be
`
`implemented on a different chip from that of the secondary processor
`
`(id., 2:42-45);
`
` that each processor can have a non-volatile memory (e.g., flash memory,
`
`ROM) that stores executable images and file systems, including the
`
`processor’s boot code—such that upon power-up, the boot code is loaded
`
`from memory for execution by that processor (id., 1:48-56); and
`
` that the multi-processor system can be implemented in a smartphone
`
`device that includes an application processor and a modem processor (id.,
`
`1:39-44).
`
`Ex-1202, ¶58.
`
`Instead, what the ’949 patent claims to have invented is a new way to avoid
`
`the “double copy” or “extra memory” approach described above. The purported
`
`solution of the ’949 patent is for a secondary (or modem) processor to (1) first
`
`receive from the primary (or application) processor the “image header” of an
`
`executable software image, and (2) then separately receive each “data segment” of
`
`the image, each of which is then scatter loaded into the secondary processor’s
`
`12
`
`

`

`U.S. Patent No. 8,838,949
`Petition for Inter Partes Review
`system memory using the data segment’s destination address from the earlier-
`
`received image header—all without first copying the entire image into the
`
`secondary processor’s system memory. The data received by the secondary
`
`processor is temporarily stored in a hardware buffer separate from the system
`
`memory. Ex-1201, 2:58-3:67, 9:42-56, 11:11-24. However, this purported
`
`solution was well-known in the prior art. Ex-1202, ¶59; see generally id., ¶¶60-67
`
`(describing the purported solution in the context of Figure 3 of the patent).
`
`C.
`Prosecution History of the ’949 Patent
`The ’949 patent was filed on Mar. 21, 2011 with twenty-four claims (six
`
`independent claims). During prosecution, the Applicants amended several
`
`independent claims to incorporate the contents of cancelled claim 4, in addition to
`
`other features, to overcome the cited prior art. Ex-1202, ¶68.
`
`The Examiner initially rejected all original claims of the ’949 patent as being
`
`anticipated by Svensson PCT.4 Ex-1204, 2-5. The Examiner found that Svensson
`
`PCT discloses:
`
` a “secondary processor [client processor 104] comprising system
`
`memory [DSPXRAM 110] and a hardware buffer [An intermediate
`
`storage area is defined within the memory 108]”;
`
`
`4 Svensson PCT claims priority to Svensson. Ex-1203, cover; Ex-1210, cover.
`
`13
`
`

`

`U.S. Patent No. 8,838,949
`Petition for Inter Partes Review
`
` a “scatter loader controller…[The slave copies the contents of the
`
`intermediate storage area to appropriate locations in its slave-private
`
`memory (Step 220), thereby implementing its actual loading, see page 7,
`
`last line - page 8, line 2]”;
`
` a “primary processor [host processor102] coupled with a memory [non-
`
`volatile memory 106]”;
`
` an “interface…[The arrows in FIG. 1 indicate access paths, e.g., busses
`
`and DMA paths…]”; and
`
` “the executable software image comprises an image header and at least
`
`one data segment [Fig. 3, it is clear that the executable software image
`
`comprises an image header and at least one segment].”
`
`Id., 2-3 (emphasis in original); see also Ex-1203, Fig. 1 (below). Ex-1202, ¶69.
`
`
`
`14
`
`

`

`U.S. Patent No. 8,838,949
`Petition for Inter Partes Review
`In response, the Applicants did not contest that Svensson PCT anticipated
`
`the original claims. Instead, the Applicants amended claim 1 to require that (1) the
`
`claimed “hardware buffer” must receive “an image header and at least one data
`
`segment” of an executable software image, “the image header and each data
`
`segment being received separately”; and (2) the claimed “scatter loader controller”
`
`is configured “to load the image header; and to scatter load each received data
`
`segment, based at least in part on the loaded image header.” Ex-1205, 2. Similar
`
`amendments were made to independent claims 11, 17, 19, 21, and 23. Id., 4-7.
`
`The Applicants also admitted that “Svensson [PCT] arguably discloses that the
`
`software includes a header and a data segment.” Id., 8. Ex-1202, ¶70.
`
`In an attempt to distinguish Svensson PCT, the Applicants argued that
`
`Svensson PCT “fails to disclose that the image header and each data segment are
`
`received separately” (i.e., the requirement added by amendment). Ex-1205, 9. The
`
`Applicants further asserted that “loading each data segment directly5 from the
`
`hardware buffer to the system memory,” as required by Applicants’ amendment,
`
`“is patentably distinguishable from concatenating the data blocks and headers in
`
`the intermediate storage area and then transferring the concatenated data to the
`
`memory, as recited in Svensson [PCT].” Id. Ex-1202, ¶71.
`
`
`5 All emphasis added unless otherwise noted.
`
`15
`
`

`

`U.S. Patent No. 8,838,949
`Petition for Inter Partes Review
`The Examiner subsequently allowed the claims only after the Applicants
`
`amended the claims to require that (1) the image header and each data segment be
`
`received separately at the secondary processor, as well as (2) each data segment be
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`scatter loaded directly to the system memory of the secondary processor. Ex-1206,
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`5. The ’949 patent then issued on Sep. 16, 2014. Ex-1201, cover.6 Ex-1202, ¶72.
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`This Petition explains how Bauer and Kim disclose the same two claim
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`features that the Examiner found allowable over Svensson PCT. These new
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`references—in combination with Svensson, the U.S. counterpart to Svensson
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`PCT—present new art and a new combination that the Examiner never had a
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`chance to consider. Ex-1202, ¶73.
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`VII.
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`LEVEL OF ORDINARY SKILL IN THE ART
`A person of ordinary skill in the art (POSITA) of the ’949 patent would have
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`had a Master’s degree in Electrical Engineering, Computer Engineering or
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`Computer Science plus at least two years of experience in mobile device
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`architecture and multi-processor systems, or a Bachelor’s degree in one of those
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`fields plus at least four years of experience in mobile device architecture and multi-
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`processor systems. In the Related ITC Case, the CALJ held this to be the level of
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`ordinary skill in the art. Ex-1207, 11-13. Ex-1202, ¶74.
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`
`6 Original claims 5-24 were re-numbered as issued claims 4-23, respectively.
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`16
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`

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`VIII.
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`CLAIM CONSTRUCTION
`A claim of an unexpired patent in inter partes review is given the “broadest
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`U.S. Patent No. 8,838,949
`Petition for Inter Partes Review
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`reasonable construction in light of the specification” (“BRI standard”). 37 C.F.R.
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`§ 42.100(b); see Cuozzo Speed Techs., LLC v. Lee, 136 S. Ct. 2131, 2142 (2016).
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`Petitioner has set forth below its proposed constructions of certain terms of the
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`’949 patent and its support for the constructions. Should the Board decide that
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`claim terms should be construed under the standard set forth in Phillips v. AWH
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`Corp., 415 F.3d 1303 (Fed. Cir. 2005), Petitioner submits that the claim
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`constructions set out in this Petition also apply under the Phillips standard.
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`Petitioner therefore submits that the challenged claims are invalid in view of the
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`prior art under either the BRI or Phillips standard.
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`A.
`“image header” (claims 18 and 20)
`As used in the ’949 patent, a POSITA would have understood the term
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`“image header” to mean “a header associated with the entire image that specifies
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`where the data segments are to be placed in the system memory” under either the
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`BRI or Phillips standard. This understanding is consistent with the specification of
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`the ’949 patent. See Ex-1201, 8:18-21, 7:50-52, 9:23-24, 10:6. This understanding
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`is also consistent with the claims of the ’949 patent. Id., claim 10 (“processing…
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`the image header to determine at least one location within system memory…to
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`17
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`

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`U.S. Patent No. 8,838,949
`Petition for Inter Partes Review
`store each data segment”). In the Related ITC Case, the parties (including the
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`Patent Owner) agreed to this construction for this term. Ex-1208, 3. Ex-1202, ¶77.
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`IX.
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`OVERVIEW OF PRINCIPAL PRIOR ART REFERENCES
`A.
`Svensson (Ex-1210)
`Svensson is generally directed to an “OS-friendly bootloader” for loading
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`code and/or data from memory associated with a host processor to memory
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`associated with a client processor in a multi-processor system. Ex-1210, Abstract,
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`2:24-27. Ex-1202, ¶78.
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`Figure 1 of Svensson below shows a multi-processor system 100 having an
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`advanced RISC machine (ARM) device and a digital signal processor (DSP)
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`device. Ex-1210, 3:49-50, 3:54-58, Fig. 1.
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`
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`The ARM device includes a host processor (ARM CPU) 102 that is coupled to a
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`non-volatile memory 106 and to the DSP device. Id., 3:49-63, 4:3-5, Fig. 1. The
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`DSP device includes a client processor (DSP CPU) 104, a system memory (DSP
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`external RAM (XRAM)) 110, and an internal volatile memory (single-access RAM
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`18
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`

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`U.S. Patent No. 8,838,949
`Petition for Inter Partes Review
`(SARAM) or dual-access RAM (DARAM)) 108 that can have an intermediate
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`storage area (Int. Store Area). Id., 3:64-4:3, Fig. 1. The multi-processor system
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`includes access paths, such as buses and direct memory access (DMA) paths, that
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`connect the CPUs and memories. Id., 4:3-5, Fig. 1. Ex-1202, ¶79.
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`Svensson discloses that the host processor 102 loads the code and/or data
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`from the non-volatile memory 106 to the intermediate storage area in the shared
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`volatile memory 108 at the client, and the client processor 104 then copies the code
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`and/or data to end destinations in the system memory 110. Ex-1210, 1:11-15, 2:6-
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`20, 4:9-14, 4:22-26, 6:12-15, Fig. 1; see also id., 4:15-6:11, Fig. 2. Ex-1202, ¶80.
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`Figure 3 of Svensson below shows how the code and/or data can be
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`transferred from the host processor into the intermediate storage area using one or
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`more transfer blocks. Ex-1210, 6:12-23, Fig. 3.
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`Each transfer block includes a header that indicates the length (Length) of the
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`block and a destination address (Dest. Addr.) indicating where the block is to be
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`
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`19
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`U.S. Patent No. 8,838,949
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`loaded in the system memory 110. Id. Ex-1202, ¶81; see generally id., ¶82
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`(describing Svensson’s loading process).
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`B.
`Bauer (Ex-1209)
`Bauer, which is closely interrelated with Svensson, describes a file format
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`that is an improvement upon the file format described in Svensson. Instead of
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`using a separate block header to store a destination address for each block of an
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`image, the file format in Bauer has that information collected in one place as
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`section information. Ex-1209, ¶¶27, 32-34, 43, Figs. 1A-1C. Bauer teaches that
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`this approach “simplifies optimization” and “makes memory loading efficient.”
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`Id., ¶43; see also id., ¶¶16, 27. This section information is located near the
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`beginning of the image—after the header but before all the data sections of the
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`image—so that the section information can be retrieved separately from (and
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`before) the data sections are read and processed. Id., Abstract, ¶¶28-30, 47, Figs.
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`1A-1C. Ex-1202, ¶¶83-84.
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`Bauer teaches that its file format can be used in the same multi-processor
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`system described in Svensson. Bauer shows and describes the same system
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`architecture as Svensson (Ex-1209, Fig. 2 (below), ¶¶35, 36; cf. Ex-1210, Fig. 1,
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`3:49-4:8), and further cites to Svensson as an example of a program loader for
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`loading an image with this file format in that same system (Ex-1209, ¶31). Ex-
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`1202, ¶¶85-87.
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`20
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`U.S. Patent No. 8,838,949
`Petition for Inter Partes Review
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`Figures 1A-1C of Bauer below show the file format of a data image 100,
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`which includes a header 102, section information 104, and section data 106:
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`
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`
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`Ex-1209, ¶¶32-34, Figs. 1A-1C. Ex-1202, ¶89; see generally id., ¶90 (describing
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`Bauer’s file