`
`_____________________________
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`IN THE UNITED STATES PATENT TRIAL AND APPEAL BOARD
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`_____________________________
`
`
`BLUEHOUSE GLOBAL LTD.
`Petitioner
`
`v.
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`SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
`Patent Owner
`
`
`
`
`_____________________________
`
`
`CASE IPR: 2018-01377
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`U.S. PATENT NO. 9,281,405 B2
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`_____________________________
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`
`PETITION FOR INTER PARTES REVIEW
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`
`
`
`Mail Stop Patent Board
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
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`
`
`
`
`Petition for Inter Partes Review
`U.S. Patent No. 9,281,405
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`Table of Contents
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`INTRODUCTION……………………………………………………. ...1
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`
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`I.
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`II. MANDATORY NOTICES (37 C.F.R. § 42.8)………………………...1
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`A. Real Parties-In-Interest (37 C.F.R. § 42.8(b)(1))……………….1
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`B. Related Matters (37 C.F.R. § 42.8(b)(2))……………………......1
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`C. Lead and Backup Counsel (37 C.F.R. § 42.8(b)(3))……………2
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`D.
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`Service Information (37 C.F.R. § 42.8(b)(4))…………………...2
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`III. GROUNDS FOR STANDING (37 C.F.R. § 42.104(a))……………….3
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`IV.
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`V.
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`IDENTIFICATION OF CHALLENGES……………………………...3
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`BACKGROUND………………………………………………………...4
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`A.
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`B.
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`C.
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`Technology………………………………………………………..4
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`The ‘405 Patent………………………………………………...…6
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`Prosecution History………………………………………………7
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`VI. PERSON OF ORDINARY SKILL IN THE ART…………………….7
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`VII. CLAIM CONSTRUCTION…………………………………………….8
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`VIII. IDENTIFICATION OF HOW EACH CHALLENGED
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`CLAIM OF THE ‘405 PATENT IS UNPAENTABLE……………….9
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`
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`A. Challenge #1: Claims 10, 11, 15 and 16 are
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`anticipated under pre-AIA 35 U.S.C. § 102(b)
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`by Godo..………………………………………………………......9
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`ii
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`Petition for Inter Partes Review
`U.S. Patent No. 9,281,405
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`1.
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`2.
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`3.
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`4.
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`Claim 10…………………………………………………. .12
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`Claim 11…………………………………………………. .24
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`Claim 15…………………………………………………. .25
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`Claim 16…………………………………………………. .26
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`B. Challenge #2: Claims 10, 15 and 16 are
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`anticipated under pre-AIA 35 U.S.C. § 102(b)
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`by Toyota………...…………………………………………...…..28
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`
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`1.
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`2.
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`Claim 10....………………………………………………...30
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`Claim 15…………………………………………………. ..43
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`IX. CONCLUSION…………………………………………………..…….50
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`3.
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`Claim 16…………………………………………………. ..44
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`C. Challenge #3: Claim 11 is obvious under
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`pre-AIA 35 U.S.C. § 103(a) over Toyota in
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`view of Godo………………………………………….………….45
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`iii
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`Petition for Inter Partes Review
`U.S. Patent No. 9,281,405
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`List of Exhibits
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`
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`Ex. 1001 United States Letters Patent No. 9,281,405 B2
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`Ex. 1002
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`Prosecution history of U.S. Patent No. 9,281,405 B2
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`Ex. 1003 Declaration of Richard A. Flasck
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`Ex. 1004 United States Patent Application Publication No. 2011/0193081 A1
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`
` (“Godo”)
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`Ex. 1005 United States Patent Application Publication No. 2008/0299693 A1
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`(“Toyota”)
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`iv
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`I.
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`
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`INTRODUCTION
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`BlueHouse Global Ltd. (“Petitioner”) hereby petitions for inter partes
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`review of claims 10, 11, 15 and 16 (the “challenged claims”) of U.S. Patent No.
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`9,281,405 (“the ‘405 Patent”; Ex. 1001) under 35 U.S.C. §§ 311–319 and 37
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`C.F.R. § 42. According to the assignment information on the front of the ‘405
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`Patent, and the records of the United States Patent & Trademark Office (the
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`“USPTO”), the ‘405 Patent is assigned to, and therefore owned by, Semiconductor
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`Energy Laboratory Co., Ltd. (the “Patent Owner”). For the reasons provided in
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`detail below, the challenged claims should be found unpatentable and canceled.
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`
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`II. MANDATORY NOTICES (37 C.F.R. § 42.8)
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`
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`
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`A. Real Parties-In-Interest (37 C.F.R. § 42.8(b)(1))
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`The real parties-in-interest in this matter are Petitoner BlueHouse Global
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`Ltd. and its parent company, Caesar Global Fund.
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`
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`
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`B. Related Matters (37 C.F.R. § 42.8(b)(2))
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`As of the filing date of this Petition, Petitioner is unaware of any matters
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`involving the ‘405 Patent pending in any United States court or administrative
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`agency.
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`
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`C. Lead and Backup Counsel (37 C.F.R. § 42.8(b)(3))
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`Petition for Inter Partes Review
`U.S. Patent No. 9,281,405
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`Lead Counsel:
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`Ryan O. White (USPTO Reg. No. 45,541)
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`TAFT, STETTINIUS & HOLLISTER LLP
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`One Indiana Square, Suite 3500
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`Indianapolis, IN 46204
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`
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`Tel: (317) 713-3455
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`Fax: (317) 713-3699
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`Email: rwhite@taftlaw.com
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`
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`Backup Counsel:
`
`
`Roshan P Shrestha (No. 71,277)
`TAFT, STETTINIUS & HOLLISTER LLP
`111 East Wacker Dr. Suite 2800
`Chicago, IL 60601
`Tel: (312) 527-4000
`Fax: (312) 966-8573
`Email: rshrestha@taftlaw.com
`
`
`Philip R. Bautista (pro hac vice
`authorization requested)
`TAFT, STETTINIUS & HOLLISTER LLP
`200 Public Square Suite 3500
`Cleveland, OH 44114-2302
`Tel: (216) 706-3957
`Fax: (216) 241-3707
`Email: pbautista@taftlaw.com
`
`
`Petitioner hereby requests authorization to file a motion under 37 C.F.R. § 42.10(c)
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`for Backup Counsel Philip R. Bautista to appear pro hac vice, as Mr. Bautista is an
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`experienced litigating attorney and has an established familiarity with this subject
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`matter at issue in this proceeding. Petitioner intends to file such a motion once
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`authorization is granted.
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`D.
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`Service Information (37 C.F.R. § 42.8(b)(4))
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`
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`Please address all correspondence to Lead Counsel at the mailing address
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`shown above. Petitioner also consents to electronic service by email.
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`2
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`III. GROUNDS FOR STANDING (37 C.F.R. § 42.104(a))
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`Petition for Inter Partes Review
`U.S. Patent No. 9,281,405
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`
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`Petitioner hereby certifies that: (1) the ‘405 Patent issued on March 8, 2016
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`and so is eligible for inter partes review; (2) Petitioner has not been served with a
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`complaint alleging infringement of any of the claims of the ‘405 Patent and so is
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`therefore not barred or estopped from requesting inter partes review of the ‘405
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`Patent on the grounds identified herein; and (3) Petitioner has not filed a complaint
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`challenging the validity of the ‘405 Patent. This Petition is being filed in
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`accordance with 37 C.F.R. § 42.106(a).
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`
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`IV.
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`IDENTIFICATION OF CHALLENGES
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`Petitioner asks that the Board review the accompanying prior art and
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`analysis thereof, and the supporting evidence, institute a trial for Inter Partes
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`Review of claims 10, 11, 15 and 16 of the ‘405 Patent, and cancel those claims as
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`invalid under 35 U.S.C. § 102 or 35 U.S.C. § 103. More specifically, Petitioner
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`requests cancellation of claims 10, 11, 15 and 16 of the ‘405 Patent on the
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`following grounds:
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`
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`Challenge #1: Claims 10, 11, 15 and 16 are anticipated under pre-AIA 35
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`U.S.C. § 102(b) by United States Application Publication No. 2011/0193081 to
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`Godo et al. (“Godo”; Ex. 1004). Godo was published on August 11, 2011 and is
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`prior art to the ‘405 Patent under pre-AIA 35 U.S.C. § 102(b).
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`3
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`Challenge #2: 10, 15 and 16 are anticipated under pre-AIA 35 U.S.C. §
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`Petition for Inter Partes Review
`U.S. Patent No. 9,281,405
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`
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`102(b) by United States Application Publication No. 2008/0299693 to Toyota et al.
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`(“Toyota”; Ex. 1005). Toyota was published on December 4, 2008 and is prior art
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`to the ‘405 Patent under pre-AIA 35 U.S.C. § 102(b).
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`
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`Challenge #3: Claim 11 is obvious under pre-AIA 35 U.S.C. 103(a) over
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`Toyota (Ex. 1005) in view of Godo (Ex. 1004)
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`
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`V.
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`BACKGROUND
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`A.
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`Technology
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`Semiconductor devices are electronic components that exploit the electronic
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`properties of semiconductor materials, such as silicon. Semiconductor materials
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`are useful because their behavior can be easily manipulated by the addition of
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`impurities, known as doping. Current conduction in a semiconductor occurs via
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`mobile or “free” electrons and holes, collectively known as charge carriers. Doping
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`a semiconductor such as silicon with a small proportion of an atomic impurity,
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`such as phosphorus, greatly increases the number of free electrons or holes within
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`the semiconductor (a doped semiconductor containing excess holes is called “p-
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`type”; one containing excess free electrons is known as “n-type”).
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`
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`A thin film transistor, or TFT, is an example of semiconductor device. TFTs
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`can be used as simple ON/OFF switches in a wide variety of electrical devices,
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`4
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`such as active-matrix LCD displays. Basically, a TFT consists of a semiconductor
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`Petition for Inter Partes Review
`U.S. Patent No. 9,281,405
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`and three electrodes: (i) the gate electrode; (ii) the source electrode; and (iii) the
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`drain electrode. The gate electrode must be insulated from the semiconductor by a
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`dielectric layer (or gate insulation layer), while the drain electrode and source
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`electrode must both directly contact the semiconductor. Because of this, TFTs
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`generally have one of the following configurations:
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`where “coplanar” in the drawings above refers to the gate electrode being on the
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`same side of the semiconductor as the source and drain electrode; “staggered”
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`refers to the gate electrode being on the opposite side of the semiconductor; and
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`“top” and “bottom” refer to the location of the gate electrode relative to the other
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`layers.
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`Petition for Inter Partes Review
`U.S. Patent No. 9,281,405
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`B.
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`The ‘405 Patent
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`According to the specification, the ‘405 Patent relates “to a semiconductor
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`
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`device typified by a transistor and a method for manufacturing the semiconductor
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`device.” Ex. 1001 at 1:18-20.
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`
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`The specification discloses that
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`a semiconductor device including a gate electrode layer; a gate
`insulating layer on and in contact with the gate electrode layer; an
`oxide semiconductor layer being on and in contact with the gate
`insulating layer and overlapping with the gate electrode layer; a first
`conductive layer and a second conductive layer provided on and in
`contact with the oxide semiconductor layer apart from each other with
`the gate electrode layer provided therebetween; a first low-resistance
`material layer on and in contact with the first conductive layer; a
`second low-resistance material layer on and in contact with the second
`conductive layer; a first protective layer on and in contact with the
`first conductive layer, the first low-resistance material layer, the
`second conductive layer, and the second low-resistance material layer;
`and a second protective layer in contact with a part of the oxide
`semiconductor layer. In the semiconductor device, a distance between
`the first conductive layer and the second conductive layer is shorter
`than a distance between the first low-resistance material layer and the
`second low-resistance material layer. The first conductive layer and
`the first low-resistance material layer serve as a source electrode and
`the second conductive layer and the second low-resistance material
`layer serve as a drain electrode.
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`Ex. 1001 at 4:40-63.
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`Petition for Inter Partes Review
`U.S. Patent No. 9,281,405
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`C.
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`Prosecution History
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`The prosecution history of the ‘405 Patent (Ex. 1002) is relatively brief, with
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`the majority of the claims, including the challenged claims being allowed in the
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`first Office Action on the merits. Ex. 1002 at 8-18.
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`Neither of the references relied upon herein was cited or considered during
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`the prosecution of the ‘405 Patent. Ex. 1003 at ¶ 31.
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`
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`VI. PERSON OF ORDINARY SKILL IN THE ART
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`
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`A United States patent is to be read and understood from the perspective of a
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`person of ordinary skill in the relevant art (technical field) at the time the invention
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`was made. Here, the relevant date is December 23. 2011, i.e. when the inventors
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`named on the ‘405 Patent filed the original Japanese patent applications to the
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`subject matter now claimed in the ‘405 Patent and to which priority is claimed.
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`
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`A person of ordinary skill in the art is a hypothetical person presumed to
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`know the relevant prior art. See, e.g., Gnosis S.p.A. v. South Alabama Med. Sci.
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`Found., IPR2013-00116, Final Written Decision (Paper 68) at 9. Such a person is
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`of ordinary creativity, not merely an automaton, and is capable of combining the
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`teachings of the prior art. See id., citing KSR Int’l Co. v. Teleflex Inc., 550 U.S.
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`398, 420-21 (2007). The factors that may be used to determine the level of skill of
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`a person of ordinary skill in the art may include the education level of those
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`7
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`working in the field, the sophistication of the technology, the types of problems
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`Petition for Inter Partes Review
`U.S. Patent No. 9,281,405
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`encountered in the art, prior art solutions to those problems and the speed at which
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`innovations in the art are made and implemented.
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`In this case, the ‘405 Patent is directed to semiconductor devices, such as the
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`thin film transistors (“TFTs”) found in many display devices. Petitioner therefore
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`submits that a person of ordinary skill should have some at least some familiarity
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`with the practical aspects of fabricating TFTs. Ex. 1003 at ¶ 25. Accordingly,
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`Petitioner submits that a person of ordinary skill in the art of the ‘405 Patent as of
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`December 23, 2011, would have had at least a bachelor of science or engineering
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`degree in electrical engineering, semiconductor technology, physics, or a related
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`field, and either an advanced degree (such as a masters) or an equivalent amount of
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`work experience, i.e. 2-3 years, in an area relating to semiconductor design and/or
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`fabrication, liquid crystal display (“LCD”) design or fabrication, electrical
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`engineering, or a related technical field. Id. at ¶ 25.
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`VII. CLAIM CONSTRUCTION
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`
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`Petitioner submits that no claim term in any of the challenged claims appears
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`to require construction.
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`Petition for Inter Partes Review
`U.S. Patent No. 9,281,405
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`VIII. IDENTIFICATION OF HOW EACH CHALLENGED CLAIM OF
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`THE ‘405 PATENT IS UNPATENTABLE
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`As discussed in detail below, the challenged claims are unpatentable over
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`the prior art.
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`A. Challenge #1: Claims 10, 11, 15 and 16 are anticipated
`under pre-AIA 35 U.S.C. § 102(b) by Godo
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`Godo (Ex. 1004) was published on August 11, 2011. Since the first
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`application in the United States from which the ‘405 Patent claims priority was
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`filed on December 17, 2012, Godo qualifies as prior art against the ‘405 Patent
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`under pre-AIA 35 U.S.C. § 102(b).
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`
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`“‘Anticipation’” in patent terms means that the claimed invention is not new;
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`that is, the invention as claimed was already known.” Ericson Inc. v. Intellectual
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`Ventures LLC, ___ F.3d ___, ___ (Fed. Cir. 2018). A finding of anticipation
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`requires that every limitation of the claim is present in a single prior art reference.
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`See, e.g., Blue Calypso, LLC v. Groupon, Inc., 815 F.3d 1331, 1341 (Fed. Cir.
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`2016); In re Gleave, 560 F.3d 1331, 1334 (Fed. Cir. 2009).
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`
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`In at least FIG. 1B and the accompanying text in the specification, Godo
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`discloses a semiconductor device having all of the same layers that are recited in
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`each of claims 10, 11, 15 and 16 and those layers are arranged in the same order as
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`required by the challenged claims. Ex. 1003 at ¶¶ 34-90. Godo therefore
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`anticipates each of claims 10, 11, 15 and 16 of the ‘405 Patent. That is, “each and
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`9
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`every element” of claims 10, 11, 15 and 16 of the ‘405 Patent is identically
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`Petition for Inter Partes Review
`U.S. Patent No. 9,281,405
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`disclosed by Godo, “arranged or combined in the same way as in the claim.”
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`Ericson Inc. v. Intellectual Ventures LLC, ___ F.3d ___, ___ (Fed. Cir. 2018)
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`(citing Blue Calypso, 815 F.3d at 1341).
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`
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`With reference to the specific embodiments disclosed in the specification,
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`Godo teaches that
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`A transistor 180 illustrated in FIG. 1A includes, over a substrate 100,
`a gate electrode 148, a gate insulating layer 146 provided over the
`gate electrode 148, an oxide semiconductor layer 144a provided over
`the gate insulating layer 146, an insulating layer 150a provided on and
`in contact with the oxide semiconductor layer 144a, and a source
`electrode 141a and a drain electrode 141b provided over the gate
`insulating layer 146 and the insulating layer 150a.
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`Ex. 1004 at ¶ 52.
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`
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`Godo’s FIG. 1B depicts an alternate structure for this semiconductor device
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`“in which the source electrode 141a has a structure in which a second conductive
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`layer 145a and a first conductive layer 142a are stacked in this order and the drain
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`electrode 141b has a structure in which a second conductive layer 145b and a first
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`conductive layer 142b are stacked in this order.” Ex. 1004 at ¶ 55.
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`10
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`Godo’s FIG. 1B is reproduced below:
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`Petition for Inter Partes Review
`U.S. Patent No. 9,281,405
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`where:
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`144a is the semiconductor layer (Ex. 1004 at ¶¶ 52, 55);
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`148 is the gate electrode (Ex. 1004 at ¶¶ 52, 55);
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`142b and 145b are each conductive layers that together form the drain
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`electrode 141b (Ex. 1004 at ¶¶ 52, 55);
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`142a and 145a are each conductive layers that together form the source
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`electrode 141a (Ex. 1004 at ¶¶ 52, 55); and
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`
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`146 is the gate insulating layer (Ex. 1004 at ¶¶ 52, 55).
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`Petition for Inter Partes Review
`U.S. Patent No. 9,281,405
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`1.
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`Claim 10
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`a.
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`The preamble
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`The preamble of claim 10 of the ‘405 Patent recites “[a] semiconductor
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`device comprising . . ..” Ex. 1001 at 29:48. If deemed a limitation, then this
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`limitation is expressly disclosed by Godo. Ex. 1003 at ¶ 35. Specifically, Godo
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`discloses that “[T]he present invention relates to a semiconductor device.” Ex.
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`1004 at ¶ 1.
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`Accordingly, to the extent the preamble is limiting, this limitation is
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`identically disclosed by Godo. Ex. 1003 at ¶ 36.
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`b.
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`a gate electrode layer
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`The first element of claim 10 is a gate electrode layer. Ex. 1001 at 29:49.
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`Godo identically discloses this element. Ex. 1003 at ¶ 37.
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`Godo discloses a semiconductor device having a gate electrode layer. Ex.
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`1004 at ¶ 51. Referring to FIG. 1B, Godo teaches that “FIGS. 1A and 1B each
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`illustrate a cross-sectional structure of a transistor as an example of a
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`semiconductor device. A transistor . . . includes, over a substrate 100, a gate
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`electrode 148 . . ..” Ex. 1004 at ¶ 52.
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`Godo therefore identically discloses the gate electrode layer limitation of
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`claim 10. Ex. 1003 at ¶ 40.
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`Petition for Inter Partes Review
`U.S. Patent No. 9,281,405
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`c.
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`a gate insulating layer . . .
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`The second element of claim 10 is a gate insulating layer over the gate
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`electrode layer. Ex. 1001 at 29:50. Godo identically discloses this element, and in
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`the same arrangement as recited in the claim. Ex. 1003 at ¶ 41.
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`
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`Godo discloses a semiconductor device having a gate insulating layer over
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`the gate electrode layer. Ex. 1003 at ¶ 42. Godo teaches that the transistor
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`“includes, . . . a gate insulating layer 146 provided over the gate electrode 148 . .
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`..” Ex. 1004 at ¶ 52.
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`
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`Godo’s FIG. 1B is reproduced below:
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`As shown in FIG. 1B above, the gate insulating layer 146 is over, and directly on
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`top of, the gate electrode 148. Ex. 1003 at ¶ 43.
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`
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`Godo therefore identically discloses the gate insulating layer over the gate
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`electrode layer limitation of claim 10. Ex. 1003 at ¶ 44.
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`d.
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`a semiconductor layer . . .
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`The third element of the semiconductor device of claim 10 is a
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`semiconductor layer over the gate insulating layer. Ex. 1001 at col. 29:51. Godo
`13
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`identically discloses this element, and in the same arrangement as recited in the
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`Petition for Inter Partes Review
`U.S. Patent No. 9,281,405
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`claim. Ex. 1003 at ¶ 45.
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`
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`Godo discloses a semiconductor device having a semiconductor layer over
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`the gate insulating layer. Ex. 1003 at ¶ 46. Godo teaches that the transistor
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`“includes . . . an oxide semiconductor layer 144a provided over the gate insulating
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`layer 146 . . ..” Ex. 1004 at ¶ 52.
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`
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`Godo’s FIG. 1B is reproduced below:
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`As depicted in this FIG. 1B, the semiconductor layer 144a is over, and directly on
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`top of, the gate insulating layer 146. Ex. 1003 at ¶ 47.
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`
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`Godo therefore identically discloses the semiconductor layer over the gate
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`insulating layer limitation of claim 10. Ex. 1003 at ¶ 48.
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`e.
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`a first conductive layer . . .
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`The fourth element of the semiconductor device of claim 10 is a first
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`conductive layer and a second conductive layer over the semiconductor layer. Ex.
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`1001 at col. 29:52-53. Godo identically discloses this element, and in the same
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`arrangement as recited in the claim. Ex. 1003 at ¶ 49.
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`14
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`Godo discloses a semiconductor device having a source electrode and a
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`drain electrode. Ex. 1003 at ¶ 50. Godo teaches that the transistor “includes, . . .
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`a source electrode 141a and a drain electrode 141b . . ..” Ex. 1004 at ¶ 52.
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`Godo’s FIG. 1B is reproduced below:
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`As can be seen in this FIG., the source electrode 141a is composed of two layers,
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`142a and 145a, and the drain electrode 141b is also composed of two layers, 142b
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`and 145b. Ex. 1003 at ¶ 51.
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`Godo discloses that FIG. 1B depicts “a structure in which the source
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`electrode 141a has a structure in which a second conductive layer 145a and a first
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`conductive layer 142a are stacked in this order and the drain electrode 141b has a
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`structure in which a second conductive layer 145b and a first conductive layer
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`142b are stacked in this order may be employed.” Ex. 1004 at ¶ 55. Thus, Godo
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`discloses that the two layers that compose the source electrode are both conductive
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`layers and the two layers that compose the drain electrode are both conductive
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`layers. Ex. 1003 at ¶ 52. Godo’s conductive layer 145a corresponds to the
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`claimed first conductive layer and Godo’s conductive layer 145b corresponds to
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`the claimed second conductive layer. Id.
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`Godo teaches that the “source electrode 141a and a drain electrode 141b
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`[are] provided over the gate insulating layer 146 and [the] layer 150a” and that
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`“layer 150a [is] provided on and in contact with the oxide semiconductor layer
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`144a.” Ex. 1004 at ¶ 53. Thus, the lower layer of the source electrode 145a and
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`the lower layer of the drain electrode 145b are over layer 150a which is, in turn,
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`directly on top of (and in contact with) the semiconductor layer 144a. Based on
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`this arrangement, and as clearly shown in FIG. 1B above, the lower layer of the
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`source electrode 145a (the first conductive layer) and the lower layer of the drain
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`electrode 145b (the second conductive layer) are over the semiconductor layer
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`144a. Ex. 1003 at ¶ 53.
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`Godo therefore identically discloses the first conductive layer and a second
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`conductive layer over the semiconductor layer limitation of claim 10. Ex. 1003 at
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`¶ 54.
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`f.
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`a third conductive layer . . .
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`The next element of claim 10 is a third conductive layer over the first
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`conductive layer. Ex. 1001 at 29:54. Godo identically discloses this element, and
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`in the same arrangement as recited in the claim. Ex. 1003 at ¶ 55.
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`Godo’s FIG. 1B depicts an alternate structure for a semiconductor device “in
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`which the source electrode 141a has a structure in which a second conductive layer
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`145a and a first conductive layer 142a are stacked in this order and the drain
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`electrode 141b has a structure in which a second conductive layer 145b and a first
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`conductive layer 142b are stacked in this order.” Ex. 1004 at ¶ 55. Godo’s 145a
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`corresponds to the claimed first conductive layer and Godo’s 142a corresponds to
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`the claimed third conductive layer. Ex. 1003 at ¶ 56.
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`Godo’s FIG. 1B is shown below:
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`where 142a and 145a are the two conductive layers that together form the source
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`electrode 141a. Ex. 1004 at ¶ 55; Ex. 1003 at ¶ 57. As can be seen in this FIG.,
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`the third conductive layer 142a is stacked above (over) and, indeed, directly on top
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`of, the first conductive layer 145a. Ex. 1003 at ¶ 57.
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`Godo therefore identically discloses the third conductive layer over the first
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`conductive layer limitation of claim 10. Ex. 1003 at ¶ 58.
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`g.
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`a fourth conductive layer . . .
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`The next element of claim 10 is a fourth conductive layer over the second
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`conductive layer. Ex. 1001 at 29:55-56. Godo identically discloses this element,
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`and in the same arrangement as recited in the claim. Ex. 1003 at ¶ 59.
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`Godo’s FIG. 1B depicts a semiconductor device “in which the source
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`electrode 141a has a structure in which a second conductive layer 145a and a first
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`conductive layer 142a are stacked in this order and the drain electrode 141b has a
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`structure in which a second conductive layer 145b and a first conductive layer
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`142b are stacked in this order.” Ex. 1004 at ¶ 55; Ex. 1003 at ¶ 60. Godo’s 145b
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`corresponds to the claimed second conductive layer and Godo’s 142b corresponds
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`to the claimed fourth conductive layer. Ex. 1003 at ¶ 60.
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`Godo’s FIG. 1B is reproduced below:
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`where 142b and 145b are the two conductive layers that together form the drain
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`electrode 141b. Ex. 1003 at ¶ 61. As shown in this FIG., the fourth conductive
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`layer 142b is stacked above (over) and, indeed, directly on top of, the second
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`conductive layer 145b.
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`Godo therefore identically discloses the fourth conductive layer over the
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`second conductive layer limitation of claim 10. Ex. 1003 at ¶ 62.
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`h.
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`a first insulating layer . . .
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`The final element of claim 10 of the ‘405 Patent is a first insulating layer
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`over the third conductive layer and the fourth conductive layer. Ex. 1001 at 29:57-
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`58. Godo identically discloses this element, and in the same arrangement as
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`recited in the claim. Ex. 1003 at ¶ 63.
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`Godo discloses that a “protective insulating layer” is formed over the
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`semiconductor device after formation of the source electrode and the drain
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`electrode. Ex. 1004 at ¶ 110; Ex. 1003 at ¶ 64. More specifically, Godo teaches
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`that a “second heat treatment is performed after the source electrode 141a and the
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`drain electrode 141b are formed in this embodiment; however, the timing of the
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`second heat treatment is not particularly limited to this. For example, the second
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`heat treatment may be performed after a protective insulating layer is formed
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`over the transistor . . ..” Ex. 1004 at ¶ 110 (emphasis added).
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`Godo’s FIG. 1B is shown below:
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`where 190 is the transistor and 142a and 142b are the upper conductive layers of
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`the source electrode 141a and the drain electrode 141b, respectively (i.e. the
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`claimed third conductive layer and the claimed fourth conductive layer,
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`respectively). Ex. 1004 at ¶ 55; Ex. 1003 at ¶ 65.
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`Since Godo teaches that the “protective insulating layer” is to be formed
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`over the transistor, when formed over the transistor 190 shown in FIG. 1B, the
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`“protective insulating layer” will be on top of, and therefore over, the upper layer
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`of the source electrode 142a (i.e. the claimed third conductive layer) and the upper
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`layer of the drain electrode 142b (i.e. the claimed fourth conductive layer). Ex.
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`1003 at ¶ 66.
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`Godo therefore identically discloses the first insulating layer over the third
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`conductive layer and the fourth conductive layer limitation of claim 10. Ex. 1003
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`at ¶ 67.
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`i.
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`the wherein clauses
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`The final limitations of claim 10 are two wherein clauses relating to the
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`claimed first conductive layer, second conductive layer, third conductive layer and
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`fourth conductive layer. As described below, Godo identically discloses both of
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`these features of the claimed semiconductor device. Ex. 1003 at ¶ 68.
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`i.
`wherein a distance between the first conductive
`layer and the second conductive layer is shorter than a
`distance between the third conductive layer and the
`fourth conductive layer
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`The first wherein clause relates to the distance between the upper layers of
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`the electrodes (142a and 142b) and the distance between the lower layers of the
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`electrodes (145a and 145b). Ex. 1001 at 29:59-62; Ex. 1003 at ¶ 69. More
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`specifically, the first wherein clause of claim 10 requires that a distance between
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`the first conductive layer and the second conductive layer is shorter than a
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`distance between the third conductive layer and the fourth conductive layer. Ex.
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`1001 at 29:59-62. Godo identically discloses this feature. Ex. 1003 at ¶ 69.
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`Godo’s FIG. 1B is shown below:
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`A magnification of a region of the transistor 190 in the FIG. 1B above, with the
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`relevant distances identified by double-headed arrows, is depicted below:
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`As shown in this magnification of the portion of interest of FIG. 1B, Godo
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`discloses a semiconductor device in which the distance between the edge of the
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`lower layer of the source electrode and the edge of the lower layer of the drain
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`electrode (represented by the blue arrow) is shorter than the distance between the
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`edge of the upper layer of the source electrode and the edge upper layer of the
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`drain electrode (represented by the green arrow). Ex. 1004 at FIG. 1B; Ex. 1003 at
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`¶ 70.
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`Godo therefore teaches that the distance between the first conductive layer
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`and the second conductive layer is shorter than [the] distance between the third
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`conductive layer and the fourth conductive layer as required by Claim 10. Ex.
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`1003 at ¶ 71.
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`ii.
`wherein the first conductive layer and the third
`conductive layer serve as a source electrode and the
`second conductive layer and the fourth conductive layer
`serve as a drain electrode
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`The second wherein clause relates to function of the four conductive layers
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`in the claimed semiconductor device. Ex. 1003 at ¶ 72. More specifically, the
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`second wherein clause of claim 10 requires that the first conductive layer and the
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`third conductive layer serve as a source electrode and the second conductive layer
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`and the fourth conductive layer serve as a drain electrode. Ex. 1001 at 30:1-4.
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`Godo identically discloses this feature. Ex. 1003 at ¶ 72.
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`Godo’s FIG. 1B depicts a semiconductor device “in which the source
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`electrode 141a has a structure in which a second conductive layer 145a and a first
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`conductive layer 142a are stacked in this order and the drain electrode 141b has a
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`structure in which a second conductive layer 145b and a first conductive layer
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`142b are stacked in this order.” Ex. 1004 at ¶ 55. And, as described above,
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`Godo’s 145a corresponds to the claimed first conductive layer, Godo’s 145b
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`corresponds to the claimed second conductive layer, Godo’s 142a corresponds to
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`the claimed third conductive layer and Godo’s 142b corresponds to the claimed
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`fourth conductive layer. Ex. 1003 at ¶ 73. Thus, the first conductive layer 145a
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`and the third conductive layer 142a together form the source electrode 141a.
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`Likewise, the second conductive layer 145b and the fourth conductive layer 142b
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`that together form the drain electrode 141b. Id. at ¶¶ 74-75.
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`Godo therefore teaches that the first conductive layer and the third
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`conductive layer serve as a source electrode and the second conductive layer and
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`the fourth conductive layer serve as a drain electrode as required by Claim 10. Ex.
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`1003 at ¶ 76.
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`2.
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`Claim 11
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`Claim 11 of the ‘405 Patent depends directly from Claim 10, and therefore
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`contains all of the limitations of Claim 10 as if recited fully therein. Accordingly,
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`each of these limitations is expressly disclosed by Godo for the same reasons as
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`provided with respect to claim 10 above in section VIII.A.1. (which is herein
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`incorporated i