UNITED STATES PATENT AND TRADEMARK OFFICE
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`_____________________________
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`IN THE UNITED STATES PATENT TRIAL AND APPEAL BOARD
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`_____________________________
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`BLUEHOUSE GLOBAL LTD.
`Petitioner
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`v.
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`SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
`Patent Owner
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`_____________________________
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`CASE IPR: 2018-01382
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`U.S. PATENT NO. 9,601,603 B2
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`_____________________________
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`PETITION FOR INTER PARTES REVIEW
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`i
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`Mail Stop Patent Board
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
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`_____________________________
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`IN THE UNITED STATES PATENT TRIAL AND APPEAL BOARD
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`_____________________________
`
`
`BLUEHOUSE GLOBAL LTD.
`Petitioner
`
`v.
`
`
`SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
`Patent Owner
`
`
`
`
`_____________________________
`
`
`CASE IPR: 2018-01382
`
`U.S. PATENT NO. 9,601,603 B2
`
`_____________________________
`
`
`PETITION FOR INTER PARTES REVIEW
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`
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`i
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`Mail Stop Patent Board
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
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`Petition for Inter Partes Review
`U.S. Patent No. 9,601,603
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`Table of Contents
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`INTRODUCTION……………………………………………………. .....1
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`I.
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`II. MANDATORY NOTICES (37 C.F.R. § 42.8)……………………….....1
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`A. Real Parties-In-Interest (37 C.F.R. § 42.8(b)(1))………………..1
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`B. Related Matters (37 C.F.R. § 42.8(b)(2))…………………….......1
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`C. Lead and Backup Counsel (37 C.F.R. § 42.8(b)(3))……………..2
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`D.
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`Service Information (37 C.F.R. § 42.8(b)(4))………………….....2
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`III. GROUNDS FOR STANDING (37 C.F.R. § 42.104(a))………………..3
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`IV.
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`V.
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`IDENTIFICATION OF CHALLENGES………………………………3
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`BACKGROUND………………………………………………………....4
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`A.
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`B.
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`C.
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`Technology………………………………………………………...4
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`The ‘603 Patent………………………………………………...….5
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`Prosecution History……………………………………………….6
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`VI. PERSON OF ORDINARY SKILL IN THE ART……………………..6
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`VII. CLAIM CONSTRUCTION……………………………………………..8
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`VIII. IDENTIFICATION OF HOW EACH CHALLENGED
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`CLAIM OF THE ‘603 PATENT IS UNPATENTABLE….…………….9
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`A. Challenge #1: Claims 1, 2, 4, 5 and 8-10 are
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`anticipated under pre-AIA 35 U.S.C. § 102(b)
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`by Ishii….……………………………………….………......9
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`ii
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`Petition for Inter Partes Review
`U.S. Patent No. 9,601,603
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`1.
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`2.
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`3.
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`4.
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`5.
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`6.
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`7.
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`Claim 1.………………………………………………….. ..10
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`Claim 2..…………………………………………………. ..23
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`Claim 4..…………………………………………………. ..25
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`Claim 5...………………………………………………… ..26
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`Claim 8..…………………………………………………. ..27
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`Claim 9..…………………………………………………. ..28
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`Claim 10.………………………………………………… ..29
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`B. Challenge #2: Claims 3, 6 and 7 are obvious under
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`pre-AIA 35 U.S.C. § 103(a) over Ishii in view of Akimoto…….30
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`1.
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`Claim 3......………………………………………………...31
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`Claim 6..…………………………………………………. ..35
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`Claim 7..…………………………………………………. ..37
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`2.
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`3.
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`C. Challenge #3: Claims 11-24 are anticipated under
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`pre-AIA 35 U.S.C. 102(b) by Akimoto..………..……………….40
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`1.
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`2.
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`3.
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`4.
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`5.
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`6.
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`Claim 11....………………………………………………...40
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`Claim 12…………………………………………………. ..49
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`Claim 13…………………………………………………. ..50
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`Claim 14....………………………………………………...51
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`Claim 15…………………………………………………. ..53
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`Claim 16…………………………………………………. ..54
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`iii
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`Petition for Inter Partes Review
`U.S. Patent No. 9,601,603
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`7.
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`8.
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`9.
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`Claim 17....………………………………………………...55
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`Claim 18…………………………………………………. ..56
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`Claim 19…………………………………………………. ..57
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`IX. CONCLUSION…………………………………………………..……..61
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`10. Claim 20....………………………………………………...57
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`11. Claim 21…………………………………………………. ..58
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`12. Claim 22…………………………………………………. ..59
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`13. Claim 23....………………………………………………...59
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`14. Claim 24…………………………………………………. ..60
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`iv
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`Petition for Inter Partes Review
`U.S. Patent No. 9,601,603
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`List of Exhibits
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`Ex. 1001 United States Letters Patent No. 9,601,603 B2
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`Ex. 1002
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`Prosecution history of U.S. Patent No. 9,601,603
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`Ex. 1003 Declaration of Richard A. Flasck
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`Ex. 1004 United States Patent Application Publication No. 2006/0278873 A1
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`(“Ishii”)
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`Ex. 1005 United States Patent Application Publication No. 2007/0072439 A1
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`(“Akimoto”)
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`v
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`I.
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`INTRODUCTION
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`BlueHouse Global Ltd. (“Petitioner”) hereby petitions for inter partes
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`review of claims 1-24 (the “challenged claims”) of U.S. Patent No. 9,601,603 (“the
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`‘603 Patent”) (Ex. 1001) under 35 U.S.C. §§ 311–319 and 37 C.F.R. § 42.
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`According to the assignment information on the front of the ‘603 Patent, and the
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`records of the United States Patent & Trademark Office (the “USPTO”), the ‘603
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`Patent is assigned to, and therefore owned by, Semiconductor Energy Laboratory
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`Co., Ltd. (the “Patent Owner”). For the reasons provided in detail below, the
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`challenged claims should be found unpatentable and canceled.
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`
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`II. MANDATORY NOTICES (37 C.F.R. § 42.8)
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`A. Real Parties-In-Interest (37 C.F.R. § 42.8(b)(1))
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`The real party-in-interest in this matter is Petitioner BlueHouse Global Ltd.
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`and its parent company, Caesar Global Fund.
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`B. Related Matters (37 C.F.R. § 42.8(b)(2))
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`As of the filing date of this Petition, Petitioner is unaware of any matters
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`involving the ‘603 Patent pending in any United States court or administrative
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`agency.
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`
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`1
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`
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`C. Lead and Backup Counsel (37 C.F.R. § 42.8(b)(3))
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`Petition for Inter Partes Review
`U.S. Patent No. 9,601,603
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`Lead Counsel:
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`Ryan O. White (USPTO Reg. No. 45,541)
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`TAFT, STETTINIUS & HOLLISTER LLP
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`One Indiana Square, Suite 3500
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`Indianapolis, IN 46204
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`Tel: (317) 713-3455
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`Fax: (317) 713-3699
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`Email: rwhite@taftlaw.com
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`Backup Counsel:
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`Roshan P Shrestha (No. 71,277)
`TAFT, STETTINIUS & HOLLISTER LLP
`111 East Wacker Dr. Suite 2800
`Chicago, IL 60601
`Tel: (312) 527-4000
`Fax: (312) 966-8573
`Email: rshrestha@taftlaw.com
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`
`Philip R. Bautista (pro hac vice
`authorization requested)
`TAFT, STETTINIUS & HOLLISTER LLP
`200 Public Square Suite 3500
`Cleveland, OH 44114-2302
`Tel: (216) 706-3957
`Fax: (216) 241-3707
`Email: pbautista@taftlaw.com
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`Petitioner hereby requests authorization to file a motion under 37 C.F.R. § 42.10(c)
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`for Backup Counsel Philip R. Bautista to appear pro hac vice, as Mr. Bautista is an
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`experienced litigating attorney and has an established familiarity with this subject
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`matter at issue in this proceeding. Petitioner intends to file such a motion once
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`authorization is granted.
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`D.
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`Service Information (37 C.F.R. § 42.8(b)(4))
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`Please address all correspondence to Lead Counsel at the mailing address
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`shown above. Petitioner also consents to electronic service by email.
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`2
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`III. GROUNDS FOR STANDING (37 C.F.R. § 42.104(a))
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`Petition for Inter Partes Review
`U.S. Patent No. 9,601,603
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`
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`Petitioner hereby certifies that: (1) the ‘603 Patent issued on March 21, 2017
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`and so is eligible for inter partes review; (2) Petitioner has not been served with a
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`complaint alleging infringement of any of the claims of the ‘603 Patent and so is
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`therefore not barred or estopped from requesting inter partes review of the ‘603
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`Patent on the grounds identified herein; and (3) Petitioner has not filed a complaint
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`challenging the validity of the ‘603 Patent. This Petition is being filed in
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`accordance with 37 C.F.R. § 42.106(a).
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`IV.
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`IDENTIFICATION OF CHALLENGES
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`Petitioner asks that the Board review the accompanying prior art and
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`analysis thereof, and the supporting evidence, institute a trial for Inter Partes
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`Review of claims 1-24 of the ‘603 Patent, and cancel those claims as invalid under
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`35 U.S.C. § 102 or 35 U.S.C. § 103. More specifically, Petitioner requests
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`cancellation of claims 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
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`20, 21, 22, 23 and 24 of the ‘603 Patent on the following grounds:
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`Challenge #1: Claims 1, 2, 4, 5 and 8-10 are anticipated under pre-AIA 35
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`U.S.C. § 102(b) over United States Patent Application Publication No.
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`2006/0278873 A1 to Ishii (“Ishii”; Ex. 1004). Ishii was published on December
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`14, 2006 and so is prior art to the ‘603 Patent under pre-AIA 35 U.S.C. § 102(b).
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`3
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`Challenge #2: Claims 3, 6 and 7 are obvious under pre-AIA 35 U.S.C.
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`Petition for Inter Partes Review
`U.S. Patent No. 9,601,603
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`103(a) over United States Patent Application Publication No. 2007/0072439 A1 to
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`Akimoto et al. (“Akimoto”; Ex. 1005) in view of Ishii. Akimoto was published on
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`March 29, 2007 and is therefore prior art to the ‘603 Patent under pre-AIA 35
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`U.S.C. § 102(b).
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`Challenge #3: Claims 11-24 are anticipated under pre-AIA 35 U.S.C.
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`102(b) by Akimoto.
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`V.
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`BACKGROUND
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`A.
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`Technology
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`Semiconductor devices are electronic components that exploit the electronic
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`properties of semiconductor materials, such as silicon. Semiconductor materials
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`are useful because their behavior can be easily manipulated by the addition of
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`impurities, known as doping. Current conduction in a semiconductor occurs via
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`mobile or “free” electrons and holes, collectively known as charge carriers. Doping
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`a semiconductor such as silicon with a small proportion of an atomic impurity,
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`such as phosphorus, greatly increases the number of free electrons or holes within
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`the semiconductor (a doped semiconductor containing excess holes is called “p-
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`type”; one containing excess free electrons is known as “n-type”).
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`4
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`A thin film transistor, or TFT, is an example of semiconductor device. TFTs
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`Petition for Inter Partes Review
`U.S. Patent No. 9,601,603
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`can be used as simple ON/OFF switches in a wide variety of electrical devices,
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`such as active-matrix LCD displays. Basically, a TFT consists of a semiconductor
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`and three electrodes: (i) the gate electrode; (ii) the source electrode; and (iii) the
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`drain electrode. The gate electrode must be insulated from the semiconductor by a
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`dielectric layer (or gate insulation layer), while the drain electrode and source
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`electrode must both directly contact the semiconductor. Because of this, TFTs
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`generally have one of the following configurations:
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`where “coplanar” in the drawings above refers to the gate electrode being on the
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`same side of the semiconductor as the source and drain electrode; “staggered”
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`refers to the gate electrode being on the opposite side of the semiconductor; and
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`5
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`“top” and “bottom” refer to the location of the gate electrode relative to the other
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`Petition for Inter Partes Review
`U.S. Patent No. 9,601,603
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`layers.
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`B.
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`The ‘603 Patent
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`According to the specification, the ‘603 Patent relates to “a semiconductor
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`device using an oxide semiconductor and a method for manufacturing the
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`semiconductor device.” Ex. 1001 at 1:6-8.
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`C.
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`Prosecution History
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`Neither of the references being relied upon herein was cited or considered
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`during the prosecution of the ‘603 Patent. Ex. 1003 at ¶ 30.
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`VI. PERSON OF ORDINARY SKILL IN THE ART
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`A United States patent is to be read and understood from the perspective of a
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`person of ordinary skill in the relevant art (technical field) at the time the invention
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`was made. Here, the relevant date is Oct. 24, 2008, i.e. when the inventors named
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`on the ‘603 Patent filed the original Japanese patent application to the subject
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`matter now claimed in the ‘603 Patent and to which priority is claimed.
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`A person of ordinary skill in the art is a hypothetical person presumed to
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`know the relevant prior art. See, e.g., Gnosis S.p.A. v. South Alabama Med. Sci.
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`Found., IPR2013-00116, Final Written Decision (Paper 68) at 9. Such a person is
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`of ordinary creativity, not merely an automaton, and is capable of combining the
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`6
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`teachings of the prior art. See id., citing KSR Int’l Co. v. Teleflex Inc., 550 U.S.
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`Petition for Inter Partes Review
`U.S. Patent No. 9,601,603
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`398, 420-21 (2007). The factors that may be used to determine the level of skill of
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`a person of ordinary skill in the art may include the education level of those
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`working in the field, the sophistication of the technology, the types of problems
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`encountered in the art, prior art solutions to those problems and the speed at which
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`innovations in the art are made and implemented.
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`In this case, the ‘603 Patent is directed to improving the process of
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`fabricating semiconductor devices, such as the thin film transistors (“TFTs”) found
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`in many display devices. Petitioner therefore submits that a person of ordinary
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`skill should have some at least some familiarity with the practical aspects of
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`fabricating TFTs. Ex. 1003 at ¶ 25. Accordingly, Petitioner submits that a person
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`of ordinary skill in the art of the ‘603 Patent as of October 24, 2008, would have
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`had at least a bachelor of science or engineering degree in electrical engineering,
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`semiconductor technology, physics, or a related field, and either an advanced
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`degree (such as a masters) or an equivalent amount of work experience, i.e. 2-3
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`years, in an area relating to semiconductor design and/or fabrication, liquid crystal
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`display (“LCD”) design or fabrication, electrical engineering, or a related technical
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`field. Id.
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`7
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`VII. CLAIM CONSTRUCTION
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`Petition for Inter Partes Review
`U.S. Patent No. 9,601,603
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`
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`The following constructions of certain claim terms are proposed by
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`Petitioner using the “broadest reasonable interpretation” standard currently
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`applicable for inter partes review. See 37 C.F.R. § 42.100(b); Cuozzo Speed
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`Techs. v. Lee, 579 U.S. ___, ___, 136 S. Ct. 2131, 2134 (2016). If, however, the
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`“plain and ordinary meaning” standard was applicable, Petitioner would still
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`propose the same constructions for the same reasons as provided below.
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`1.
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`“semiconductor device” (claims 1-7 and 9-19)
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`This term appears in the preamble of all of the challenged claims. This term
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`is not defined in the specification of the ‘603 Patent, but the specification does
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`state that “[a]s a semiconductor device having a driver circuit, besides a liquid
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`crystal display device, a light-emitting display device using a light-emitting
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`element and a display device using an electrophoretic display element, which is
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`also referred to electronic paper, can be given.” Ex. 1001 at 1:7-9. Petitioner
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`therefore submits that the claim term semiconductor device should be construed to
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`mean “a device that functions by utilizing semiconductor characteristics, such as a
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`liquid crystal display device or a light-emitting display device.” Ex. 1003 at ¶ 32.
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`2.
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`“over” (claims 1-7 and 9-19)
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`This term appears in all of the challenged claims. The specification of the
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`‘603 Patent does not define this term, but generally speaking, in the field of the
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`8
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`invention claimed in the ‘603 Patent, a word which expresses a direction, such as
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`Petition for Inter Partes Review
`U.S. Patent No. 9,601,603
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`“over” or “below,” usually indicates a direction based on the substrate surface (in
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`cases where the device is provided over or on the surface of the substrate). Ex.
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`1003 at ¶ 33. Petitioner therefore submits that the claim term over should be
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`construed to mean “above.” Id.
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`VIII. IDENTIFICATION OF HOW EACH CHALLENGED CLAIM OF
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`THE ‘603 PATENT IS UNPAENTABLE
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`As discussed in detail below, the challenged claims are unpatentable over
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`the prior art.
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`A. Challenge #1: Claims 1, 2, 4, 5 and 8-10 are anticipated under
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`pre-AIA 35 U.S.C. § 102(b) by Ishii
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`Ishii (Ex. 1004) was published on December 14, 2006. Since the application
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`from which the ‘603 Patent issued was first filed in the United States on October
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`20, 2009, Ishii qualifies as prior art against the ‘603 Patent under pre-AIA 35
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`U.S.C. § 102(b).
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`“‘Anticipation’” in patent terms means that the claimed invention is not new;
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`that is, the invention as claimed was already known.” Ericsson Inc. v. Intellectual
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`Ventures LLC, 890 F.3d 1336, 1338 (Fed. Cir. 2018). A finding of anticipation
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`requires that every limitation of the claim is present in a single prior art reference.
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`9
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`See, e.g., Blue Calypso, LLC v. Groupon, Inc., 815 F.3d 1331, 1341 (Fed. Cir.
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`Petition for Inter Partes Review
`U.S. Patent No. 9,601,603
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`2016); In re Gleave, 560 F.3d 1331, 1334 (Fed. Cir. 2009).
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`Ishii anticipates each of claims 1, 2, 4, 5 and 8-10 of the ‘603 Patent. That
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`is, “each and every element” of claims 1, 2, 4, 5 and 8-10 of the ‘603 Patent is
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`identically disclosed by Ishii, “arranged or combined in the same way as in the
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`claim.” Ericson Inc., 890 F.3d at 1346 (citing Blue Calypso, 815 F.3d at 1341).
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`Specifically, in at least FIGS. 1 and 2 and the accompanying text in the
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`specification, Ishii discloses a method of manufacturing a semiconductor device
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`(such as a thin film transistor for use in a display device) having the same layers as
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`recited in each of claims 1, 2, 4, 5 and 8-10, and formed such that the layers are
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`“arranged or combined in the same way” as in those claims. Ex. 1003 at ¶ 35.
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`1.
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`Claim 1
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`a.
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`The preamble
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`The preamble of claim 1 recites “[a] method of manufacturing a
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`semiconductor device comprising . . ..” Ex. 1001 at 40:17-18. To the extent that
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`this preamble is deemed a limitation, this limitation is expressly disclosed by Ishii.
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`Ex. 1003 at ¶ 36.
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`Ishii discloses a liquid crystal display (“LCD”) device. Ex. 1004 at ¶ 34.
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`More specifically, Ishii discloses that
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`10
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`Petition for Inter Partes Review
`U.S. Patent No. 9,601,603
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`A concrete configuration of this liquid crystal display apparatus will
`now be described with reference to FIG. 2. A gate electrode 11 and
`the scanning line 2 (see FIG. 1) electrically connected with the gate
`electrode 11 are provided at a predetermined position on an upper
`surface of the thin film transistor substrate 1.
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`Id. Ishii also discloses a method of manufacturing this LCD device:
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`As a method of forming the gate electrodes 11 and the scanning lines
`2, there is recommended a method of forming a metal film by a
`sputtering technique targeting a metal oxide film containing the n-type
`or p-type impurities and patterning this film by using a
`photolithography technique.
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`Id. at ¶ 35.
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`Accordingly, to the extent the preamble is limiting, this limitation is
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`identically disclosed by Ishii. Ex. 1003at ¶ 38.
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`b.
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`forming a first conductive film . . .
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`The first limitation of claim 1 is forming a first conductive film that serves
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`as a gate electrode of a transistor. Ex. 1001 at 40:19-20. Ishii discloses a method
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`of manufacturing an LCD device that includes this step. Ex. 1003 at ¶ 39.
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`
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`More specifically, Ishii discloses a method of manufacturing an LCD device
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`that includes forming gate electrodes:
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`As a method of forming the gate electrodes 11 and the scanning
`lines 2, there is recommended a method of forming a metal film by
`a sputtering technique targeting a metal oxide film containing the n-
`type or p-type impurities and patterning this film by using a
`photolithography technique.
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`11
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`Ex. 1004 at ¶ 35 (emphasis added). It is well known by those skilled in the art that
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`Petition for Inter Partes Review
`U.S. Patent No. 9,601,603
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`a metal film is a conductive film (i.e. a film that can conduct electrons). Ex. 1003
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`at ¶ 40.
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`Ishii therefore identically discloses the forming a first conductive film that
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`serves as a gate electrode of a transistor limitation of claim 1. Id. at ¶ 41.
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`c.
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`forming a first insulating film . . .
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`The second limitation of claim 1 is forming a first insulating film over the
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`first conductive film. Ex. 1001 at 40:21-22. Ishii discloses a method of
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`manufacturing an LCD device that includes this step. Ex. 1003 at ¶ 42.
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`More specifically, Ishii discloses that, after forming the gate electrodes 11
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`(the first conductive film), “[a] gate insulating film 12 made of silicon nitride is
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`provided on upper surfaces of the gate electrodes 11, the scanning lines 2 and
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`the thin film transistor substrate 1.” Ex. 1004 at ¶ 36 (emphasis added). By
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`providing the gate insulating film 12 “on upper surfaces” of the gate electrode, the
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`gate insulating film is above (over) and, in fact, directly on top of the gate
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`electrode. Ex. 1003 at ¶ 43.
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`Ishii therefore identically discloses the forming a first insulating film over
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`the first conductive film limitation of clam 1. Id. at ¶ 44.
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`12
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`d.
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`forming an oxide semiconductor layer . . .
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`The third limitation of claim 1 is forming an oxide semiconductor layer that
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`comprises a channel formation region over the first insulating film. Ex. 1001 at
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`40:23-24. The specification of the ‘603 Patent does not, however, specify whether
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`it is just the oxide semiconductor layer that is over the first insulating film or
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`whether it is the “channel formation region” thereof that is over the first insulating
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`film. Ex. 1003 at ¶ 45. Irrespective of which alternative is correct, Ishii discloses a
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`method of manufacturing an LCD device that includes this step. Id.
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`More specifically, Ishii discloses that, after forming the gate electrodes 11
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`(the first conductive film) and gate insulating film 12 (the first insulating film), “[a]
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`semiconductor thin film 13 made of the same transparent genuine metal oxide
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`having a band gap of 2.5V or above is provided on the upper surface of the gate
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`insulating film 12 above the gate electrode 11.” Ex. 1004 at ¶ 36 (emphasis
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`added). Ishii expressly teaches that this semiconductor thin film 13 is composed of
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`a metal oxide, i.e. semiconductor thin film 13 is an oxide semiconductor. Ex. 1003
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`at ¶ 46. Moreover, by providing the semiconductor thin film 13 “on the upper
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`surface” of the gate electrode, the oxide semiconductor layer is above (over) and
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`directly on top of the gate insulating film. Id.
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`Ishii further discloses that the semiconductor thin film 13 (the oxide
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`semiconductor layer) has a channel formation region over the gate insulating film
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`13
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`12 (the claimed first insulating film). Id. at ¶ 47. More specifically, Ishii discloses
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`that “[a] channel protection film 14 made of silicon nitride is provided at a
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`substantially central part on the upper surface of the semiconductor thin film 13.”
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`Ex. 1004 at ¶ 37. One skilled in the art would understand that a “channel
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`protection film” is a film that protects the channel region of a semiconductor. Ex.
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`1003 at ¶ 47. One skilled in the art would therefore recognize that “a channel
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`protection film” over the central part of the semiconductor thin film 13 necessarily
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`means that the semiconductor thin film 13 has a channel region in the same
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`location (i.e. “substantially the central part” thereof). Id.
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`Ishii’s FIG. 2 is reproduced below:
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`As can be seen in FIG. 2 above, the channel region of the semiconductor thin film
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`13 (the oxide semiconductor layer), which is directly below the channel protection
`14
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`region 14, is above (over) the gate insulating film 12 (the first insulating film), as is
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`the semiconductor thin film 13 (the oxide semiconductor layer). Id. at ¶ 48.
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`Ishii therefore identically discloses the forming a first insulating film over
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`the first conductive film limitation of clam 1. Id. at ¶ 49.
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`e.
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`forming a second insulating film . . .
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`The fourth limitation of claim 1 is forming a second insulating film over the
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`oxide semiconductor layer. Ex. 1001 at 40:25-26. Ishii discloses a method of
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`manufacturing an LCD device that includes this step. Ex. 1003 at ¶ 50.
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`More specifically, Ishii discloses that, after forming the semiconductor thin
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`film 13 (the oxide semiconductor layer),
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`A channel protection film 14 . . . is provided at a substantially central
`part on the upper surface of the semiconductor thin film 13. A source
`electrode 15, a drain electrode 16 and the data line 3 connected with
`the drain electrode 16 . . . are provided on positions of both sides of an
`upper surface of the channel protection film 14, the upper surface of
`the semiconductor thin film 13 on both sides of the channel protection
`film 14 and the upper surface of the gate insulating film 12.
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`Ex. 1004 at ¶ 37. Thus, Ishii discloses a structure of the following layers one on
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`top of the other, starting from the upper surface of the substrate at the bottom: a
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`gate electrode 11; a gate insulating film 12; a semiconductor thin film 13; and, at
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`the top, a date line 3 and source and drain electrodes 15, 16. Ex. 1003 at ¶ 51.
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`This is a bottom-gate thin film transistor. Id.; Ex. 1004 at ¶ 38.
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`15
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`Following construction of the transistor 5, Ishii discloses “[a]n interlayer
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`insulating film 17 made of silicon nitride is provided on the upper surfaces of the
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`thin film transistors 5, the data lines 3 and the gate insulating film 12.” Ex. 1004 at
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`¶ 39 (emphasis added). By providing the interlayer insulating film 17 “on the
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`upper surface[]” of the thin film transistor 5, the insulating film 17 (the second
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`insulating film) is above (over) the semiconductor thin film 13 (the oxide
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`semiconductor layer). Ex. 1003 at ¶ 52.
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`This relationship is confirmed by referring to Ishii’s FIG. 2, which is
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`reproduced below:
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`As can be seen in FIG. 2 above, the interlayer insulating film 17 (the second
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`insulating film) is above (over) the semiconductor thin film 13 (the oxide
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`16
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`semiconductor layer, with the source and drain electrodes 15 and 16 and the
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`U.S. Patent No. 9,601,603
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`channel protection region 14 in between. Ex. 1003 at ¶ 53.
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`Ishii therefore identically discloses the forming a second insulating film over
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`the oxide semiconductor layer limitation of clam 1. Id. at ¶ 54.
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`f.
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`forming a transparent film . . .
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`The fifth limitation of claim 1 is forming a transparent film over the second
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`insulating film by a sputtering method. Ex. 1001 at 40:27-28. Ishii discloses a
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`method of manufacturing an LCD device that includes this step. Ex. 1003 at ¶ 55.
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`More specifically, Ishii discloses that, after forming the interlayer insulating
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`film 17 (the second insulating film),
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`An overcoat film (an insulating film) 18 made of silicon nitride is
`provided on upper surfaces of the auxiliary capacitance electrode 6
`and the interlayer insulating film 17. . . The pixel electrode 4 made
`of a transparent metal oxide containing n-type or p-type impurities
`or a transparent electroconductive material such as ITO is provided
`on the upper surface of the overcoat film 18 at a predetermined
`position to be electrically connected with the source electrode 15
`through the contact hole 19.
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`Ex. 1004 at ¶ 40 (emphasis added). One skilled in the art would recognize that
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`because the pixel electrode 4 (the transparent film) is above (over) the overcoat
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`film 18 and the overcoat film 18 is above (over) the interlayer insulating film 17
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`(the second insulating film), then the pixel electrode 4 (the transparent film) must
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`17
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`be above (over) the interlayer insulating film 17 (the second insulating film). Ex.
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`1003 at ¶ 56.
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`This relationship is confirmed by referring to Ishii’s FIG. 2, which is
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`reproduced below:
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`
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`As can be seen from FIG. 2 above, the pixel electrode 4 (the transparent film) is
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`above (over) the interlayer insulating film 17 (the second insulating film). Id. at ¶
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`57.
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`Ishii further discloses that the electrodes in the disclosed LCD device can be
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`formed using a sputtering technique:
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`The source electrodes 15, the drain electrodes 16 and the data lines 3
`can be formed by the sputtering technique targeting the n-type metal
`oxide film and patterning this film by the photolithography technique,
`as used for the gate electrodes 11 and the scanning lines 2.
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`18
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`Ex. 1004 at ¶ 37. Because the pixel electrode 4 is also a metal oxide containing n-
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`type impurities, one skilled in the art would understand that sputtering should be
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`used in that case as well. Ex. 1003 at ¶ 58.
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`Ishii therefore identically discloses the forming a transparent film over the
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`second insulating film by a sputtering method limitation of clam 1. Id. at ¶ 59.
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`g.
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`the wherein clauses
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`The final two limitations of claim 1 are wherein clauses relating to the
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`transparent film. Ex. 1001 at 40:29-34. Ishii discloses a method of manufacturing
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`an LCD device that includes both features. Ex. 1003 at ¶ 60.
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`(i)
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`wherein the first conductive film and the
`transparent film overlap each other with the oxide
`semiconductor layer therebetween
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`The first wherein clause requires that the first conductive film and the
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`transparent film overlap each other with the oxide semiconductor layer
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`therebetween. Ex. 1001 at 40:29-31. Ishii discloses a method of manufacturing an
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`LCD device that includes this feature. Ex. 1003 at ¶ 61.
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`19
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`Ishii’s FIG. 2 is reproduced below:
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`U.S. Patent No. 9,601,603
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`As can be seen in FIG. 2 above, the pixel electrode 4 (the transparent film) is
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`above and covers (overlaps) the gate electrode 11 (the first conductive film). Id. at
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`¶ 62. Moreover, in the stacked arrangement of layers, the pixel electrode 4 is
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`above the semiconductor thin film 13 and the gate electrode 11 is below the
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`semiconductor film 13. Id. Thus, the semiconductor thin film 13 (the oxide
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`semiconductor layer) is between the gate electrode 11 (the first conductive film)
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`and the pixel electrode 4 (the transparent film). Id.
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`Ishii therefore identically discloses the first conductive film and the
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`transparent film overlap each other with the oxide semiconductor layer
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`therebetween limitation of clam 1. Id. at ¶ 63.
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`(ii) wherein the transparent film has a larger width
`than the oxide semiconductor layer in a channel width
`direction of the transistor
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`The second wherein clause requires that the transparent film has a larger
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`width than the oxide semiconductor layer in a channel width direction of the
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`transistor. Ex. 1001 at 40:32-34. Ishii discloses a method of manufacturing an
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`LCD device that includes this feature. Ex. 1003 at ¶ 64.
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`Ishii’s FIG. 1, with the TFT identified and magnified, is reproduced below:
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`In describing FIG. 1, Ishii discloses that “the thin film transistor 5 is arranged on a
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`channel width
`direction
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`lower side of a left lower corner portion of the pixel electrode 4 and [is]
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`substantially entirely covered with the pixel electrode 4.” Ex. 1004 at ¶ 30
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`(emphasis added). One skilled in the art would understand that, because the pixel
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`electrode 4 (the transparent film) substantially entirely covers the thin film
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`transistor 5 (which includes all of the oxide semiconductor layer), it necessarily
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`21
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`has a larger width than the oxide semiconductor layer in a channel width direction
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`of the transistor. Ex. 1003 at ¶ 65. In fact, because the pixel electrode 4
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`substantially entirely covers the thin film transistor 5, it necessarily has a larger
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`width than the TFT (and, of course, the semiconductor thin film that is a part of
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`that TFT, in every direction in the horizontal plane. Id.
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`In addition, although the semiconductor thin film is not specifically shown
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`or identified in Ishii’s FIG. 1 above, Ishii’s FIG. 3, reproduced below, does
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`identify the semiconductor thin film 13 in that embodiment:
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`According to Ishii, the difference between the embodiment depicted in FIG. 1 and
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`that depicted in FIG. 3 above is that the former has a bottom-gate TFT while the
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`latter has a top-gate TFT. Ex. 1004 at ¶ 61. One skilled in the art would therefore
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`22
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`understand that the semiconductor thin film 13 depicted in FIG. 3 is substantially
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`similar in size and shape to the semiconductor thin film contained in the TFT
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`depicted in FIG. 1. Ex. 1003 at ¶ 65. And, as shown in FIG. 3, pixel electrode 4
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`(the transparent film) has a larger width than semiconductor thin film 13 (the oxide
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`se
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