Trials@uspto.gov
`571-272-7822
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`Paper No. 77
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`MICROSOFT CORPORATION,
`Petitioner,
`
`v.
`
`FG SRC LLC,
`Patent Owner.
`____________
`
`Case IPR2018-01599 (Patent 6,076,152)
` Case IPR2018-01600 (Patent 6,247,110 B1)
`____________
`
`Record of Oral Hearing
`Held: February 3, 2020
`____________
`
`
`
`
`Before KALYAN K. DESHPANDE, JUSTIN T. ARBES, and
`CHRISTA P. ZADO, Administrative Patent Judges.
`
`
`
`
`
`
`
`
`
`
`
`571-272-7822
`
`
`
`
`Paper No. 77
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`MICROSOFT CORPORATION,
`Petitioner,
`
`v.
`
`FG SRC LLC,
`Patent Owner.
`____________
`
`Case IPR2018-01599 (Patent 6,076,152)
` Case IPR2018-01600 (Patent 6,247,110 B1)
`____________
`
`Record of Oral Hearing
`Held: February 3, 2020
`____________
`
`
`
`
`Before KALYAN K. DESHPANDE, JUSTIN T. ARBES, and
`CHRISTA P. ZADO, Administrative Patent Judges.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`IPR2018-01599 (Patent 6,076,152)
`IPR2018-01600 (Patent 6,247,110 B1)
`
`
`
`APPEARANCES:
`
`ON BEHALF OF THE PETITIONER:
`
`
`JOSEPH MICALLEF, ESQ.
`SCOTT BORDER, ESQ.
`Sidley Austin, LLP
`1501 K Street, N.W.
`Washington, D.C. 20005
`
`
`
`ON BEHALF OF THE PATENT OWNER:
`
`
`ALFONSO G. CHAN, ESQ.
`DONALD PUCKETT, ESQ.
`Shore Chan DePumpo, LLP
`Bank of America Plaza
`901 Main Street
`Suite 3300
`Dallas, TX 75202
`
`
`
`
`
`The above-entitled matter came on for hearing on Monday, February
`3, 2020, commencing at 12:01 p.m., at the U.S. Patent and Trademark
`Office, 600 Dulany Street, Alexandria, Virginia.
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`IPR2018-01599 (Patent 6,076,152)
`IPR2018-01600 (Patent 6,247,110 B1)
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`
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`P R O C E E D I N G S
`- - - - -
`JUDGE ARBES: The first hearing we will have today is IPR2018-
`01599 and 1600 involving Patents 6,076,152 and 6,247,110. Can counsel
`please state your names for the record?
`MR. MICALLEF: Good afternoon, Your Honors. Joe Micallef from
`Sidley Austin for the Petitioner Microsoft Corporation. With me at counsel
`table are my partner, Scott Border and behind him our associate, Ethan Plail.
`Also in the room is my partner, Rich Cederoth, and my client, David
`Killough, in-house counsel for the Microsoft Corporation.
`JUDGE ARBES: Thank you.
`MR. CHAN: Good afternoon, Your Honors. My name is Alfonso
`Chan and I'm from Shore Chan along with my co-counsel, Don Puckett and
`Rajkumar Vinnakota, represent the Patent Owner. Along with me here is the
`inventor, Mr. Huppenthal, (indiscernible) principal and owner of the
`company, as well as my partner Ari Rafilson and co-counsel, Sean Hsu.
`JUDGE ARBES: Thank you. Per the Trial Hearing Order in these
`cases, each party will have 90 minutes for this first hearing today of time to
`present arguments. The order of presentation in each hearing is that first
`Petitioner will present its case regarding the challenged claims and may
`argue its Motion to Exclude. Petitioner may reserve time for rebuttal in each
`case but not more than 30 minutes. Patent Owner will then respond to
`Petitioner's presentation and may argue its own Motion to Exclude. Patent
`Owner may reserve time for surrebuttal but not more than 15 minutes.
`Petitioner may then use any remaining time to respond to Patent Owner and
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`finally Patent Owner may use any remaining time for a brief surrebuttal
`responding to Petitioner.
`A few matters before we begin. One, to ensure that the transcript is
`clear and because we have one judge participating remotely, I would ask you
`to only please speak at the podium and try to refer to your demonstratives by
`slide number. Also in the two proceedings today, we received the list of
`Petitioner's objections to certain demonstrative exhibits filed by Patent
`Owner. We're not going to preclude Patent Owner from using any of its
`demonstrative exhibits today, I remind the parties though that demonstrative
`exhibits are merely visual aids to assist presentations at the hearing. They're
`not briefs and they're not evidence.
` That said, we'll note two points that should hopefully give the parties
`a bit of guidance for today. First, some of the source citations at the bottom
`of Patent Owner's slides appear to be incorrect, as Petitioner pointed out in
`its objections. For example, Patent Owner's slide 194 includes an excerpt
`from Exhibit 2151, page 39. The slide says that that was cited in the
`response at page 18 but it does not appear to be cited there. Also for some
`of the slides, for example slides 36 to 108, 110, and 311, the source cite is to
`a lengthy range of pages rather than a pin cite, which makes it difficult for
`the Board to determine whether the information was previously cited in the
`record. I would just ask if Patent Owner refers to any of those slides during
`its presentation today, it would be helpful if you could identify the correct
`page from the response or surreply.
`MR. PUCKETT: Yes, thank you, Your Honor. To make sure that I
`have those correctly, slides 194, 306 through 308 and 311, I didn't get the
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`last part of the last slide.
`JUDGE ARBES: The last one that I mentioned was 36 to 108, 110,
`and 311. I believe all have the same cite.
`MR. PUCKETT: Thank you.
`JUDGE ARBES: Lastly, if either party believes that the other party is
`presenting improper argument, for instance a new argument that was not
`made in the party's briefs, we would ask you to please raise that during your
`own presentation rather than interrupting the other side. Any questions
`before we begin?
`MR. MICALLEF: No, Your Honor.
`MR. PUCKETT: No, Your Honor.
`JUDGE ARBES: Okay. Counsel for Petitioner, you may proceed.
`Would you like to reserve time for rebuttal?
`MR. MICALLEF: Your Honor, my colleague, Scott Border, is going
`to make the argument and we'd like to reserve 30 minutes.
`MR. BORDER: Your Honor, is it okay if we pass up demonstratives?
`JUDGE ARBES: Yes.
`MR. BORDER: Okay. Good morning, Your Honors. May it please
`the Board. Let's go ahead and to go slide 2, please. Your Honors, there's a
`number of grounds at issue in this proceeding. This slide is simply -- repeats
`the slide or sort of the Institution Decision identifying each of those grounds.
`I'll note that Halverson is our primary reference for each of our grounds and
`that we have anticipation based on Halverson and also a single reference
`obviousness. We also have a number of combinations that we'll discuss
`shortly.
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` If you can go to slide 3. Again, this is just to point out that the same
`grounds are at issue in the 1600 proceeding. The claims are virtually
`identical. I don't think the parties dispute that there's any patentable
`difference between the two, at least in this proceeding. As with respect to
`these primary reference, I'll also note that Patent Owner surrendered claims
`1 through 7 in their Patent Owner response.
`Can we go to slide 5, please. Real quick, this is just a road map of
`what I plan to discuss today. Real briefly I'll talk about the 152 and 110
`patents brief overview. I'll talk about the prior art and then I'll get into the
`patentability issues and try to focus on dispute issues between the parties.
`Slide 6, please.
`JUDGE ZADO: Actually counsel, before you continue maybe we can
`stop the clock for a moment. I don't want this to eat into your argument time
`but for both parties there was a housekeeping issue that I wanted us to
`address and that is that our understanding is that Patent Owner in the Patent
`Owner response has said that they surrendered claims 1 through 7 but they
`haven't filed a statutory disclaimer to disclaim those and so we were just
`wanting to establish what exactly Patent Owner or the parties believe that
`means to surrender the claims and what impact that has and whether we need
`to address that in the final decision, and the reason I want to address this
`now before you begin your argument is that if you're not going to spend any
`time arguing claims 1 through 7 today we just want to be sure that the parties
`are on the same page as to what's going to happen and they both agree that
`the claims 1 through 7 are no longer part of this case.
`MR. BORDER: Well Your Honor, I know it's not -- at least based on
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`the PTAB rules -- I don't believe it's required to file a statutory disclaimer.
`There's a number of ways that you can request adverse judgement. I think
`this is one way that Patent Owners have done in the past where in the Patent
`Owner response they've simply disclaimed or surrendered claims and I think
`the effect is that those claims are no longer contested, that patentability is no
`longer contested in the proceeding. Patent Owner may have a different
`view.
`
`MR. PUCKETT: The Patent Owner doesn't have a different view and
`I don't think this is a substantive issue. I appreciate Your Honor raising the
`issue. We're happy to file that certificate acknowledging the surrender
`formally. We felt like it was appropriate to wait until there was a final
`written decision but we have no objection to that being incorporated in the
`final written decision and we'll file a certificate. If anyone thinks it should
`be filed now we're happy to file it now, but we're in full agreement that
`claims 1 through 7 are not a part of this case because they have been
`surrendered by Patent Owner.
`JUDGE ARBES: I'm sorry, counsel. Just to clarify, what is the
`certificate you're discussing?
`MR. PUCKETT: So I'm going to refer to the patent prosecution
`counsel. There's some regulations, something that needs to be filed when
`Patent Owner surrenders claims.
`JUDGE ARBES: You're referring to a statutory disclaimer?
`MR. PUCKETT: I think that maybe there's something that's called a
`little different than that and here I'm limited in terms of my patent
`prosecution practice but I know that there's a document that needs to be
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`filed, we're happy to file it. We were just sort of waiting on for this case to
`be resolved and a final written decision to enter and sort of effectuate that,
`but if it needs to be in earlier we're happy to do it. If the issue is whether or
`not there needs to be any argument on 1 through 7 today, we don't have any
`disagreement that there's no reason to have an argument because we have
`surrendered those claims formally. Does that answer the questions?
`JUDGE ZADO: Yes. For me for now I don't know if at the end of
`this hearing or maybe tomorrow at some point we might follow up and
`formalize what needs to be filed to cancel those claims because I think right
`now what we're thinking is to have that done before we issue the final
`written decision. So just to be clear that we wouldn't have to address it in
`the final written decision but we don't have to resolve that right now, but I
`just wanted to be sure that the parties agreed that the claims are out of the
`case and wouldn't be addressing it during their argument before the
`argument actually started. We just wanted to be sure that that was
`everyone's understanding.
`MR. PUCKETT: Thank you. Patent Owner agrees.
`JUDGE ZADO: Okay, thank you.
`MR. BORDER: Thank you, Your Honors. Okay. Real quick, back
`to the 152 and the 110 patents. These were filed in December -- sorry, the
`152 was filed in December of 1997, the 110 is the continuation of that
`patent. I don't think there's any dispute here that 1997 is the priority date,
`the December date that we're focusing on. Let's go to slide 6. Two quick
`points about the patents at issue. First I am going to largely just address the
`152 patent. The citations are slightly off because of some introductory
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`material in the 110, generally when I cite to the patent it would be 1.2 and I
`just simply wanted to point out a couple of things.
`Figure 1 is what the 152 patent describes as a conventional
`architecture including multiple processors. Figure 3 is a description of what
`the 152 calls a memory bank. It's the only description in the patent or the
`only figure in the patent directed to the elements in the memory bank and it
`includes a MAP assembly which we'll discuss later on, a data and address
`bus and a bank controlled logic among other things.
`Let's go to slide 7. This is just for the Board's comfort that the issues
`that we're talking today sort of track both of these patents and there is slight
`differences that I've highlighted. There are no arguments directed to those
`differences in this proceeding.
`Let's go to slide 9, please. Now I'm going to talk very briefly about
`the prior art. Again, the primary reference is Halverson and we have a
`number of secondary references that we'll discuss.
`Slide 10, please. This is some excerpts from Halverson. It's a 1994
`thesis by Dr. Richard Halverson. He describes it as a software system and
`related hardware architecture. He set out to build what he called a functional
`memory computer which is within the class of custom computing machines.
`He did so by connecting FPGAs and parallel conventional memory. These
`are a couple of figures from the patent. For the reference that you might
`recognize figure 2.15, which is on page 46 of Halverson and is cited in our
`petition on page 24, is the functional memory computer. It doesn't have
`every element of the FMC but you can see the FPGAs sitting parallel, the
`minimal processor and then a system bus and we use this figure throughout
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`our petition to highlight a couple of different mappings that we have and I'll
`discuss those in a moment. To the right is an example of one of the
`applications that are described in Halverson and highlighted here in red. A
`couple of the unique addresses that are associated with the various FPGAs.
`Can we go to slide 11, please. Now Halverson is 102(b) prior art and
`it was written in 1994. It was -- shortly thereafter it was placed into the
`shelves of the University of Hawaii. We solicited testimony from Dr.
`Halverson. What he told us was that he went to check, you know, that it was
`on the shelves, that he found it and was indexed by subject, author and title.
` We also submitted a declaration from Dr. Mullins -- actually can you
`go to slide 12 -- we submitted a declaration from Dr. Mullins. He is an
`expert in library and librarian sciences. He did an analysis based on the
`digital records associated with the thesis. His opinion was that it was
`certainly cataloged at least by February, 1996. The Board credited both of
`these experts' testimony. Well, Mr. Halverson, his own personal knowledge
`and Dr. Mullins expertise in librarian services to confirm that this was
`publicly accessible to the interested public more than a year before the filing
`date of the 152 patent.
`Let's go to slide 10, please. I wanted to point out one other thing.
`There are five FPGAs in the functional memory computer described by
`Halverson. There's the four on the right and then the minimal processor
`which we'll discuss in a moment.
`Let's go to slide 14, please. These are the three other prior art
`references, the secondary references that we rely on for various aspects of
`the claims. These are all 102(e) prior art, excuse me not 102(e) prior art but
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`they're all prior art. There's no dispute on the public availability of any of
`these references. We'll discuss very briefly what they disclose shortly.
`Slide 15, please. Now we're going to get into the patentability issues.
`I'm going to focus on the issues that are actually in dispute. Slide 16. This
`term plurality of data processors appears in claim 11 of the 152 and 110
`patents. This is a term that both the parties have construction for. The
`Board, looking at the intrinsic evidence to the right, found that this means a
`processor for operating on user data in accordance with program instructions
`or steps. We believe that construction is consistent with the construction
`advanced by Petitioner.
`If we can go to slide 17. In response, the Patent Owner agreed with
`some aspects of the Board's interpretation but sought to add the language
`had been read by the processor from memory which the processor executes
`on successive cycles of the processor block. We don't think there's any
`support in the intrinsic record for that additional limitation and certainly as
`we pointed out in the reply on page 13, DirectStream cites to none.
`Next slide please, slide 18. In the petition we demonstrated that
`Halverson does disclose a plurality of data processors. We did this in
`multiple ways. We showed, for example, that the minimal processor
`functioned as a data processor and we showed that it satisfies the elements of
`the claim or the Board's construction through its application of the moot
`words and we'll discuss that in a moment. Halverson also discloses a system
`processor. It's the i8031 processor. This is also on the functional memory
`computer. It's used to initialize and control the FMC. We also --
`JUDGE ZADO: Counsel, I do have one question about construction
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`here. It's not what a processor means but if we look at the claim language it
`says a plurality of data processors for executing at least one application
`program and I'm specifically referring to the 110 patent claim 11 and so
`when the claim says that there are a plurality of data processors for
`executing at least one application program does Petitioner understand that to
`mean that this one program that's being executed has to be executed by all
`the processors, that somehow there's something parallel happening so all
`these processors are all executed in one program that's the same program or
`is there some other reading you have of this?
`MR. BORDER: Well Your Honor, certainly the claims say nothing
`about executing in parallel. I think that's a very specific limitation that
`Patent Owner has argued is present in the claims but there's certainly no
`support in the specification for that additional element. We did show in our
`petition, and this is on page 43, that the system processor does participate in
`the execution of the program, for example, it controls, initializes the FMC.
`We also described how the connected IBM PC, its microprocessor would
`certainly participate in for example the launching of the application
`programs and with respect to the image processing application would be
`used to display the results and, you know, I also note that we also have an
`obviousness combination based on this express language. But I suppose to
`answer your question, Your Honor, no, we don't believe parallel processing
`or parallel execution of the application is required by the claims and there's
`certainly nothing in the intrinsic record to suggest that's the case.
`JUDGE ZADO: So even if there's no requirement that the program be
`executed in parallel, would you agree that there is a requirement though that
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`a plurality of data processors do have to participate in executing the same
`one application?
`MR. BORDER: Well we certainly agree that the claim language says
`that the plurality of data processors execute -- plurality of data processors for
`executing at least one application program. So, and what we endeavor to do
`in our petition and in our expert declaration to show not only how that
`satisfied literally by Halverson again its description of initializing and
`controlling the various programs that relied on. There was the Bubble Sort,
`there was the image processing application, Shortest Path and we
`demonstrated how the system processor would, for example, participate in
`various aspects of executing that program. In our combination with the IBM
`PC again we demonstrated how the IBM PC would participate in that
`process and again just to refer you, I believe this is page 42 through 45 of
`our petition. I don't have the slides in front of me to show you.
`JUDGE ZADO: So, I apologize, I'm not trying to beat a dead horse,
`I'm just trying to be sure that I've clarified and understand Petitioner's
`position. So your position is that for example there is an application
`program in Halverson in which more than one processor participates in
`executing it?
`MR. BORDER: That's correct, Your Honor.
`JUDGE ZADO: Okay.
`MR. BORDER: For example, the minimal processor executes the
`image processing application and Halverson describes how the system
`processor participates in that execution and again, we also have a number of
`obviousness combinations including the Parkin reference which discusses
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`splitting application tasks among local processors. That's one of our several
`grounds that we advanced.
`Let's go to the next slide, slide 19 please. And again the evidentiary
`support for our positions were counted on Dr. Trimberger who has expertise
`in these types of systems and incorporating reconfigurable processing
`elements.
`Can we go to slide 21. Actually back up to slide 20. I put this slide in
`here simply to say that there is no dispute between the parties that the
`FPGAs in Halverson's system satisfy the claimed memory algorithm
`processor and this is an oft cited case by the Board that basically explains
`that if it's not in controversy, that it need not be construed.
`Let's talk about memory banks. Slide 21 please. Petitioner's
`interpretation of this term was a group of devices connected together for use
`as a memory for a data processor and that was based on testimony from our
`expert, Dr. Halverson, and that was looking primarily to the figure described
`in the 152 patent and its corresponding description. We note that this
`construction, although not identical, was consistent with the construction
`that Petitioner advanced in the District Court which I've shown here at the
`bottom right, that's Exhibit 2041 which is the joint claim chart that the
`parties submitted. If we can go to slide 22.
`JUDGE ARBES: I'm sorry counsel. That was Petitioner's proposed
`construction?
`MR. BORDER: I'm sorry, back up please. That was the Patent
`Owner's proposed claim construction and that was a physical model that is
`part of the memory subsystem having a range of memory addresses assigned
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`to it.
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`JUDGE ARBES: Do you disagree with that construction?
`MR. BORDER: I don't think we have an opinion on that construction,
`Your Honor. I think it is somewhat consistent with the interpretation we
`proposed. I don't think -- and I think they've walked away from that
`construction so we haven't attempted to address that specific construction. I
`do think it is consistent though with Petitioner's interpretation.
`Slide 22 please. In response to the Institution Decision in our petition,
`and this is Patent Owner's proposal after institution, they've proposed the
`term memory bank to be a collection of similar memory cell array devices
`with the collection of memory cell arrays comprising the memory bank
`sharing electrical and physical connections such that on any memory cycle
`or any data within any array cell is reader in 1) all the array cells in the bank
`are accessible for memory transactions through electrical activation and
`other prerequisites to memory access and also separate memory array cells
`within the bank are each capable of being accessed by various system
`processors in parallel with the other cell arrays on the same memory cycle.
`The only citation to this proposed construction is to Exhibit 2148 and
`paragraph 236, that's to their expert Dr. Guccione. As we pointed out in our
`reply, there is no basis in the intrinsic record for this construction and in fact
`it's also inconsistent with the expert's understanding which his understanding
`of that term is consistent with what Petitioner has advanced. He said that the
`term, at least as he understood it, was a group of interconnected memory
`devices that are accessible by a processor or other similar devices.
`We asked Dr. Guccione whether that construction was correct and he
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`IPR2018-01599 (Patent 6,076,152)
`IPR2018-01600 (Patent 6,247,110 B1)
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`certainly said he would agree with that definition so their own expert, Dr.
`Guccione, who had the opinion that a memory bank was this long series of
`requirements tended to agree with the interpretation that was actually
`consistent with what Petitioner advanced and, again, there's no support in the
`intrinsic record for any of Patent Owner's constructions.
`JUDGE ARBES: Counsel, do you disagree with Patent Owner's
`argument that this is a term of art, that this would be well understood by
`persons of ordinary skill in the art? Certainly the term is referenced multiple
`times in the documentation that Patent Owner submitted.
`MR. BORDER: Well certainly it was referenced multiple times. I do
`agree with that. I know at the time in the late 90s memory bank was a term
`that was not always used consistently. I think that at the time there was
`discussions of (indiscernible) and banks and so I think what we needed to do
`was look at the intrinsic evidence which the patent itself to understand what
`exactly they mean by memory bank, and that's precisely what we did. We
`identified the figure and the related description. I think a person of skill
`looking at the specification at the time would understand precisely what the
`inventor of the 152 was describing.
`JUDGE ARBES: And how do we deal with the situation where some
`documentation arguably might support a broader view of the term and other
`documentation might support a narrower view? How do we reconcile that?
`MR. BORDER: Well, Your Honor, I think if you're looking at
`evidence that is intrinsic to the 152 patent and the manner which is
`described, I think then that certainly would support what the intrinsic record
`has disclosed. If you look at intrinsic record and it's inconsistent or in this
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`IPR2018-01599 (Patent 6,076,152)
`IPR2018-01600 (Patent 6,247,110 B1)
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`case, substantially narrower, I think the way the law is that that's improper.
`To look at the intrinsic evidence that's certainly inconsistent with what the
`intrinsic record describes.
`Can we go to slide 23. The reason this is relevant, the description of
`memory bank, is because this is the only argument that Patent Owner offers
`with respect to that term. They say that to the extent their definition is used
`then we don't show memory algorithm processor sitting in memory bank.
`We pointed out in our reply at page 26 that argument's certainly not relevant
`because their construction of memory bank is legally erroneous and
`unsupported by the intrinsic record.
`Let's go to slide 25, please. Next term I want to address is
`individually memory addressable. The Board construed this term to mean
`that a particular individual map may be accessed through use of a memory
`address and this was in the Institution Decision at page 16. I note that this
`construction was consistent with what the Patent Owner advocated in
`District Court which they simply said an address of a particular location in
`memory.
`Can we go to slide 26. Again, in its response Patent Owner sought to
`add additional limitations to this claim to narrow it. They said that it's a
`memory unit that has a memory address that distinguishes it from all other
`memory units of the same type. They also add the phrase independently of
`all other memory units of the same type and, again, they cite to paragraph
`240 of their expert's declaration. This testimony here we've included to
`show that again, there's no citations to the intrinsic record, no citations to the
`prior art. This is ipsy dipsy analysis. I mean they should be rejected for that
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`IPR2018-01599 (Patent 6,076,152)
`IPR2018-01600 (Patent 6,247,110 B1)
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`reason and as we pointed out in our reply, again there's no reference to the
`intrinsic record. This is not a proper claim construction.
`JUDGE ARBES: Counsel, why is that not the plain and ordinary
`meaning of a term like individually memory addressable, that the address
`distinguishes it from other memory units? Why is that not the plain and
`ordinary meaning of that language?
`MR. BORDER: Well, I think distinguishing it -- I think Your Honors
`were correct in the Institution Decision when you suggested that simply
`swapping individually for the word separately for example, was not
`necessary. If we can go back to slide 25, and we (indiscernible) that, Your
`Honor. The term individual is well known and so the Board's construction
`that an individual map may be accessed through the use of a memory
`address is proper. I don't see anything in that claim phrase that suggests that
`an address may be distinguishable from other addresses. I also don't know
`that it's relevant because we certainly show that Halverson does have
`individually and unique addresses for its maps.
` If you can go to slide 30 please -- sorry, slide 28 please. This is one
`of two slides where we showed, or this is from Dr. Trimberger relying on
`Halverson's description of unique compiler allocated addresses. He showed
`how an individual map may be accessed through a specific memory address
`and I note that Patent Owner doesn't dispute this evidence. They continue to
`rely on figures describing the background of functional memory computers
`to dispute that Halverson discloses individually memory addressable. They
`never take on this argument. Neither Dr. Trimberger's testimony nor, on
`slide 28, or the petition's explanation on pages 50 and 51 that demonstrated
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`IPR2018-01599 (Patent 6,076,152)
`IPR2018-01600 (Patent 6,247,110 B1)
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`Halverson included unique compiler allocated addresses.
`Let's go to slide 30, please. Now the final disputed claim term relates
`to the means coupling limitation. I included it on this slide just to show the
`position we advanced in the petition. But to get to the issues that are
`actually in dispute, let's move to slide 31 please. In the District Court the
`Patent Owner initially took the position that the phrase was not covered by
`Section 112 6. They then took the alternative approach that if it is covered
`by Section 112 6, that the disclosed fortifying structure is -- and this is
`paraphrasing -- all the figures in every line of the text describing those
`figures in the specification. So what we did was we looked at the
`specification and we attempted to figure out what the possible corresponding
`structure could be based on Patent Owner's position.
`JUDGE ZADO: So counsel, I do have a question about your
`construction. I'm looking at figure 3 of the 152 patent.
`MR. BORDER: Okay.
`JUDGE ZADO: And actually I'm looking at the 110 patent but I
`believe th
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