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`Systematic Low Temperature Bonding And Its Application To The
`Hydrogen Ion Cut Process And Three-Dimensional Structures
`
`By
`
`YANG LI
`
`Dissertation
`
`Submitted in partial satisfaction of the requirements for the degree of
`
`Doctor of Philosophy
`
`in
`
`Electrical Engineering
`
`in the
`
`OFFICE OF GRADUATE STUDIES
`
`of the
`
`UNIVERSITY OF CALIFORNIA
`
`Davis
`
`Approved:
`
`_____________
`
`Committee in Charge
`
`1999
`
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`UMI Number: 9940109
`
`UMI Microform 9940109
`Copyright 1999, by UMI Company. All rights reserved.
`
`This microform edition is protected against unauthorized
`copying under Title 17, United States Code.
`
`UMI
`
`300 North Zeeb Road
`Ann Arbor, MI 48103
`
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`Abstract
`
`A systematic low temperature process is demonstrated in this work. This process
`
`is improved from the earlier wafer bonding technology. It can be reproduced consistently
`
`therefore it can be implemented in the modem semiconductor industry to produce three-
`
`dimensional structures. A brief review of the revolution of modem semiconductor
`
`device, especially metal-oxide-semiconductor (MOS) device,
`
`is given.
`
`Three-
`
`dimensional electronic devices are considered the next generation in the IC industry. Low
`
`temperature bonding technology is a necessary approach to produce this multi-layer,
`
`multi-function electronic device. To stack the electronic devices, as well as vertical
`
`integration of different other microstructures, such as UI-V based photo-electro devices,
`
`microwave devices and Micro-Electro-Mechanical-Structure (MEMS), into one single
`
`silicon based IC chip, to achieve so-called system-on-chip structure, is critical for the
`
`further development of the ultra-large-scale-integration (ULSI) technology. Some
`
`necessary approaches, such as systematic low temperature wafer bonding, reversible
`
`bonding, layer splitting and thin film transferring, copper to copper low temperature
`
`direct bonding, etc. are demonstrated, in order to make it possible for the vertical
`
`integration. Low temperature direct bonding together with reversible bonding, are the
`
`key steps to stack different pre-fabricated active device layer into one single chip. Ion-
`
`cut technology, also referred as Smart-cut9 technology, demonstrated a excellent way to
`
`form thin films that can be further processed in the conventional IC microfabrication
`
`laboratory. The development of this technology, especially using boron and hydrogen
`
`co-implantation instead of using hydrogen implantation only, as of the conventional
`
`Smart-cut9 technology, reduced both the implantation dose and the cutting temperature to
`
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`an acceptable level for the active device layer. Copper (Cu), considered as the key
`
`candidate of the interconnection metal for the next generation of ultra-large-scale-
`
`integrated circuit (ULSI) and giga-scale-integrated circuit (GSI), is receiving more and
`
`more attention. Cu to Cu low temperature direct bonding technology may be critical in
`
`some of the ULSI applications, not only due to its mechanical properties (e.g., high
`
`thermal conductivity for heat dissipation), but also due to the possibility of vertical
`
`integration of the multi-layer microelectronics structures for the next generation of faster
`
`ULSI and GSI devices. An easy way of Cu-Cu low temperature bonding is demonstrated
`
`in this work. Following the summary, some further work also critical for the vertical
`
`integration is discussed, such as the thin film transfer, or so-called low temperature
`
`modular lift-off technology, the possibility of implementing B-H co-implantation layer
`
`splitting in partially or fully processed device layers, etc.
`
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`Dedicated to My Parents - Qingchang and Weihe
`
`-iv-
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`Acknowledgment
`
`I wish to express my deepest gratitude to my research advisor, Professor Robert
`
`W. Bower. I greatly appreciate his guidance, instruction, encouragement, patience,
`
`support, understanding and friendship, it has always been, and will, a great pleasure to
`
`work with him. I surely do not remember how many times Professor Bower and I were
`
`working late till midnight running some experiment in the cleanroom, only two of us left
`
`in the whole building. However, I can never forget the experiment we did on December
`
`24, 1997, the one we did not stop until 8:30 in the evening, when everything worked out
`
`so nicely we could not believe with our own eyes. I guess it was the holly God watching
`
`over us and grant us such excellent results.
`
`I want to express my special thanks to Dr. Michael Nastasi, my supervisor at Los
`
`Alamos National Laboratory, who, together with Professor Bower, supported my
`
`research work in the last eight months of my graduate studies. I want to thank for his
`
`patience, understanding, guidance and friendship. Working with Dr. Nastasi, as well as
`
`Kevin Walter, Tobias Hoechbauer, Kent Scarborough, Joe Tesmer, Calib Evans, Mark
`
`Hollander, Carl Magriore, Xiao-Ming He, Doek-Hyung Lee, Serge Fayeulle, Zoran
`
`Falkenstein, Neil Baker and many others at Los Alamos National Laboratory, is forever a
`
`valuable experience.
`
`I also extend great appreciation to Professor Olav Solgaard in the Department of
`
`Electrical and Computer Engineering, who served as the chairman on my committee in
`
`the qualifying examination. Professor Subuuh Risbud in the Department of Chemical
`
`Engineering and Material Science and Professor Vojin Oklobdzija in the Department of
`
`-V -
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`Electrical and Computer Engineering are also acknowledged, for their help and kindness
`
`in serving on my qualifying exam as well as their valuable suggestions, comments,
`
`discussions and advice.
`
`I am especially indebted to Mr. Angus McFadden, first with the Implant Center
`
`and then switched to nTEK Inc., for his tireless help on providing the implant wafers.
`
`I would like to express thanks to all the students in Professor Bower's research
`
`group at different times while I am staying at UC Davis - Victor Watt, Winnie Chan,
`
`Linh Hong, Frank Y.-J. Chin, Jennifer Lee, Louis LeBoeuf, Wade Xiong, Jason Wu,
`
`Jimmy Kuei, Bryan Frane and Ray Verda, their presence, friendship and assistance have
`
`created the working environment exciting and rewarding.
`
`I want to thank many other fellow graduate students at UC Davis, Tao Pi,
`
`Xiaodong Wang, Kris Vossough, Bonnie Gray, Carlos Gonzales, Dave Pedersen, Paul
`
`Hagelin and others, for their friendship, company and valuable discussions.
`
`Finally, I want to acknowledge University of California MICRO program,
`
`Material Science and Technology Division-8 at Los Alamos National Laboratory,
`
`Hughes Aircraft Inc., Santa Barbara Research Center, Fairchiled Semiconductor
`
`Corporation, for their cooperation, equipment, facilities and financial support.
`
`-vi-
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`CONTENTS
`
`CHARTER 1
`
`Introduction
`
`1.1 VLSI Technology in the Past 25 Years
`
`1.2 Three-dimensional Microelectronics
`
`1.3 Vertical Integration Multi-layer Microstructure
`
`References
`
`CHARTER 2
`
`Low Temperature Direct Bonding
`
`2.1 Brief History of Wafer Bonding
`
`2.2 Aligned Wafer Bonding
`
`2.3 Mechanical Considerations of Wafer Bonding
`
`2.4 RCA Clean
`
`2.5 Optimization of Plasma Activation Process
`
`2.6 Plasma Treatment and Surface Activation Energy
`
`1
`
`8
`
`2.7 Three-step Systematic Low Temperature Wafer Bonding Process
`
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`References
`
`CHARTER 3
`
`Reversible Bonding
`
`39
`
`3.1 Importance of the Reworkability in Three-dimensional Integration
`
`3.2 Possible Ways to Reverse the Bond
`
`3.3 Analysis of the Reversible Bonding for Two Typical Cases
`
`References
`
`CHARTER 4
`
`Layer Splitting and Thin Film Transfer
`
`51
`
`4.1 A Brief Review of Smart-cut® Technology
`
`4.2 Hydrogen-Silicon System and Basic Mechanism of Smart-cut®
`
`4.3 Low Temperature and Smoother Thin Film Transference
`
`4.4 Lower Hydrogen Dose and Lower Temperature Layer Splitting
`
`References
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`CHARTER 5
`
`Low Temperature Copper Direct Bonding
`
`82
`
`5.1 Comparison of Possible Interconnect Metal
`
`5.2 Low Temperature Copper to Copper Low Temperature Direct Bonding
`
`5.3 Bond Strength Test
`
`5.4 Specific Contact Resistance Measurement
`
`References
`
`CHARTER 6
`
`Summary and Future Work
`
`6.1.Overall Scheme for the Vertical Integration of Multi-layer Microstructure
`
`6.2.Future Work
`
`References
`
`Appendix
`
`Bonding Classification
`
`97
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`List of Tables
`
`Table 1.1 A few major changes for MOSFET in the past 25 years
`
`7
`
`Table 2.1 Optimized recipes for different plasma activation process in the low
`
`temperature direct bonding
`
`27
`
`Table 2.2 Experimental evidence of the effects for different plasma activation process in
`
`low temperature direct bonding
`
`Table 2.3
`
`Initial bonding results with pressure only
`
`Table 2.4 Bonding samples after pressure and temperature
`
`27
`
`27
`
`28
`
`Table 2.5 Bond types before and after the third (200 °C anneal) step with or without the
`
`intermediate step (second step with both temperature and pressure)
`
`28
`
`Table 4.1 Monte Carlo simulation results for hydrogen implants into silicon by SRIM 6 8
`
`Table 4.2 Implant boron as the catalyst material may greatly reduce both the hydrogen
`
`implantation dose and the splitting temperature.
`
`Table 5.1 Comparison of properties of possible interlayer metals (ref. 3 and 4)
`
`69
`
`88
`
`Table 5.2 Contact resistance measurement for Cu-Cu direct bonding, the contact area is
`
`18 mm2 for this sample
`
`88
`
`Table A.l Bond classification, only type 4 or 5 bonds shown in IR can produce strong
`
`bonding where the bond strength is measured >1,000 ergs/cm2
`
`99
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`-X -
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`List of Figures
`
`Figure 2.1 The experimental setup for aligned wafer bonding (after Bower et al., 1991)29
`
`Figure 2.2 Some mechanical considerations for the wafer bonding - radius of curvature,
`
`waviness and microroughness (after Bower et al., 1995)
`
`30
`
`Figure 2.3 AFM surface measurement shows, for commercial (100) silicon wafer, the
`
`microroughness is much below the mechanical criteria for achieving a
`
`successful wafer bonding
`
`31
`
`Figure 2.4 Cross sectional SEM image of aligned bonded commercial SRAMs (after
`
`Bower et at., 1993)
`
`32
`
`Figure 2.5 Reduction of the surface activation energy (£„) by applying the plasma
`
`treatment to the attempted bonded samples
`
`33
`
`Figure 2.6 Pressure fixture built for applying the pressure in three-step low temperature
`
`direct bonding process
`
`Figure 2.7 Average initial type of bond with pressure only
`
`Figure 2.8 Likelihood of Good Bond with Pressure only
`
`Figure 2.9 Average type of bond after pressure and temperature treatment
`
`34
`
`35
`
`36
`
`37
`
`Figure 2.10 Likelihood of Good Bond after Pressure and Temperature Treatment 38
`
`Figure 3.1 Cross section of wafers or chips stacked in a three-dimension array with an
`
`offset when aligned bonded, so that a force can be applied along the edge 49
`
`Figure 3.2 Rectangular chip of dimensions d by w, with line force Fj applied
`
`Figure 3.3 Circular wafer of diameter D, with angular force Fq applied
`
`49
`
`49
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`-X I-
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`Figure 3.4 Force needed to debond a 100mm circuit bonded sample, from the calibration
`
`measurement of a 2cm x 2cm square bonded sample, where 0.5 lb force is
`
`applied on the side (Note a =20, can change from 0 to 90°, they represent the
`
`total length of the arc at the edge that a force is applied).
`
`Figure 4.1 Smart-cut® technology to produce silicon-on-insulator material
`
`50
`
`70
`
`Figure 4.2 Four possible hydrogen configurations in silicon (1) bond - centered (BC); (2)
`
`antibonding (AB); (3) H2*; (4) silanic
`
`71
`
`Figure 4.3 Blisters at the silicon surfaces after hydrogen ion implantation.(a) 4.5xl016 H*
`
`into (100) Si, 40 KeV, 425 °C, 6 hours; (b) 4.9xl016 lT into (100) Si, 40 KeV,
`
`425 °C, 2 hours; (c) 5.3xl016 H+ into (100) Si, 40 KeV, 425 °C, 25 minutes;
`
`(d) 5.7xl016 IT into (100) Si, 40 KeV, 425 °C, 20 minutes
`
`72-75
`
`Figure 4.4 Proposed basic mechanism of Smart Cut® process
`
`Figure 4.5 Monte Carlo TRIM-95 simulation for H+ implantation into silicon
`
`76
`
`77
`
`Figure 4.6 A 10cm diameter SOI wafer produced with a hydrogen ion cut at 420 °C after
`
`low temperature wet SRD direct bonding
`
`78
`
`Figure 4.7 The surface roughness of smart-cut® layers created with a normal direct bond
`
`after an Atomic Force Microscopic (AFM) picture published in a recent article
`
`(after M. Bruel et al)
`
`79
`
`Figure 4.8 AFM of the surface roughness low temperature bonded hydrogen cut wafer
`
`(vertical scale is 0 - 12.49 nm)
`
`80
`
`Figure 4.9 Process of layer splitting and thin film transfer
`
`81
`
`Figure 5.1 AFM surface roughness measurement Scan range is 1 pm x
`
`1 pm; the
`
`vertical scale is 0 to 11 nm
`
`89
`
`-X ll-
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`Figure 5.2 Specific contact resistance measurement experimental setup
`
`90
`
`Figure 5.3 I-V measurement shows very good linear relation indicates no extra contact
`
`barrier exists for this Cu-Cu direct bond
`
`91
`
`Figure 6.1 Overall process flow for the vertical integration of multi-layer microstructure
`
`Figure A.1 Typel bond
`
`Figure A.2 Type2 bond
`
`Figure A.3 Type3 bond
`
`Figure A.4Type4 bond
`
`Figure A.5 Type5 bond
`
`96
`
`97
`
`97
`
`98
`
`98
`
`99
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`-xiii-
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`CHAPTER 1
`
`Introduction
`
`l.l.VLSI Technology in the Past 25 Years
`
`The electronics industry has being experienced phenomenal growth in the past
`
`few decades. It is now become the largest industry in the world with global sales over
`
`one trillion (1012) dollars! It never has such an impact to the people in their day-to-day
`
`life. Low power, fast speed, high packaging density, high yield and low cost are always
`
`the key driven forces in the evolution of this industry. The most important device for
`
`ultra-large-scale-integration (ULSI) may be the enhancement mode metal-oxide-
`
`semiconductor field-effect transistor (MOSFET). Although reported as early as in the
`
`early 1960's (by Kahng and Atalla [1], Bower and Dill [2], etc.), it could not be fabricated
`
`properly and reliably until the early 1970's. However, since then, lots of changes
`
`happened to this simple device, Table 1.1 just listed a few major ones.
`
`R. W. Bower summarizes one simple relation between the manufacturing
`
`fabrication cost and the device feature size in the early 1990's as following:
`
`Fabrication Cost ac l/(Feature size)2
`
`It is not surprising that the manufacturing fabrication cost is in the range of two billions
`
`nowadays when the device feature size reaches one-quarter micron. One can further
`
`easily predict that the fabrication cost will be in the range of 10-13 billion dollars when
`
`the feature size decreases to 0.1 micron in the very near future.
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`However, the feature size is no longer the pre-dominant parameter for the speed,
`
`performance and packaging density in the ULSI and giga-scale-integration (GSI)
`
`technology. As S. J. Hilenius stated in Modem Semiconductor Device Physics (Wiley-
`
`Interscience, 1998), "... we have seen various technologies become more integrated into
`
`a single chip and more and more functionality incorporated into these 'system on a chip'
`
`architectures. The future of these systems will be in the increased integration of these
`
`different structures with an ever-increasing dependence on the three-dimensional nature
`
`of these devices..." [3].
`
`Should we keep on squeezing the near-saturated devices in two-dimensional as
`
`we did in the past 25 years, or should we move to the three-dimensional scheme for the
`
`next generation of ULSI and GSI? What are the advantages for the three-dimensional
`
`integration? What are the necessary approaches to achieve the vertical integration?
`
`These are the questions to be answered in this work.
`
`1.2.Three-dimensional Microelectronics
`
`The aluminum based two-dimensional networks has been found inadequate in
`
`ULSI and GSI
`
`technology, because of the unacceptable high values of the
`
`interconnection delay (or so-called RC delay) [4, 5]. One can reduce the RC delay either
`
`by reducing C associated with the dielectric or by reducing R, while only the latter will be
`
`considered in this work. According to the simple relationship of R = pL/A, R can be
`
`reduced by reducing the resistivity p and the length L of the interconnection metal or by
`
`increasing the cross-sectional area of the interconnections, with geometry factors also
`
`affecting C.
`
`Increasing the interconnection area has little appeal, since (a) the area
`
`occupied by interconnection lines is already an extremely large fraction of the chip area
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`3
`
`and (b) the fabrication requirements limit the thickness of the metal (in the matter of fact,
`
`however, using other interconnect metal with higher electromigration resistance, such as
`
`copper, to replace aluminum, may be also possible to reduce the cross sectional area A,
`
`this issue wiil be addressed briefly in Chapter 5 of this work). Therefore, a vertical
`
`structure integrating the multi-layer is proposed in this work, the lowering of I in such
`
`schemes is achieved by using vertical interconnections that span shorter horizontal
`
`distances on selected planar levels.
`
`The industrial standard integrated circuits (ICs) are usually two-dimensional.
`
`However, huge gain can be achieved when expand the device into three-dimensional.
`
`Take static random-access-memory (SRAM) as a simple example. Although the device
`
`dimension is kept on shrinking in the last few years, the most significant structural
`
`change is the accomplishment of extensive usage of the thin-film transistors (TFT) to
`
`allow the p-channel load transistor to be put on top of the n-channel transistor to produce
`
`a cell stacked in the third dimension. Dynamic random-access-memory (DRAM), as
`
`another example, the incredible volume increase comes from the expanding the device
`
`properly in the third dimension also, either using a deep-trench capacitor deep under the
`
`MOS transistor or using a crown type of capacitor structure above the MOS transistor.
`
`Besides modifying the processing technology and producing the single device in
`
`three-dimensional
`
`directly,
`
`the post-single-device-fabrication
`
`three-dimensional
`
`packaging is also proposed. Packaging the conventional two-dimensional IC into three-
`
`dimensional microelectronics is always a challenging issue in the semiconductor field.
`
`The gain is huge, e.g., a two-dimensional conventional IC is about 500 pm thick (for
`
`10cm wafer), the active layer of this IC is only about 1 to 2 pm thick. Thus, three­
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`dimensional stacked aligned bonded chips would have a density of 250 to 500 times
`
`denser than conventional chips. Moreover, the conventional IC is also mounted in a
`
`package that increases its thickness to the order of > 2 mm. Thus, ideally speaking, the
`
`density ratio of three-dimensional to two-dimensional chips is as great as 1000 to 1!
`
`Overall, three-dimensional microelectronics devices, comparing to their two-
`
`dimensional counterparts, have faster speed at a given feature size, much higher
`
`packaging density at a given feature size. Therefore, the cost per function is reduced and
`
`the performance is increased. Smaller manufacturing capital cost can then eventually be
`
`accomplished.
`
`1.3.Vertical Integration Multi-layer Microstructures
`
`Silicon based integrated circuit technology has been a major factor for the
`
`semiconductor industry evolution in the past few decades. Some other important
`
`developments are those of micro-electro-mechanical structure (MEMS), III-V based
`
`photonic devices and microwave devices, etc. The integration of these technologies is a
`
`goal whose impact will be far reaching. Unfortunately, different processing lines are
`
`required for fabricating different type of devices. Thus, packaging the processed devices
`
`into one chip turns out to be the main approach for this issue.
`
`Wafer bonding is considered the major approach for stacking different active
`
`device layer into one single chip. A systematic low temperature silicon/Si0 2 wafer
`
`bonding technology is developed in this work [6, 7]. The re-workability of this wafer
`
`bonding technology is also discussed and a reasonable re-work method is proposed and
`
`analyzed [8, 9].
`
`Ion-cut technology for layer splitting and thin film transferring is
`
`developed [10], the basic mechanism of Smart-cut9 is discussed [11]. A brand new
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`boron/hydrogen co-implantation compared with low temperature direct wafer bonding
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`ion-cut technology, allowing a lower implantation dose and more importantly, at much
`
`lower cutting temperature, is developed [12]. Finally, copper metallization is discussed
`
`and a copper to copper low temperature direct bonding process is demonstrated [13].
`
`References
`
`1. D. Kahng and M .M. Atalla, "Silicon-silicon dioxide surface device", in IRE Device
`
`Research Conference, Pittsburgh, 1960.
`
`2. R. W. Bower and H. G. Dill "INSULATED GATE FIELD EFFECT TRANSISTORS
`
`FABRICATED USING THE GATE AS SOURCE-DRAIN MASK", Paper 16.6
`
`International Electron Device Meeting, Washington, D.C., 1966.
`
`3. "Modem Semiconductor Device Physics", Edited by S. M. Sze, published by Wiley-
`
`Interscience, 1998.
`
`4. S. P. Murarka, R. J. Gutmann, A. E. Kaloyeros and W. A. Lanford, “Advanced
`
`multilayer metallization schemes with copper as interconnection metal”, Thin Solid
`
`Films, 236 (1993) 257-266.
`
`5. Ronald J. Gutmann, T. Paul Chow, William N. Gill, Alain E. Kaloyeros, William A.
`
`Lanford
`
`and
`
`Shyam
`
`P. Murarka,
`
`“COPPER METALLIZATION
`
`MANUFACTURING ISSUES FOR FUTURE ICs”, Mat. Res. Sco. Symp. Proc. Vol.
`
`337, 1994.
`
`6 . Y. Albert Li and Robert W. Bower, "Low temperature direct bonding using pressure
`
`and temperature", Proceedings of SPIE, Vol. 3184, June 1997,124-128.
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`R eproduced with perm ission of the copyright owner. Further reproduction prohibited without perm ission.
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`7. Y. Albert Li and Robert W. Bower, "Systematic Low Temperature Silicon Bonding
`
`using Pressure and Temperature", Japanese Journal of Applied Physics, Vol. 37, No.
`
`3,737-741 (March), 1998.
`
`8. Robert, W. Bower and Y. Albert Li, "Reversible low temperature direct bonds for
`
`fabrication of three-dimensional microelectronic structures", Proceedings of SPIE,
`
`Vol. 3184, June 1997,120-123.
`
`9. Robert W. Bower and Y. Albert Li, "Analysis of Rectangular Chip and Circular
`
`Wafer Debonding Applied to Reversible Low Temperature Bonding", to be
`
`published, 1998.
`
`10. Robert W. Bower, Y. Albert Li and Frank Y-J Chin, "The hydrogen ion cut
`
`technology combined with low temperature direct bonding", Proceedings of SPIE,
`
`Vol. 3184, June 1997,2-4.
`
`11. Y. Albert Li and Robert W. Bower, "Surface Conditions and Morphology of
`
`Hydrogen Ion Cut Low Temperature Bonded Thin Film Layers", submitted to Journal
`
`of Applied Physics, August 1998.
`
`12. Robert W. Bower, Louis LeBoeuf, and Y. Albert Li, "Transposed Splitting of Silicon
`
`Implanted With Spatially Offset Distributions of Hydrogen and Boron", IL NUOVO
`
`CIMENTO, Vol. 19, D, N. 12,1871-1879, December 1997.
`
`13. Y. Albert Li Robert W. Bower and Izak Bencuya, "Low Temperature Copper to
`
`copper Direct Bonding", Jpn. J. Appl. Phys. Vol.37(1998) pp.L1068-L1069, Part 2,
`
`No. 9A/B, 15 September 1998.
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`R eproduced with perm ission of the copyright owner. Further reproduction prohibited without perm ission.
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`7
`
`Why
`Speed and Packaging
`Density
`Yield
`Speed and Packaging
`Density
`Money
`
`Wafer Size
`Devices per
`Chip
`Fab Cost
`(in US $)
`Table 1.1. A few major changes for MOSFET in the past 25 years.
`
`Issue
`Feature Size
`
`From
`To
`By
`10 pm < 0.25 pm Hard Work
`
`10 mm > 2 0 0 mm
`25
`> 2 x 10;
`
`106
`
`2x 10*
`
`Growing
`Scaling
`
`Money
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`CHAPTER 2
`
`Low Temperature Direct Bonding
`
`8
`
`2.1 Brief History of Wafer Bonding
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`Wafer bonding, in order to create novel structures, is not a new technology. As
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`early as in 1969, Wallis and Pomerantz first introduced their work on anodic bonding of
`
`glass to metal or silicon to quartz, which is also known as field-assisted bonding [1].
`
`This process is based on electrostatic forces pulling materials together and is applicable
`
`only when at least one of the materials is insulating or covered with an insulator. The
`
`materials brought into mechanical contact are heated to an elevated temperature and an
`
`electric field is applied across the boundary. This method is used extensively in
`
`fabricating sensors and actuators especially for creating a hermetic sealed cavity.
`
`However, this method is limited to the materials, at least one of the wafers must be
`
`insulator as mentioned above. In addition to the material limitations, anodic bonding
`
`requires high voltage (200 - 2000 Volts) which is generally detrimental for use with pre­
`
`fabricated electronics devices.
`
`Gluing is another natural, simple bonding method. Two attempted pairs are
`
`joined together with a thin adhesive “glue” layer, which usually is low temperature
`
`melting glass such as boron glass, BPSG glass, or spin-on-glass, polymer (PMMA, e.g.)
`
`glue, sometimes even low melting point metal for conductive bonding [2-7]. The
`
`intermediate layer gives good adherence between two wafers after an annealing step.
`
`Applications of gluing include an epitaxial film transfer technique for producing single
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`crystal silicon film on an insulating substrate [8]. The drawbacks are that the adhesive
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`may produce a layer of unnecessary material with temperature restrictions that may
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`impose unnecessary limitations on the composite structures.
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`Direct bonding, which does not require any adhesive or electrostatic field, was
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`first performed by two independent groups in the mid 1980’s. Lasky et al. reported the
`
`bonding of silicon dioxide and silicon dioxide to silicon dioxide, and Shimbo et al.
`
`reported the silicon to silicon direct bonding in 1985 and 1986 respectively [9, 10].
`
`Direct bonding usually consists of room temperature bonding of clean and particle free,
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`mirror-polished, flat wafer surface (either hydrophilic or hydrophobic). The initial weak
`
`room temperature bond is followed by an anneal cycle to create a permanent strong bond.
`
`The temperature of the thermal anneal cycle dictates the type of direct bonding. An
`
`anneal cycle above 700°C is usually required for this category of direct bonding, which is
`
`also called fusion bonding, thermal bonding or high temperature direct bonding [11-13].
`
`Plasma activated low temperature direct bonding was first introduced by Bower et
`
`al in the early 1990's [14-17]. Where the attempted samples were first received a plasma
`
`treatment prelude the room temperature initial contact, following a thermal anneal at a
`
`temperature of only 90-300°C. As a well known fact, that silicon has a 0.5-1 percent
`
`solid solubility in aluminum at a temperature of 450-500°C, therefore, during heat
`
`treatment, Si will diffuse into Al, forming Al spikes in the Si. These spikes may destroy
`
`the operation of the transistor. This phenomenon is particularly severe in the LSI scheme
`
`and beyond since the junction is designed shallower and shallower. To bond pre-
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`processed electronics device with metal line already in place, a low temperature process
`
`is required. Since the year of 1993, independent research groups developed different
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`10
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`methods of low temperature wafer bonding, either by sufficiently long time