Trials@uspto.gov
`571-272-7822
`
`
`
` Paper 11
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`
` Entered: April 11, 2019
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`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`INTEL CORPORATION,
`Petitioner,
`
`v.
`
`VLSI TECHNOLOGY LLC,
`Patent Owner.
`____________
`
`Case IPR2019-00034
`Patent 7,675,806 B2
`____________
`
`
`
`Before ROBERT J. WEINSCHENK, MINN CHUNG, and
`KIMBERLY McGRAW, Administrative Patent Judges.
`
`CHUNG, Administrative Patent Judge.
`
`
`DECISION
`Denying Institution of Inter Partes Review
`35 U.S.C. § 314
`
`
`
`
`571-272-7822
`
`
`
` Paper 11
`
`
` Entered: April 11, 2019
`
`
`
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`INTEL CORPORATION,
`Petitioner,
`
`v.
`
`VLSI TECHNOLOGY LLC,
`Patent Owner.
`____________
`
`Case IPR2019-00034
`Patent 7,675,806 B2
`____________
`
`
`
`Before ROBERT J. WEINSCHENK, MINN CHUNG, and
`KIMBERLY McGRAW, Administrative Patent Judges.
`
`CHUNG, Administrative Patent Judge.
`
`
`DECISION
`Denying Institution of Inter Partes Review
`35 U.S.C. § 314
`
`
`
`
`
`IPR2019-00034
`Patent 7,675,806 B2
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`
`I. INTRODUCTION
`Intel Corporation (“Petitioner”) filed a Petition (Paper 3, “Pet.”)
`requesting an inter partes review of claims 11, 12, 13, 15, and 17 (the
`“challenged claims”) of U.S. Patent No. 7,675,806 B2 (Ex. 1201, “the ’806
`patent”). VLSI Technology LLC (“Patent Owner”) filed a Preliminary
`Response (Paper 10, “Prelim. Resp.”).
`By statute, institution of an inter partes review may not be authorized
`unless “the information presented in the petition . . . and any response . . .
`shows that there is a reasonable likelihood that the petitioner would prevail
`with respect to at least 1 of the claims challenged in the petition.” 35 U.S.C.
`§ 314(a). Upon consideration of the Petition and the Preliminary Response,
`we conclude that the information presented does not show there is a
`reasonable likelihood that Petitioner would prevail in establishing the
`unpatentability of any challenged claim of the ’806 patent. Accordingly, we
`do not institute an inter partes review.
`
`II. BACKGROUND
`A. Related Matters
`The parties indicate that the ’806 patent is the subject of the following
`district court litigation: VLSI Technology LLC v. Intel Corporation,
`No. 5:17-cv-05671 (N.D. Cal. Oct. 2, 2017). Pet. 2; Paper 9, 2.
`The ’806 patent is also the subject of petitions for inter partes review
`filed by Petitioner in IPR2018-01034 and IPR2018-01296.1
`
`
`1 The petition in IPR2018-01034 has been dismissed at the request of
`Petitioner. IPR2018-01034, Paper 11 (Decision Granting Petitioner’s
`Unopposed Motion to Dismiss).
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`B. The ’806 Patent
`The ’806 patent describes a low-voltage memory device in an
`integrated circuit. Ex. 1201, [57]. Figure 1 of the ’806 patent is reproduced
`below.
`
`
`Figure 1 is a block diagram of an exemplary system including a memory
`device. Id. at 1:40–41. As shown in Figure 1, integrated circuit 102
`comprises microprocessor core 112, first memory 108, and
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`second memory 110. Id. at 3:9–10. Integrated circuit 102 also includes bus
`interface unit and sleep control unit 114. Id. at 3:10–11.
`As illustrated in Figure 1, integrated circuit 102 is connected to
`external bus 106. Id. at 2:7–8. During operation, integrated circuit 102 can
`communicate with external devices via external bus 106. Id. at 2:15–16. In
`an embodiment, integrated circuit 102 may be incorporated in a multi-core
`device or system such that integrated circuit 102 is accessible to external
`microprocessor cores (not shown) via external bus 106. Id. at 2:16–20.
`As also depicted in Figure 1, bus interface unit and sleep control
`unit 114 of integrated circuit 102 is connected to voltage regulator 104 to
`provide a voltage control signal. Id. at 3:14–17. Voltage regulator 104
`regulates the voltages supplied to integrated circuit 102, which can operate
`in an active mode or low-voltage mode of operation. Id. at 2:21–23.
`According to the ’806 patent, integrated circuit 102 operates with less power
`in the low-voltage mode than in the active mode of operation, albeit with
`reduced functionality. Id. at 2:30–32.
`To enter the low-voltage mode of operation, integrated circuit 102
`instructs voltage regulator 104 to reduce the voltage supplied to integrated
`circuit 102 below the minimum operating voltage for certain portions of
`integrated circuit 102. Id. at 2:56–60. In an embodiment, first memory 108
`has a minimum operating voltage, which is the lowest voltage at which first
`memory 108 can reliably respond to read and write operations. Id. at 3:44–
`47. If the voltage supplied to first memory 108 is below its minimum
`operating voltage, first memory 108 is effectively inaccessible to
`microprocessor core 112 and other devices. Id. at 3:47–50. According to
`the ’806 patent, first memory 108 also has a retention voltage, which is a
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`voltage at which the memory can still retain stored data when the voltage is
`lowered below the minimum operating voltage. Id. at 3:50–56. In other
`words, first memory 108 can retain data stored in the memory when the
`voltage supplied to first memory 108 is below the minimum operating
`voltage but above or at the retention voltage. Id.
`The ’806 patent describes that second memory 110 is a low-voltage
`memory that operates at a lower voltage than first memory 108. Id. at 3:57–
`58. In an embodiment, the minimum operating voltage for second
`memory 110 is lower than the minimum operating voltage for first
`memory 108, but higher than the retention voltage for first memory 108. Id.
`at 3:61–64.
`According to the ’806 patent, in the active mode of operation, the
`voltage supplied to first memory 108 and second memory 110 is sufficiently
`high to allow read and write operations on both memories. Id. at 4:28–31.
`In the low-voltage mode of operation, the voltage supplied to
`first memory 108 is reduced below the first memory’s minimum operating
`voltage, but the voltage supplied to second memory 110 is maintained above
`the minimum operating voltage for the second memory, such that second
`memory 110 remains accessible, although first memory 108 is inaccessible.
`Id. at 4:32–40. Thus, devices connected to external bus 106 can continue to
`access second memory 110 during the low-voltage mode of operation, which
`can reduce the number of times integrated circuit 102 needs to exit the low-
`voltage mode of operation, resulting in reduced power consumption. Id. at
`4:40–45.
`The ’806 patent describes that first memory 108 has a relatively
`high-density memory topology compared to second memory 110 and that
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`microprocessor core 112 can use first memory 108 to store large blocks of
`data. Id. at 3:32–33, 3:41–43. In an embodiment, second memory 110
`mirrors a subset of the data stored in first memory 108. Id. at 5:9–11.
`In another embodiment, second memory 110 stores status data
`associated with first memory 108 (such as status flags or other information)
`to indicate whether data stored in a particular memory location of first
`memory 108 has been changed. Id. at 4:60–64. During the low-voltage
`mode of operation, the data requesting devices can access the status
`information in second memory 110 to determine the status of data stored in
`first memory 108 and perform tasks based on the status information. Id. at
`4:64–5:1. For example, if the status information indicates that the data
`stored at a memory location of first memory 108 has changed, the data
`requesting device can instruct bus interface unit and sleep control unit 114 to
`cause microprocessor core 112 to exit the low-voltage mode of operation.
`Id. at 5:1–6. The requesting device can then access first memory 108 and
`take appropriate action on the changed memory location. Id. at 5:6–8. In an
`alternative embodiment, the requesting device can write data in second
`memory 110 that will replace the data it mirrors in first memory 108 upon
`exiting the low-voltage mode of operation. Id. at 5:9–15.
`
`C. Illustrative Claim
`Of the challenged claims, only claim 11 is independent. Claim 11 is
`illustrative of the challenged claims and is reproduced below.
`11. A device, comprising:
`a first memory located within an integrated circuit, the first
`memory having a first memory cell topology with a first
`minimum operating voltage, the first memory cell
`topology comprising a first arrangement of transistors;
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`a second memory located within the integrated circuit, the
`second memory having a second memory cell topology
`with a second minimum operating voltage, wherein the
`second minimum operating voltage is less than the first
`minimum operating voltage and wherein the second
`memory cell topology comprises a second arrangement of
`transistors, the second arrangement of transistors different
`from the first arrangement of transistors, the second
`memory configured to store status information indicative
`of a status of data stored at the first memory;
`a processing core located at the integrated circuit, the
`processing core operable to:
`access the first memory and the second memory when in a
`first mode of operation, and to access the second
`memory but not the first memory when in a second
`mode of operation;
`access the status information in the second mode of
`operation; and
`enter the first mode of operation in response to the status
`information indicating data corresponding to the data
`stored at the first memory has changed.
`Ex. 1201, 10:31–57.
`
`D. Asserted Prior Art and Grounds of Unpatentability
`Petitioner cites the following references in its challenges to
`patentability.
`
`Reference and Date(s)
`U.S. Patent No. 7,017,054 B2 (filed July 2,
`2002; issued Mar. 21, 2006)
`U.S. Patent No. 5,687,382 (issued Nov. 11,
`1997)
`
`Designation Exhibit No.
`
`Schuckle
`
`Ex. 1203
`
`Kojima
`
`Ex. 1204
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`Reference and Date(s)
`U.S. Patent No. 7,106,620 B2 (filed Feb. 28,
`2005; issued Sept. 12, 2006)
`Chetana N. Keltcher, et al., The AMD Opteron
`Processor for Multiprocessor Servers, IEEE
`COMPUTER SOCIETY 66, April 22, 2003
`Krisztián Flautner, et al., Drowsy Caches:
`Simple Techniques for Reducing Leakage
`Power, ISCA ’02 PROCEEDINGS OF THE 29TH
`ANNUAL INTERNATIONAL SYMPOSIUM ON
`COMPUTER ARCHITECTURE 148, June 12, 2002
`
`Designation Exhibit No.
`
`Chang
`
`Ex. 1205
`
`Keltcher
`
`Ex. 1207
`
`Flautner
`
`Ex. 1208
`
`Petitioner also relies on the Declaration of Bruce Jacob (Ex. 1202,
`“Jacob Declaration” or “Jacob Decl.”).2
`Petitioner asserts the following grounds of unpatentability:
`
`Claims Challenged
`
`Statutory Basis
`
`References
`
`11, 12, 13, 15, and 17
`
`§ 103(a)3
`
`11, 12, 13, 15, and 17
`
`§ 103(a)
`
`Schuckle, Kojima, Chang,
`Keltcher, and Flautner
`Schuckle, Kojima, Chang, and
`Keltcher
`
`
`Pet. 6.
`
`
`2 Additionally, Petitioner has submitted a Declaration from Dr. Sylvia Hall-
`Ellis (Ex. 1221) in support of Petitioner’s contention that Keltcher and
`Flautner qualify as prior art printed publications in this case. Patent Owner
`does not dispute Keltcher and Flautner qualify as prior art at this time.
`3 The Leahy-Smith America Invents Act, Pub. L. No. 112-29, 125 Stat. 284
`(2011) (“AIA”), amended 35 U.S.C. § 103. Because the ’806 patent has an
`effective filing date prior to the effective date of the applicable AIA
`amendments, we refer to the pre-AIA version of § 103.
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`III. ANALYSIS
`A. Level of Ordinary Skill in the Art
`The parties appear to dispute the level of skill in the art at the time of
`the invention of the ’806 patent. The main point of dispute appears to be the
`level of education and work experience a person of ordinary skill in the art
`would have had at the time of the invention—i.e., at least an undergraduate
`degree in electrical engineering (or an equivalent subject), with at least two
`years of post-graduate experience designing cache systems, according to
`Petitioner (Pet. 38 (citing Ex. 1202 ¶¶ 38–39)), as opposed to at least a B.S.
`degree in electrical engineering, computer engineering, or a related field,
`with three years of relevant industry experience, as proposed by Patent
`Owner (Prelim. Resp. 9). Petitioner also asserts that a person of ordinary
`skill in the art with a master’s degree would have had at least one year of
`post-graduate experience. Pet. 38.
`Although the parties’ proposals for the level of skill in the art have
`differences in wording, we do not find the proposals to be materially
`different. For purposes of this Decision, we find no meaningful differences
`between the parties’ respective definitions that would materially alter the
`outcome of this Decision.
`Further, the level of ordinary skill in the art may be reflected by the
`prior art of record. See Okajima v. Bourdeau, 261 F.3d 1350, 1355 (Fed.
`Cir. 2001) (prior art itself can reflect appropriate level of ordinary skill in the
`art). We find the parties’ definitions to be comparable to the level of skill
`reflected in the asserted prior art. Hence, for purposes of this Decision, the
`prior art itself is sufficient to demonstrate the level of ordinary skill in the
`art.
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`B. Claim Construction
`In this proceeding, claim terms in the unexpired ’806 patent are given
`their broadest reasonable construction in light of the specification of the
`patent. See 37 C.F.R. § 42.100(b) (2017).4 Under the broadest reasonable
`interpretation standard, and absent any special definitions, claim terms
`generally are given their ordinary and customary meaning, as would be
`understood by one of ordinary skill in the art, in view of the specification. In
`re Translogic Tech. Inc., 504 F.3d 1249, 1257 (Fed. Cir. 2007).
`Petitioner and Patent Owner propose constructions for only one term,
`namely “second mode of operation” recited in claim 11. Pet. 34–38; Prelim.
`Resp. 10–21. Petitioner asserts that the term “second mode of operation”
`should be construed to mean “when a lower voltage is provided to the first
`and second memory.” Pet. 34. Patent Owner disagrees and argues that the
`term “second mode of operation” should be given its plain and ordinary
`meaning, which is provided in claim 11 itself. Prelim. Resp. 10–12.
`As discussed below, our Decision in this case does not rest on the
`distinctions between these proposed constructions. For purposes of this
`Decision, we determine that no claim term requires express construction.
`See, e.g., Nidec Motor Corp. v. Zhongshan Broad Ocean Motor Co., 868
`F.3d 1013, 1017 (Fed. Cir. 2017) (“[W]e need only construe terms ‘that are
`in controversy, and only to the extent necessary to resolve the controversy.’”
`
`
`4 A recent amendment to this rule does not apply here because the Petition
`was filed before November 13, 2018. See “Changes to the Claim
`Construction Standard for Interpreting Claims in Trial Proceedings Before
`the Patent Trial and Appeal Board,” 83 Fed. Reg. 51,340 (Oct. 11, 2018) (to
`be codified at 37 C.F.R. pt. 42).
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`(quoting Vivid Techs., Inc. v. Am. Sci. & Eng’g, Inc., 200 F.3d 795, 803
`(Fed. Cir. 1999))).
`
`C. Obviousness over Schuckle, Kojima, Chang, Keltcher, and Flautner
`Petitioner contends that claims 11, 12, 13, 15, and 17 are unpatentable
`under 35 U.S.C. § 103(a) as obvious over the combination of Schuckle,
`Kojima, Chang, Keltcher, and Flautner. Pet. 39–75. In support of its
`contentions, Petitioner submits the Declaration of Bruce Jacob (Ex. 1202).
`Id. We have reviewed the parties’ contentions and supporting evidence.
`Based on the record presented, we are not persuaded that Petitioner has
`established a reasonable likelihood of prevailing on this asserted ground as
`to any of these challenged claims, for the reasons explained below.
`
`1. Relevant Principles of Law
`A claim is unpatentable under 35 U.S.C. § 103(a) if the differences
`between the claimed subject matter and the prior art are such that the subject
`matter, as a whole, would have been obvious at the time the invention was
`made to a person having ordinary skill in the art to which the subject matter
`pertains. KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 406 (2007). The
`question of obviousness is resolved on the basis of underlying factual
`determinations, including: (1) the scope and content of the prior art; (2) any
`differences between the claimed subject matter and the prior art; (3) the level
`of skill in the art; and (4) where in evidence, so-called secondary
`considerations.5 Graham v. John Deere Co., 383 U.S. 1, 17–18 (1966). We
`
`
`5 Patent Owner does not present arguments or evidence of such secondary
`considerations in its Preliminary Response. Therefore, secondary
`considerations do not constitute part of our analysis in this Decision.
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`analyze this asserted ground based on obviousness with the principles
`identified above in mind.
`
`2. Overview of Schuckle (Ex. 1203)
`Schuckle describes a method and system for reducing snoop traffic on
`a processor bus by redirecting the snoop traffic to a memory controller.
`Ex. 1203, 2:58–63, Abstract. According to Schuckle, the disclosed method
`can conserve power by allowing the processor to stay in a lower power state.
`Id. at 2:60–64.
`Figure 1 of Schuckle is reproduced below.
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`Figure 1 illustrates a cache based computer system for implementing a
`method to reduce snoop traffic and reduce power consumption. Id. at 4:15–
`17. As shown in Figure 1, the computer system of Schuckle comprises
`processor 110 (also referred to as a CPU), level two (L2) cache memory 115
`coupled to processor 110, and north bridge 140 (also called “memory
`controller”), which is coupled to main system memory 150. Id. at 4:33–46.
`Schuckle describes that a cache is a small, higher speed memory
`which stores the most recently used instructions or data obtained from a
`larger but slower system memory. Id. at 2:22–25. According to Schuckle,
`snooping is an operation performed by processor 110 to monitor memory
`transactions on system bus (PCI bus) 160 as they occur. Id. at 6:41–45,
`6:66–67. Schuckle describes that snooping prevents data in cache 115 from
`being “obsolete” or “dirty” due to the fact that the contents of system
`memory 150 (corresponding to the cache data) have been changed by other
`devices in the system. Id. at 6:46–49, 6:58–60. During a snoop,
`processor 110 compares the memory address of the memory transaction on
`the system bus to an index of the addresses of the (system) memory
`locations of the data stored in cache memory 115. Id. at 6:67–7:2. The
`index list (also called a directory) of the system memory locations of the
`data stored in the cache is called a “cache tag” and is stored in the cache
`memory. Id. at 7:2–3, 10:1–7. In an embodiment, a status bit is included in
`the cache tag to indicate whether cache data has become different from the
`corresponding value in the system memory. Id. at 10:46–47, 10:64–66.
`Schuckle discloses that during a “snoopable” state, such as the
`Normal or C0 state (i.e., when the processor is in the normal operating mode
`actively executing instructions) or the C1 state, processor 110 performs the
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`snoop operations. Id. at 5:52–61, 6:41–67, 9:41–43. When processor 110 is
`in a lower power state (such as Sleep State C2 or Deep Sleep State C3), the
`processor is unable to perform snoop operations and typically ignores snoop
`traffic. Id. at 5:62–6:8, 7:4–6.
`Schuckle discloses that when the processor is in a lower power state,
`the snoop traffic is redirected from the processor to the memory controller so
`that the processor can remain in a lower power state to conserve power. Id.
`at 2:60–64, 7:20–31, 9:46–50, 9:54–57, 10:29–32, Fig. 2. In an
`embodiment, a copy of the cache tag is maintained in the memory controller,
`which performs snoop operations on its copy of the cache tag while the
`processor is in a lower power state. Id. at 3:1–8, 7:23–31, 10:21–25.
`Figure 3A of Schuckle is reproduced below.
`
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`Figure 3A is a flow chart illustrating a method of reducing snoop traffic on a
`processor bus. Id. at 9:63–64.
`As shown in Figure 3A, in step 300, a mirror copy or an exact copy of
`the cache tag in the cache memory is created and maintained in a memory
`within the memory controller. Id. at 9:64–67. In an embodiment, when the
`cache tag is written to the cache memory, the cache tag information is
`copied (or mirrored) to mirror tag 142 included in memory controller 140.
`Id. at 10:4–7. In another embodiment, processor 110 may create the mirror
`copy of the cache tag by writing to mirror tag 142 just before processor 110
`enters a lower power state, e.g., the C2 or C3 state. Id. at 10:7–10.
`In step 320, while the processor is in a lower power state, memory
`controller 140 performs the snoop operations, which are typically performed
`by processor 110 when it is in the Normal state or other snoopable state
`(e.g., the C0 or C1 state). Id. at 10:11–13. As discussed above, the snoop
`operation is redirected from processor 110 to memory controller 140 during
`a lower power state. Id. at 10:29–32. Performing a snoop operation
`involves comparing the memory address of the requested memory operation
`to the addresses stored in mirror tag 142 to find a match. Id. at 10:21–25.
`In step 340, when a matching entry is found in mirror tag 142,
`memory controller 140 determines whether the cache data corresponding to
`the matching address has been modified in the system memory, e.g., by
`using the status bit in mirror tag 142. Id. at 10:42–48. If the cache data
`(also called cache line) is unchanged, processor 110 remains in the lower
`power state, which reduces the number of times the processor is wakened,
`resulting in reduced power consumption. Id. at 10:51–56. If, on the other
`hand, the cache data has become different from the corresponding value in
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`the system memory, processor 110 exits the lower power state to perform
`appropriate actions depending on the data request. Id. at 10:57–65.
`Referencing Figure 3B (not reproduced herein), Schuckle describes in detail
`the actions performed by processor 110 upon exiting the lower power state
`due to a modified cache line. Id. at 11:51–56, Fig. 3B.
`
`3. Discussion
`In what follows below, we first discuss claim 11, which is the only
`independent claim among the claims challenged in this asserted ground of
`obviousness. We then discuss the rest of the challenged claims, i.e.,
`dependent claims 12, 13, 15, and 17.
`
`a. Claim 11
`In its proposed combination of Schuckle, Kojima, Chang, Keltcher,
`and Flautner, Petitioner relies on Schuckle as the primary reference,
`asserting that Schuckle alone or in combination with other cited reference(s)
`teaches or suggests all limitations of claim 11. See Pet. 39–71. For
`example, Petitioner contends that Schuckle’s level two (L2) cache memory
`discloses “a first memory located within an integrated circuit,” as recited in
`claim 11. Id. at 40 (citing Ex. 1203, 4:42–43, 6:67–7:2, Fig. 1). In addition,
`Petitioner asserts that Schuckle’s “mirror tag” memory (i.e., mirror tag 142)
`that stores a mirror copy of the cache tag is the claimed “second memory.”
`Id. at 42 (citing Ex. 1203, 5:3–8, 9:64–67, Fig. 1).
`Importantly, Petitioner maps Schuckle’s “memory controller” (i.e.,
`north bridge or memory controller 140)—not processor 110 of Schuckle—to
`the “processing core” recited in claim 11. Id. at 59–60 (citing Ex. 1203,
`9:46–57, 10:12–14; Ex. 1202 (Jacob Decl.) ¶¶ 165, 167–168). Petitioner
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`also maps the higher power state (i.e., the C0 or C1 state) of Schuckle to “a
`first mode of operation” and the lower power state (i.e., the C2 or C3 state)
`of Schuckle to “a second mode of operation” recited in claim 11. Id. at 61
`(citing Ex. 1203, 12:35–38 (claims 2, 3); Ex. 1202 ¶¶ 186–188), 63–64
`(citing Ex. 1203, 7:4–19, 10:22–25, 10:43–48; Ex. 1202 ¶ 191).
`Claim 11 recites four separate steps performed by “a processing core.”
`Ex. 1201, 10:47–57. These limitations are reproduced below with
`identifying labels used by the parties and with the key terms emphasized in
`italics.
`a processing core located at the integrated circuit, the processing
`core operable to:
`(11[i]) access the first memory and the second memory when
`in a first mode of operation, and (11[j]) to access the
`second memory but not the first memory when in a second
`mode of operation;
`(11[k]) access the status information in the second mode of
`operation; and
`(11[l]) enter the first mode of operation in response to the
`status information indicating data corresponding to the
`data stored at the first memory has changed.
`As discussed above, Petitioner identifies Schuckle’s memory
`controller 140 as the “processing core” recited in claim 11. Pet. 59–
`60. Consistent with this mapping, Petitioner identifies certain
`operations performed by Schuckle’s memory controller 140 as the
`steps performed by the claimed “processing core” recited in
`limitations 11[i], 11[j], and 11[k].
`Addressing limitation 11[i] (reciting [the processing core
`operable to] “access the first memory and the second memory when in
`a first mode of operation”), Petitioner asserts that “[d]uring the higher
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`
`power state, [Schuckle’s] memory controller (the ‘processing core’) is
`operable to access both the L2 cache (the ‘first memory’) and the
`mirror tag (the ‘second memory’).” Id. at 61 (emphasis added).
`Regarding limitation 11[j] (reciting [the processing core operable to]
`“access the second memory but not the first memory when in a second
`mode of operation”), Petitioner asserts that “Schuckle discloses that
`the memory controller (the ‘processing core’) is operable to access the
`second memory but not the first memory during a lower power state
`(C2 or C3).” Id. at 63 (emphasis added). As for limitation 11[k]
`(reciting [the processing core operable to] “access the status
`information in the second mode of operation”), Petitioner asserts that
`“Schuckle teaches that during the low power state (‘second mode of
`operation’), the memory controller accesses the ‘status bit in the cache
`tag’ to ‘determine[] whether the cache line accessed represented a
`modified or unmodified cache line.’” Id. at 68 (emphasis added)
`(citing Ex. 1203, 10:43–48; 11:41–45, Fig. 3B).
`When it comes to limitation 11[l] (reciting “and [the processing core
`operable to] enter the first mode of operation in response to the status
`information indicating data corresponding to the data stored at the first
`memory has changed”), however, Petitioner does not mention Schuckle’s
`memory controller at all. Instead, Petitioner relies on the operations of
`processor 110 (rather than memory controller 140) of Schuckle to teach the
`step recited in limitation 11[l]. Id. at 69–70 (quoting Ex. 1203, 10:58–66
`(“Access to a modified cache line would generally require that
`processor 110 be enabled to exit the lower power state . . . .” (emphasis
`added)), 11:44–53 (“As described earlier, a status bit in the cache tag is set
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`up to indicate whether the cache line has been modified. If it is determined
`the cache line is modified . . . then the program control is transferred to
`step 3404. . . . In step 3404, processor 110 is enabled to exit the low power
`state since a snoop hit has occurred.” (emphasis added))) (citing Ex. 1203,
`Fig. 3B; Ex. 1202 ¶¶ 199–200).
`In the cited paragraphs of his Declaration, Dr. Jacob similarly opines
`that Schuckle’s processor 110 performs the step recited in limitation 11[l].
`Ex. 1202 ¶ 199 (“Schuckle discloses that, while Processor 110 (not the same
`as the claimed ‘processing core’) is in low-power mode, corresponding to
`the claimed second mode of operation, Processor 110 can be brought out of
`low-power mode and back into the claimed first mode of operation, if the
`cache-coherence operation warrants.” (emphases added)), ¶ 200 (“Schuckle
`allows the cache-coherence engine to access the Mirror Tag while the
`Processor 110 is asleep, in the claimed second mode. If the Mirror Tag’s
`address and status bits (including dirty bit) indicate that . . . the data in the
`targeted block has been modified, then the Processor 110 must wake up and
`respond to the coherence message . . . thus bringing the processor back into
`the claimed first mode of operation. Thus, Schuckle satisfies this
`limitation.” (emphases added)).
`Petitioner’s arguments are deficient in several aspects. First, in its
`contention that Schuckle’s processor 110 teaches the step recited in
`limitation 11[l], Petitioner does not show sufficiently how Schuckle teaches
`the claimed “processing core” is operable to perform the recited step of
`limitation 11[l]. As noted above, Petitioner’s declarant, Dr. Jacob,
`acknowledges that processor 110 is not the “processing core” recited in
`claim 11. Ex. 1202 ¶ 199 (“Processor 110 [is] not the same as the claimed
`
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`‘processing core’” (emphases added)). Indeed, Petitioner does not argue
`explicitly that Schuckle’s processor 110 is the claimed “processor core,”
`although Petitioner relies on the operation of Schuckle’s processor 110 to
`teach the step recited in limitation 11[l]. Pet. 69–70. Instead, Petitioner
`leaves ambiguous and unspecified how (i.e., to which recitation of claim 11)
`Petitioner maps Schuckle’s processor 110. See id. Nor does Petitioner
`explain adequately how it is reading claim 11 as to which recited element of
`claim 11 performs the step to “enter the first mode of operation” recited in
`limitation 11[l]. See id. Thus, Petitioner does not demonstrate sufficiently
`that Schuckle teaches that the claimed “processing core” is operable to
`perform the step recited in limitation 11[l].
`Next, to the extent Petitioner implicitly argues Schuckle’s
`processor 110 is “a processing core” recited in claim 11, Petitioner does not
`identify “a processing core” in Schuckle that performs all of the steps recited
`in claim 11. As set forth above, claim 11 recites “a processing core located
`at the integrated circuit” and that “the processing core is operable to”
`perform the four recited steps—i.e., (1) “access the first memory and the
`second memory” in the first mode of operation (limitation 11[i]), (2) “access
`the second memory but not the first memory” in the second mode of
`operation (limitation 11[j]), (3) “access the status information” in the second
`mode (limitation 11[k]), (4) “and enter the first mode of operation” in
`response to the content of the status information (limitation 11[l]). See
`Ex. 1201, 10:47–57. Thus, the plain language of claim 11 requires
`
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`the processing core—i.e., the same processing core—is “operable to” carry
`out all of the steps recited in limitations 11[i], 11[j], 11[k], and 11[l].6
`As discussed above, although Petitioner maps the claimed “processing
`core” to memory controller 140 of Schuckle (Pet. 59) and identifies the
`operations performed by Schuckle’s memory controller as the steps
`performed by the claimed “processing core” recited in limitations 11[i],
`11[j], and 11[k] (id. at 61, 63, 68), Petitioner does not establish that the same
`memory controller of Schuckle performs the step recited in limitation 11[l]
`(id. at 69–70). Instead, Petitioner relies on the operation of Schuckle’s
`processor 110 to teach the step recited in limitation 11[l]. Id. Thus,
`Petitioner does not identify a “processing core” in Schuckle that performs all
`of the steps recited in claim 11, as required by the plain language of the
`claim.
`Lastly, Petitioner’s evidence indicates that Schuckle’s memory
`controller (which Petitioner maps to the claimed “processing core”) does not
`perform the step recited in limitation 11[l]. In paragraph 167 of his
`Declaration, Dr. Jacob acknowledges that Schuckle’s memory controller
`does “not enter” a “low-power mode” (i.e., the claimed “second mode of
`operation”). Ex. 1202 ¶ 167. In the same paragraph, Dr. Jacob explains that
`Schuckle’s memory controller “[s]tays awake,” i.e., remains in a higher
`
`
`6 As discussed below, Petitioner acknowledges that the claim language “an
`integrated circuit” followed by “the
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