FfGEOTEXT
`
`SS
`
`STATE OF CALIFORNIA
`
`)))
`
`COUNTY OF SAN FRANCISCO )
`
`CERTIFICATION
`
`This is to certify that the attached translation is, to the best of my knowledge andbelief, a true
`
`and accurate translation from Japanese into English of the attached Patent Application No.
`
`05-66937, with publication date of March 19, 1993.
`
`
`
`Zach Duncan, Senior Project Manager
`Geotext Translations, Inc.
`
`
`
`A notary public or otherofficer completing this
`certificate verifies only the identity of the individual
`who signed the document to whichthis certificate
`is attached, and notthe truthfulness, accuracy, or
`validity of that document.
`
`State of California, County of San Francisco
`
`Subscribed and sworn to (or affirmed) before me
` on this 40"day of Hip ,20/8_,
`
`by
`Lae A
`vn¢ GA
`
`>
`
`proved to me on thebasis ofsatisfactory evidence
`
`to be the person(s) who appeared before me.
` BRADLEY RHYMER
`Signature:
`\ Commission No.2160632 3
`NOTARY PUBLIC-CALIFORNIA 2
`SAN FRANCISCO COUNTY
`
`My Comm, Expires JULY 22, 2020
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`Page 1 of 40
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`GOOGLE EXHIBIT 1007
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`Page 1 of 40
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`GOOGLE EXHIBIT 1007
`
`

`

`(19) JAPANESE PATENT
`OFFICE (JP)
`
`(12) KOKAI TOKKYO PATENT
`JOURNAL (A)
`
`(11) PATENT APPLICATION PUBLICATION
`
`NO. 05-66937
`
`(43) Publication Date March 19, 1993
`
`(51) Int. Cl.X:
`G06F 9/06
`
` 13/00
`
`Identification Codes:
`440 Q
`351 L
`
`Sequence Nos. for Office
`Use:
`8944-5B
`7368-5B
`
` FI
`
` Technical Disclosure Section
`
`Examination Request: Not filed
`
`No. of Claims: 3 (Total pages in original
`Japanese-language document: 19)
`
`(21) Filing No.:
`
`H04-56215
`
`(22) Filing Date:
`
`February 6, 1992
`
`(31) Prior Number:
`
`H03-40936
`
`(32) Priority Date:
`
`February 12, 1991
`
`(33) Priority Country: Japan (JP)
`
`(71) Applicant(s): 000000295
`Oki Electric Industry, Co., Ltd.
`1-7-12 Toranomon, Minato-ku, Tokyo
`
`(72) Inventor(s): Tadao SHIMIZU,
`Oki Electric Industry, Co., Ltd.
`1-7-12 Toranomon, Minato-ku, Tokyo
`
`(72) Inventor(s): Nobuhiro KUBOTA,
`Oki Electric Industry, Co., Ltd.
`1-7-12 Toranomon, Minato-ku, Tokyo
`
`(72) Inventor(s): Hiroaki MIYAZAWA,
`Oki Electric Industry, Co., Ltd.
`1-7-12 Toranomon, Minato-ku, Tokyo
`
`(74) Agent(s):
`
`Yuko SATO, Attorney
`
`continued on last page
`
`(54) [Title]
`
`Data Processing Device and Process Modification Method Therefor
`
`(57) Abstract
`[Objective] To reduce labor associated with modifying a
`program.
`[Constitution] Data to be modified for the processing
`sequence of a data process is received by a wireless
`communications means 1. Next, the data that was
`received is saved in a saving means 3, and after its
`validity has been assessed, it is stored in a storage means
`2. Consequently, in cases where there are a plurality of
`data processing devices having a program that must be
`modified, the operation can be easily performed even in
`cases where [said devices] are located in a dangerous
`area. In addition, it is possible to perform the operation
`even without needing to disassemble or assemble the data
`processing devices.
`
`
`computation processing
`
`means
`
`wireless communications
`means
`
`storage means
`
`saving means
`
`Embodiment of the data processing
` device of the present invention
`
`Page 2 of 40
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`

`

`
`
`(2)
`
`NO. 05-066937
`
`1
`
`[Claims]
`[Claim 1] A data processing device comprising:
`a storage means that stores a processing sequence for a data
`process;
`a computation processing means that sequentially reads out said
`processing sequence from said storage means and executes [said
`sequence];
`a wireless communication means that receives data for the part of
`said processing sequence that is to be modified; and
`a saving means that saves said modification portion;
`wherein,
`the data that is received by said wireless communications means is
`saved in the saving means, and after its validity has been
`determined, [said data] is stored in said storage means.
`[Claim 2] A data processing device that is furnished with an
`interface section that is connected to an external device, the data
`processing device being characterized in that it comprises of:
`a nonvolatile read/write memory that can only be overwritten at
`certain times and that stores the processing sequence for the data
`process; and
`a transfer means that transfers the data that was input from said
`interface section to said nonvolatile read/write memory.
`[Claim 3] A data process modification method characterized in
`that:
`data for the modification portion in the processing sequence for a
`data process is transmitted to one or more devices by means of
`either individual transmission or broadcast transmission;
`the data for said modification portion is saved by each device on
`the receiving end, and error checking is performed; and
`when there are no errors in the data of said modification portion,
`the processing sequence for said data process is replaced with the
`data in said modification portion.
`[Detailed Description of the Invention]
`[0001]
`[Field-of-use from the standpoint of manufacturing] The present
`invention pertains to a data processing device that stores a program
`in a storage means such as ROM and performs operations, as well
`as to a data process modification method that modifies the contents
`of that program.
`[0002]
`[Prior Art] Until now, in data processing devices that store a
`program in a ROM or other storage means and then perform
`operations, in cases where the program needs to be revised, in
`some cases, the printed circuit board on which the ROM was
`mounted has had to be replaced. Figure 2 is a block diagram of an
`example of a conventional data processing device. The device
`shown in the figure is a control device for a printer, which is a
`kind of data processing device. This device is made up of a CPU
`51, ROM 52, RAM 53, and I/O port 54 and the like. The CPU 51
`is the center that controls the printer. The ROM 52 stores text
`pattern data and programs to be executed when printing. The RAM
`53 is used as a work area for programs and a reception buffer. The
`I/O port 54 is connected to drive mechanisms such as the print
`head 56, space motor (SP), and linefeed motor (LF) 57 and the
`like; it is also connected to switches and lamps on the operation
`panel 58 and an interface section 59 [for interfacing with] an
`external device 60. A bus line 55 is connected to each component,
`and sends and receives addresses and data. The external device 60
`
`2
`is made up of a personal computer or workstation main unit and a
`disk drive mechanism; it is connected to the printer shown in the
`figure via the interface section 59. In addition, in a data processing
`device operating as an online system, programs—that is, load
`modules—were replaced by the scheme shown in Figure 3 (see
`pages 177 - 179 in Unexamined Japanese Patent Application No.
`62-280933).
`[0003] Figure 3 is a block diagram that shows an online system in
`accordance with a conventional load module modification scheme.
`The system that is shown in the figure is composed of a load
`module modification management table 22, a load module library
`24, and a main memory 26 and the like. The load module
`modification management table 22 manages and saves a load
`module identifier "A" that is input from the load module library 24
`and modification information for that load module. The load
`module library 24 may, for example, be composed of a magnetic
`disk device or the like; it stores load modules contained in a data
`processing sequence in the online system.
`[0004] The main memory 26 is made up of a random access
`memory (RAM) or the like; it loads load modules in the load
`module library 24. Load modules that have been loaded into the
`main memory 26 are sequentially read out by a processor (not
`shown in the figure) and executed. In such systems, the contents of
`the load module that is in main memory 26 are modified using
`modification
`information
`in
`the
`load module modification
`management table 22. The load module can then be executed using
`the contents that were modified. In addition, even if the online
`system experiences a failure, by following said load module
`modification management table 22, the modification contents of
`the load module in main memory 26 are safeguarded without loss
`of the modification information.
`[0005]
`Invention] The above
`the
`[Issues To Be Resolved by
`notwithstanding, with
`the
`above described
`conventional
`technology, the following problems arise. Specifically, using a
`conventional data processing device, in cases where there are
`multiple data processing devices whose programs are to be
`modified, one must replace the ROM circuit board for each device.
`In addition, in cases where there are multiple ROM circuit boards,
`one must search out the ROM circuit board that stores the program
`to be modified on each device, pull the located ROM circuit board
`out from its socket, and replace it. Consequently, a great deal of
`work is required for the modification operation. In particular, in
`cases where it is necessary to replace the ROM circuit board in a
`data processing device that is operating in a dangerous location or
`that is operating in a location where a person cannot easily access
`it, that much more labor will be required.
`[0006] In addition, in order to actually replace the ROM circuit
`board, a large number of steps may be required, and if the person
`performing the work is not used to performing such a task, failures
`may easily occur, and operation safety can become an issue. Now,
`printers, which are used in a wide variety of computer systems as
`shown in Figure 2, constitute an example of a kind of data
`processing device. The program that controls the actual printing
`
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`

`
`
`
`
`(3)
`
`NO. 05-066937
`
`3
`in a ROM 52.
`traditionally been stored
`operation has
`Consequently, if something goes wrong with the program or there
`is a need to modify or improve printer usage, one must replace the
`ROM 52. During such replacement operations, one must first open
`the printer cover and possibly even disassemble the machinery.
`Either way, one requires an experienced operator or maintenance
`person for such replacement operations, and considerable time is
`required for the work. In addition, one must also prepare a new
`ROM for the replacement. Further still, in order to reduce the cost
`of the printer, a mask ROM may be used for the ROM 52, and in
`cases where a mask ROM is installed onto the circuit board while
`eliminating the IC socket, then replacing the ROM 52 becomes
`exceedingly difficult.
`[0007] On the other hand, in a load module modification scheme
`for an online system like that shown in Figure 3, the following
`sorts of issues may arise. Specifically, in cases where the load
`module is stored not in RAM but in ROM, this sort of approach
`cannot be used. In addition, in cases where, outside of failure
`times, one starts the system back up after having cut off power to
`the system, then using the modification information that is stored
`in the load module modification management table 22, one must
`insert a patch once again into the load module that is in main
`memory 26. Consequently, if the amount of patching to be done is
`high, the task of modifying the load module will be troublesome,
`time will be required until the system starts back up, and
`throughput will be lowered.
`[0008] The present invention was conceived taking the above
`issues into consideration. As such, it is an object of the present
`invention to provide a data processing device and a process
`modification method that aims to improve the operational safety
`and reduce the amount of labor in program modification work by
`performing program modification via a device interface or through
`remote operations that are performed using wireless or broadcast
`communications.
`[0009]
`[Means for Resolving the Issues Described] The data processing
`device of the present invention comprises: a storage means that
`stores a processing sequence for a data process; a computation
`processing means that sequentially reads out said processing
`sequence from said storage means and executes [said sequence]; a
`wireless communication means that receives data for the part of
`said processing sequence that is to be modified; and a saving
`means that saves said modification portion;
`wherein, the data that is received by said wireless communications
`means is saved in the saving means, and after its validity has been
`assessed, [said data] is stored in said storage means. Another data
`processing device of the present invention constitutes a data
`processing device that is furnished with an interface section that is
`connected to an external device, the data processing device being
`characterized in that it comprises: a nonvolatile read/write memory
`that can only be overwritten at certain times and that stores the
`processing sequence for the data process; and a transfer means that
`transfers the data that was input from said interface section to said
`nonvolatile read/write memory.
`[0010] The data process modification method of the present
`invention is characterized in that: data for the modification portion
`in the processing sequence for a data process is transmitted to one
`or more devices by means of either individual transmission or
`broadcast transmission; the data for said modification portion is
`saved by each device on the receiving end, and error checking is
`
`
`4
`performed; and when there are no errors in the data of said
`modification portion, the processing sequence for said data process
`is replaced with the data in said modification portion.
`[0011]
`[Effects] In the data processing device and process modification
`method therefor of the present invention, data for the modification
`target in a processing sequence of a data process is received by a
`wireless communications means or the like. Next, the data that was
`received is saved by a saving means, and after its validity has been
`determined, it is stored in a storage means. Consequently, in cases
`where there are multiple data processing devices for which a
`program must be modified, it is easy to perform the operation even
`when those devices are in a dangerous location. In addition, it is
`possible to perform the operation without disassembling or
`assembling the data processing device. Further still, in data
`processing devices that are furnished with an interface section that
`is connected to an external device, the processing sequence of the
`data process is stored in a nonvolatile read/write memory. Next,
`the data that has been input from said interface section at a certain
`time is transferred to the nonvolatile read/write memory by means
`of a transfer. As a result, overwriting of control programs for
`printers and the like is easily performed.
`[0012]
`[Embodiments] Below, embodiments of the present invention shall
`be described in detail with reference to the figures. Figure 1 is a
`block diagram of an embodiment of the data processing device of
`the present invention. The device in the figure is made up of a
`wireless communications means 1, storage means 2, saving means
`3, ROM 4, and RAM 5 — these being connected to the bus line of
`a computation processing means 10. The wireless communications
`means 1
`receives data
`that has been
`transmitted using
`electromagnetic waves. Using this wireless communications
`means 1, beyond individual communications involving a single
`recipient, it is also possible to handle broadcast communications
`involving multiple recipients. The storage means 2 is made from
`EEPROM or the like. As is well known, EEPROM is a kind of
`memory that operates as a ROM that cannot normally be
`overwritten, though it can be overridden using electronic means. A
`program that is actually operated by the computation processing
`means 10 is stored in this storage means 2. Patches are attached to
`the program that is stored in this storage means 2.
`[0013] The saving means 3 temporarily saves patch programs that
`have been transmitted via the wireless communications means 1.
`This saving means 3 is made up of a battery backup memory
`(BBM) or the like. The computation processing means 10
`performs error control on patch programs, and in cases where there
`are no errors, it expands the patch into the storage means 2. The
`ROM 4 is a so-called read-only memory; it stores all of the
`programs that are used by the terminal. The program that is stored
`in this ROM 4 is the original program prior to modification. When
`power is turned onto the device, after an initial diagnostic process
`is executed, the program is transferred from the ROM 4 to the
`storage means 2. The RAM 5 is a so-called random access
`memory that can be overwritten. This RAM 5 is used as a work
`area for the computation processing means 10 that executes the
`program.
`[0014] The original program that is stored in ROM 4 is divided
`into a portion that is executed in ROM 4 and a portion that is
`
`
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`

`
`
`
`
`(4)
`
`NO. 05-066937
`
`5
`executed on the storage means 2. The former is referred to as a
`core, while the latter is referred to as firmware. The core performs
`such activities as executing the initial diagnosis performed when
`the power is switched on, transferring firmware to the storage
`means 2, and expanding patches in the storage means 2. The
`firmware is a program executed on the terminal. This firmware can
`be overwritten on the storage means 2. The firmware that is stored
`in ROM 4 is a program that has a version number. This firmware
`is only transferred to the storage means 2 once when the power is
`turned on. When the firmware version is updated, then a patch is
`applied to the storage means 2. At this time, the version number
`record section on the storage means 2 is updated. Subsequently, at
`the same time that the patch is applied to the storage means 2, each
`time the version is being updated, the version number is also
`updated. This flow of control is shown in Figure 3.
`[0015] Figure 4 is a flowchart that shows a processing sequence
`for modifying a program. First, when the power is turned on a
`determination is made as to whether the installed ROM 4 is new
`(step S21). This determination may be made by, for example,
`pressing a certain key on the keyboard while the power is turned
`on. If the ROM 4 is new, then the firmware is transferred to the
`storage means 2 (step S22). If it is not, then because the firmware
`that is stored in the storage means 2 is the latest version, the
`transfer of firmware from ROM 4 is not performed.
`[0016] Patch data that has been received from the wireless
`communications means 1 is temporarily saved in the saving means
`(step S23) without immediately being expanded into the storage
`means 2. When reception of the latest patch data has been
`completed (step S24), control privileges are transferred to the
`ROM 4, and the patch is expanded into the storage means 2 (step
`S25). At this point, the reason that control privileges are
`temporarily transferred to ROM is so as to make the entire region
`of the storage means 2 eligible for patching. Now, thanks to the
`execution of step S36, in cases where the firmware of the storage
`means 2 is transferred to the RAM 5, when the patch is expanded
`into the storage means 2, there is no need to transfer the control
`privileges to the core of the ROM 4. In other words, the patch can
`be expanded into the storage means 2 with the control privileges
`remaining as is in the firmware in RAM 5.
`[0017] Figure 5 is an explanatory diagram of a sequence for
`implementing the data process modification method of the present
`invention. First, the patch transmission device transmits patch data
`to a plurality of data processing devices that are within the reach of
`[its] electromagnetic waves through broadcast transmissions using
`a wireless communications means 1 (T1). Next, after an elapse of
`time (T2) that is needed for each data processing device to expand
`the patch into the storage means 2, a patch transmission device
`sends a patch result read command by means of broadcast
`communications (T3). Each data processing device transmits a
`total hash value that is set in the patch data and a response that
`determines whether the patch terminated normally based on the
`patch version number to the patch transmission device (T4). In
`cases where the patch terminated abnormally, then once again the
`patch operation is repeated only for that data processing device
`(T5).
`[0018] Figure 6 is an explanatory diagram of the transition of
`
`
`
`6
`control privileges. Due to the power being turned on, the data
`processing device passes through each of the following device
`modes. These device modes are an initial diagnostic M1, transfer
`of the firmware in ROM to EEPROM M2, operation M3, patch
`data incoming M4, patch saving to EEPROM M5, and operation
`M6. In each of these device modes, control privileges are
`transitioned between the ROM and the EEPROM. First, in the
`initial diagnosis M1 and the transition of the firmware section in
`ROM to EEPROM M2, control privileges reside in the core on
`ROM. In the initial diagnostic M1, the ROM and RAM are
`checked, and a hash check is performed for the EEPROM. The
`transfer of the firmware section in ROM to EEPROM is executed
`only when there is an instruction to the effect that a new ROM has
`been installed.
`[0019] Next, during operation M3 and patch data incoming M4,
`the control privileges are transitioned from ROM to EEPROM and
`reside in the firmware on EEPROM. In operation M3, operation
`task processing is performed. In this operation M3, if a patch is
`received, then processing advances to patch data incoming M4. As
`a result, processing advances to storing patch in EEPROM M5,
`and control privileges are transitioned from EEPROM to ROM.
`After that, once processing moves to operation M6, control
`privileges are once again transitioned from ROM to EEPROM.
`[0020] Figure 7 is an explanatory diagram of a transfer when the
`power is turned on. The program that is stored in ROM is made up
`of a core 41 and a firmware 42. The core 41 is left on ROM
`without being forwarded. The firmware 42 is the portion that is
`forwarded to the EEPROM, and contains a version number record
`portion 43 for said program. Forwarding of this firmware 42 is
`only performed once. In other words, the version number that is
`forwarded from the ROM constitutes the initial value of the
`version number in EEPROM. When executing a patch, a
`comparison is made between the version number that is set in the
`last patch command shown in Figure 10 prior to execution and the
`version number that is stored in the EEPROM, and the patch is
`stored in the EEPROM only if these version numbers are the same.
`[0021] Figure 8 is an explanatory diagram of a patch command
`scheme. The commands in the figure consist of an identifier CMD,
`command length LNG, flags FLG, patch address ADR, and patch
`data DATA. The identifier CMD is a code for identifying other
`commands and the patch command. Command length LNG shows
`the total number of bytes in said patch command. The flags FLG
`show which portion of the patch command prior to partitioning the
`segmented patch command is located in cases where the patch
`command is segmented into multiple patch commands and then
`transmitted. The patch address ADR is the address of the portion
`where the patch data was entered into the program. The patch data
`DATA is the patch data constituting the revised portion of the
`program.
`[0022] Figure 19 is an explanatory diagram of the contents of the
`flags. The flags shown in the figure are composed of two-bit data.
`"00" indicates that the segmented patch command is one that
`comes from the middle of the patch. "01" indicates that the
`
`
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`NO. 05-066937
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`7
`segmented patch command is the initial command. "10" indicates
`that the segmented patch command is the final command. And
`"11" indicates that it is a single entity, and not a patch command
`that has been segmented.
`[0023] Figure 11 is a flowchart of the processing sequence when
`the power source is turned on again. Just like the commands
`shown in Figure 8, the commands shown in the figure consist in of
`an identifier CMD, command length LNG, flags FLG, a patch
`address ADR, and patch data DATA, but also include data on the
`version number and the hash value, which are not contained in the
`commands of Figure 8. The version number is the version number
`of the EEPROM that is being targeted for the patch. The hash
`value is the total of the check bits from the header of the initial
`patch command to the version number of the final patch command.
`In addition, each of the patch mode numbers like those shown
`below are then set in the saving means 3 to ensure that a
`malfunction will not occur even if the power to device is turned
`back on at any point in time after the patch has been initiated, as
`this content is referenced when the power is turned on.
`[0024] Figure 11 is a flowchart of the processing sequence when
`the power source is turned on again. In other words, for example,
`patch mode "0" indicates that a patch is not underway. Patch mode
`"1" indicates that patch data is incoming, or that [the device] is
`waiting for the final patch data. Finally, patch mode "2" indicates
`that the patch is being stored on the storage means 2. When the
`power is turned on, first a determination is made as to whether a
`new ROM 4 is installed (step S31). When the results of this
`determination indicate that the ROM 4 is not new, then the patch
`mode is determined (step S32). If the power is turned back on
`during patch mode "2,” because the patch data is incomplete, the
`patch data that is stored in the saving means 3 is re-expanded into
`the storage means 2 starting from the beginning (step S33). In the
`case of patch mode "1,” said patch data is rendered invalid (steps
`S34 and S35). In the case of patch mode "0,” because there are no
`issues, processing advances as is to the next step (step S37). On
`the other hand, in cases where a new ROM 4 is installed, then the
`firmware is forwarded to the storage means 2 (step S36), and
`processing advances to the next step (step S37).
`[0025] Figure 12 is a hardware configuration diagram of an online
`system to which the method of the present invention has been
`applied. The system shown in the figures is made up of a host
`computer 11, a computer for communications control use 12, a
`communications cable 13, and terminal devices 16 and 17. The
`host computer 11 processes data that is sent from each of the
`terminal devices 16 and 17 via the communications cable 13 and
`the computer for communications controlled use 12. The computer
`for communications control use 12 controls communications
`between the host computer 11 and each of the terminal devices 16
`and 17.
`[0026] The communications cable 13 connects the computer for
`communications control use 12 and the control sections 63 and 73
`of the terminal devices 16 and 17. The terminal device 16 is made
`
`
`
`8
`up of a CRT 61, keyboard 62, control section 63, and printer 64.
`The terminal device 17 is made up of a CRT 71, keyboard 72,
`control section 73, and printer 74. Here, the method for writing
`patch data—data constituting the modification portion—into the
`program for printer control use in a terminal device 16 or 17 shall
`be described.
`[0027] Figure 13 is a memory configuration diagram of the printer.
`As shown in the figure, the printer memory is made up of a RAM
`81, EEPROM 82, BBM 83, and ROM 84. The RAM 81 is a
`random-access memory, and is the area that transfers registered
`programs from the EEPROM 82 and executes said transferred
`program when the power is turned on. The EEPROM 82 is a
`region that registers programs and saves them. The program for
`printer control use is registered in this EEPROM 82.
`[0028] The BBM 83 is a region that temporarily writes the patch
`data when it is written to the EEPROM 82. This region is used as a
`log region. The ROM 84 sets the initial modes for the control
`sections 63 and 73 when the power is turned on, and stores a
`program for checking the correctness of the RAM 81, EEPROM
`82, BBM 83, and ROM 84. After registering the program in
`EEPROM 82, or after writing unwritten patch data that is in the
`BBM 83 into the EEPROM 82, the program is transferred from
`said EEPROM 82 to the RAM 81, and control privileges for the
`program are transferred to the RAM 81.
`[0029] The operations of the above described system shall be
`described next. Figure 14 is a flowchart that describes the
`operations of an online system to which the method of the present
`invention has been applied. When power to the terminal devices
`16 and 17 is turned on, the initial modes for control sections 63
`and 73 are set, and the correctness of the ROM 84 and RAM 81
`and so forth is checked (steps S41 and S42). If something is not
`correct, then an error display is made on the CRTs 61 and 71 (step
`S43). In order to subsequently transmit a malfunction advisory, the
`information in this error display is saved.
`[0030] Next, the program that is in EEPROM 82 is transferred to
`the RAM 81, and control privileges are transferred to said RAM
`81 (steps S44 and thereafter). Here, in cases where patch data has
`been sent to the terminal devices 16 and 17, said patch data is
`temporarily stored in the BBM 83. For that reason, first, after the
`error information on the CRTs 61 and 71 has been cleared (step
`S44), then the status of the patch data region in the BBM 83 is
`referenced, and a determination is made as to whether the patch
`data has been completely registered in the BBM 83 (step S45). In
`cases where the status of the patch data region is "patch
`unregistered,” then prior to transferring the program to the RAM
`81, the following sorts of patch data error control are performed
`(steps S46 - S49). Specifically, a hash check is performed on the
`patch data (step S46), and if there is no hash error, then patch data
`is written from the BBM 83 to the EEPROM 82 and a comparison
`check is performed (step S48). If there is no comparison error,
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`then the status of the patch data region is set to patch data
`registered (step S50).
`[0031] Next, a hash check is performed on the program that is in
`the EEPROM 82 (steps S51 and S52). If there was no hash error,
`then the patch data is correctly written into the program that is in
`the EEPROM 82. Consequently, at this time, the program is
`transferred from the EEPROM 82 to the RAM 81 (step S53). After
`that, control privileges are transferred to the RAM 81. At this time,
`the printers 64 and 74 are operating based on the program prior to
`insertion of the patch. Operation of the printers 64 and 74 is
`temporarily stopped, but after they are restarted, they can operate
`using the program to which the patch data has been written in. If
`there is a hash error, then error information is set (step S54), and
`the program is transferred from the ROM 84 to the RAM 81 (step
`S55). Control privileges are then transferred to the RAM 81.
`[0032] Figure 15 is a flowchart that describes the operations of an
`online system after the transcription of EEPROM contents. First,
`each task is started up (step S56), and the machinery undergoes an
`initialization process (step S57). If this process concludes
`normally, a ready notification is issued (steps S58 and S59). Then,
`[the device] waits for command input (step S60), and each
`command process is executed upon receipt of a command. On the
`other hand, if the initialization process did not terminate normally,
`then a device malfunction advisory is made (step S61), and [the
`device] awaits for input of a malfunction handling command (step
`S62).
`[0033] Figure 16 is a flowchart that describes the operations of an
`online system following the transcription of ROM contents. First,
`each of the tasks is started up (step S63), and a device malfunction
`advisory is issued (step S64). In other words, a notification is
`made to the effect that a hash error occurred in the EEPROM 82.
`Based on this notification, the program that needs to be registered
`is sent. Each of the terminal devices 16 and 17 awaits the reception
`of that program (step S65), and once the program has been
`received, they perfor