IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`Examiner:
`Group/ Art Unit:
`Atty. Dkt. No:
`
`Unknown
`Unknown
`5888-00507
`
`Unknown
`
`Application No.:
`Filed: Herewith
`Inventor( s):
`Brian J. Campbell
`Vincent R. von Kaenel
`Daniel C. Murray
`Gregory S. Scott
`Sribalan Santhanam
`Title:
`Integrated Circuit with
`Separate Supply Voltage for
`Memory That is Different
`from Logic Circuit Supply
`Voltage
`
`§
`§
`§
`§
`§
`§
`§
`§
`§
`§
`§
`§
`§
`§
`
`PRELIMINARY AMENDMENT
`
`Commissioner for Patents
`P.O. Box 1450
`Alexandria, VA 22313-14 5 0
`
`Dear Sir:
`
`Please enter the following preliminary amendment in the above-captioned case.
`
`Please amend the case as listed below.
`
`Qualcomm, Ex. 1020, Page 1
`
`

`

`IN THE CLAIMS:
`
`Please amend the claims as indicated below.
`
`1-20. (Cancelled)
`
`21. (New) A level shifter configured to level shift an input signal from a first voltage
`
`domain corresponding to a first supply voltage to a second voltage domain corresponding
`
`to a second supply voltage, the level shifter comprising:
`
`a first P-type metal-oxide-semiconductor (PMOS) transistor having a source
`
`coupled to receive the second supply voltage and coupled to receive a
`
`signal on a gate terminal of the first PMOS transistor;
`
`a second PMOS transistor having a drain coupled to a first node, a gate coupled to
`
`receive the input signal, and a source coupled to a drain of the first PMOS
`
`transistor;
`
`a first N-type metal-oxide-semiconductor (NMOS) transistor having a drain
`
`coupled to the first node, a gate coupled to receive the input signal, and a
`
`source coupled to ground; and
`
`a second NMOS transistor coupled in parallel with the first NMOS transistor and
`
`having a gate coupled to an enable signal, wherein, if the enable signal
`
`indicates that the input signal is disabled, the second NMOS transistor
`
`participates in holding an output of the level shifter steady at a
`
`predetermined voltage level.
`
`22. (New) The level shifter as recited in claim 21 further comprising:
`
`a third PMOS transistor having a source coupled to receive the second supply
`
`voltage and a gate coupled to the first node, wherein the second PMOS
`
`2
`
`Qualcomm, Ex. 1020, Page 2
`
`

`

`transistor is configured to charge a second node responsive to a voltage on
`
`the first node; and
`
`a third NMOS transistor having a drain coupled to the second node, a gate
`
`controlled by a logical combination of the enable signal and the input
`
`signal, and a source coupled to ground;
`
`wherein a gate of the first PMOS transistor is coupled to the second node.
`
`23. (New) The level shifter as recited in claim 22 further comprising a fourth PMOS
`
`transistor having a drain coupled to a drain of the first NMOS transistor, a gate coupled to
`
`the gate of the third NMOS transistor, and a source coupled to a drain of the second
`
`PMOS transistor.
`
`24. (New) The level shifter as recited in claim 22 further comprising an output inverter
`
`having an input coupled to the second node, wherein an output of the output inverter is
`
`the output of the level shifter, and wherein the output inverter comprises a series
`
`connection of two NMOS transistors, wherein a gate of a first of the NMOS transistors is
`
`coupled to the input of the output inverter, and wherein a gate of a second of the NMOS
`
`transistors is coupled to the first supply voltage.
`
`25. (New) The level shifter as recited in claim 24 wherein the output inverter further
`
`comprises a series connection of two PMOS transistors, wherein a gate of a first of the
`
`PMOS transistors is coupled to the input of the output inverter, and wherein a gate of a
`
`second of the PMOS transistors is coupled to the first supply voltage, and wherein a
`
`source of the second of the PMOS transistors is coupled to the second supply voltage.
`
`26. (New) A level shifter configured to level shift an input signal from a first voltage
`
`domain corresponding to a first supply voltage to a second voltage domain corresponding
`
`to a second supply voltage, the level shifter comprising:
`
`3
`
`Qualcomm, Ex. 1020, Page 3
`
`

`

`a shift stage coupled to receive the input signal and to shift the input signal to the
`
`second voltage domain, producing a shifted signal; and
`
`an output inverter coupled to receive the shifted signal and drive an output signal
`
`of the left shifter, the output inverter comprising a series connection of
`
`two NMOS transistors, wherein a gate of a first of the NMOS transistors is
`
`coupled to receive the shifted signal, and wherein a gate of a second of the
`
`NMOS transistors is coupled to the first supply voltage.
`
`27. (New) The level shifter as recited in claim 26 wherein the output inverter further
`
`comprises a series connection of two PMOS transistors, wherein a gate of a first of the
`
`PMOS transistors is coupled to receive the shifted signal, and wherein a gate of a second
`
`of the PMOS transistors is coupled to the first supply voltage, and wherein a source of the
`
`second of the PMOS transistors is coupled to the second supply voltage.
`
`28. (New) The level shifter as recited in claim 26 wherein the shift stage comprises:
`
`a first P-type metal-oxide-semiconductor (PMOS) transistor having a source
`
`coupled to receive the second supply voltage and configured to charge a
`
`first node responsive to a signal on a gate terminal of the first PMOS
`
`transistor;
`
`a first N-type metal-oxide-semiconductor (NMOS) transistor having a drain
`
`coupled to the first node, a gate coupled to receive the input signal, and a
`
`source coupled to ground; and
`
`a second NMOS transistor coupled in parallel with the first NMOS transistor and
`
`having a gate coupled to an enable signal, wherein, if the enable signal
`
`indicates that the input signal is disabled, the second NMOS transistor
`
`participates in holding an output of the level shifter steady at a
`
`predetermined voltage level.
`
`4
`
`Qualcomm, Ex. 1020, Page 4
`
`

`

`29. (New) The level shifter as recited in claim 28 wherein the shift stage further
`
`comprises a second PMOS transistor having a drain coupled to a drain of the first NMOS
`
`transistor, a gate coupled to receive the input signal, and a source coupled to a drain of
`
`the first PMOS transistor.
`
`30. (New) The level shifter as recited in claim 28 further comprising:
`
`a second PMOS transistor having a source coupled to receive the second supply
`
`voltage and a gate coupled to the first node, wherein the second PMOS
`
`transistor is configured to charge a second node responsive to a voltage on
`
`the first node; and
`
`a third NMOS transistor having a drain coupled to the second node, a gate
`
`controlled by a logical combination of the enable signal and the input
`
`signal, and a source coupled to ground;
`
`wherein a gate of the first PMOS transistor is coupled to the second node, and
`
`wherein the second node is the shifted signal.
`
`31. (New) The level shifter as recited in claim 30 further comprising a third PMOS
`
`transistor having a drain coupled to a drain of the first NMOS transistor, a gate coupled to
`
`the gate of the third NMOS transistor, and a source coupled to a drain of the second
`
`PMOS transistor.
`
`32. (New) A level shifter configured to level shift an input signal from a first voltage
`
`domain corresponding to a first supply voltage to a second voltage domain corresponding
`
`to a second supply voltage, the level shifter comprising:
`
`a shift stage coupled to receive the input signal and to shift the input signal to the
`
`second voltage domain, producing a shifted signal; and
`
`5
`
`Qualcomm, Ex. 1020, Page 5
`
`

`

`an output inverter coupled to receive the shifted signal and drive an output signal
`
`of the left shifter, the output inverter comprising a series connection of
`
`two PM OS transistors, wherein a gate of a first of the PM OS transistors is
`
`coupled to receive the shifted signal, and wherein a gate of a second of the
`
`PMOS transistors is coupled to the first supply voltage, and wherein a
`
`source of the second of the PMOS transistors is coupled to the second
`
`supply voltage.
`
`33. (New) The level shifter as recited in claim 32 wherein the output inverter further
`
`comprises a series connection of two NMOS transistors, wherein a gate of a first of the
`
`NMOS transistors is coupled to receive the shifted signal, and wherein a gate of a second
`
`of the NMOS transistors is coupled to the first supply voltage.
`
`34. (New) The level shifter as recited in claim 32 wherein the shift stage comprises:
`
`a first P-type metal-oxide-semiconductor (PMOS) transistor having a source
`
`coupled to receive the second supply voltage and configured to charge a
`
`first node responsive to a signal on a gate terminal of the first PMOS
`
`transistor;
`
`a first N-type metal-oxide-semiconductor (NMOS) transistor having a drain
`
`coupled to the first node, a gate coupled to receive the input signal, and a
`
`source coupled to ground; and
`
`a second NMOS transistor coupled in parallel with the first NMOS transistor and
`
`having a gate coupled to an enable signal, wherein, if the enable signal
`
`indicates that the input signal is disabled, the second NMOS transistor
`
`participates in holding an output of the level shifter steady at a
`
`predetermined voltage level.
`
`6
`
`Qualcomm, Ex. 1020, Page 6
`
`

`

`35. (New) The level shifter as recited in claim 34 wherein the shift stage further
`
`comprises a second PMOS transistor having a drain coupled to a drain of the first NMOS
`
`transistor, a gate coupled to receive the input signal, and a source coupled to a drain of
`
`the first PMOS transistor.
`
`36. (New) The level shifter as recited in claim 34 further comprising:
`
`a second PMOS transistor having a source coupled to receive the second supply
`
`voltage and a gate coupled to the first node, wherein the second PMOS
`
`transistor is configured to charge a second node responsive to a voltage on
`
`the first node; and
`
`a third NMOS transistor having a drain coupled to the second node, a gate
`
`controlled by a logical combination of the enable signal and the input
`
`signal, and a source coupled to ground;
`
`wherein a gate of the first PMOS transistor is coupled to the second node, and
`
`wherein the second node is the shifted signal.
`
`37. (New) The level shifter as recited in claim 36 further comprising a third PMOS
`
`transistor having a drain coupled to a drain of the first NMOS transistor, a gate coupled to
`
`the gate of the third NMOS transistor, and a source coupled to a drain of the second
`
`PMOS transistor
`
`7
`
`Qualcomm, Ex. 1020, Page 7
`
`

`

`REMARKS
`
`Claims 1-20 have been cancelled, and claims 21-37 have been added. Claims 21-
`
`3 7 remain pending in the application.
`
`8
`
`Qualcomm, Ex. 1020, Page 8
`
`

`

`CONCLUSION
`
`Applicants submit the application is in condition for allowance, and an early
`
`notice to that effect is requested.
`
`If any fees are due, the Commissioner is authorized to charge said fees to
`
`Meyertons, Hood, Kivlin, Kowert, & Goetzel, P.C. Deposit Account No. 501505/5888-
`
`00500/LJM.
`
`Respectfully submitted,
`
`/Lawrence J. Merkel/
`Lawrence J. Merkel
`Reg. No. 41,191
`AGENT FOR APPLICANT(S)
`
`Meyertons, Hood, Kivlin, Kowert, & Goetzel, P.C.
`P.O. Box 398
`Austin, TX 78767-0398
`Phone: (512) 853-8800
`
`Date: February 20, 2008
`
`9
`
`Qualcomm, Ex. 1020, Page 9
`
`

`

`REMARKS
`
`Claims 1-20 have been cancelled, and claims 21-37 have been added. Claims 21-
`
`3 7 remain pending in the application.
`
`8
`
`Qualcomm, Ex. 1020, Page 10
`
`

`

`CONCLUSION
`
`Applicants submit the application is in condition for allowance, and an early
`
`notice to that effect is requested.
`
`If any fees are due, the Commissioner is authorized to charge said fees to
`
`Meyertons, Hood, Kivlin, Kowert, & Goetzel, P.C. Deposit Account No. 501505/5888-
`
`00500/LJM.
`
`Respectfully submitted,
`
`/Lawrence J. Merkel/
`Lawrence J. Merkel
`Reg. No. 41,191
`AGENT FOR APPLICANT(S)
`
`Meyertons, Hood, Kivlin, Kowert, & Goetzel, P.C.
`P.O. Box 398
`Austin, TX 78767-0398
`Phone: (512) 853-8800
`
`Date: February 20, 2008
`
`9
`
`Qualcomm, Ex. 1020, Page 11
`
`

`

`Electronic Patent Application Fee Transmittal
`
`Application Number:
`
`Filing Date:
`
`Title of Invention:
`
`Integrated Circuit with Separate Supply Voltage for Memory That is
`Different from Logic Circuit Supply Voltage
`
`First Named Inventor/Applicant Name:
`
`Brian J. Campbell
`
`Filer:
`
`Lawrence J. Merkel/Dena Poudrier
`
`Attorney Docket Number:
`
`5888-00507
`
`Filed as Large Entity
`
`Utility
`
`Filing Fees
`
`Description
`
`Fee Code
`
`Quantity
`
`Amount
`
`Sub-Total in
`USO($)
`
`Basic Filing:
`
`Utility application filing
`
`Utility Search Fee
`
`Utility Examination Fee
`
`1011
`
`1111
`
`1311
`
`1
`
`1
`
`1
`
`310
`
`510
`
`210
`
`310
`
`510
`
`210
`
`Pages:
`
`Claims:
`
`Miscellaneous-Fi Ii ng:
`
`Petition:
`
`Patent-Appeals-and-Interference:
`
`Qualcomm, Ex. 1020, Page 12
`
`

`

`Description
`
`Fee Code
`
`Quantity
`
`Amount
`
`Sub-Total in
`USO($)
`
`Post-Al I owance-and-Post-lssu ance:
`
`Extension-of-Time:
`
`Miscellaneous:
`
`Total in USD ($)
`
`1030
`
`Qualcomm, Ex. 1020, Page 13
`
`

`

`Electronic Acknowledgement Receipt
`
`EFSID:
`
`Application Number:
`
`2884207
`
`12034071
`
`International Application Number:
`
`Confirmation Number:
`
`7508
`
`Title of Invention:
`
`Integrated Circuit with Separate Supply Voltage for Memory That is
`Different from Logic Circuit Supply Voltage
`
`First Named Inventor/Applicant Name:
`
`Brian J. Campbell
`
`Customer Number:
`
`35690
`
`Filer:
`
`Lawrence J. Merkel/Dena Poudrier
`
`Filer Authorized By:
`
`Lawrence J. Merkel
`
`Attorney Docket Number:
`
`5888-00507
`
`Receipt Date:
`
`Filing Date:
`
`Time Stamp:
`
`20-FEB-2008
`
`13:55:46
`
`Application Type:
`
`Utility under 35 USC 111 (a)
`
`Payment information:
`
`Submitted with Payment
`
`Payment Type
`
`Payment was successfully received in RAM
`
`RAM confirmation Number
`
`Deposit Account
`
`Authorized User
`
`yes
`
`Deposit Account
`
`$1030
`
`9719
`
`501505
`
`The Director of the USPTO is hereby authorized to charge indicated fees and credit any overpayment as follows:
`
`Charge any Additional Fees required under 37 C.F.R. Section 1.16 (National application filing, search, and examination fees)
`
`Charae anv Additional Fees reauired under 37 C.F.R. Section 1.17 (Patent application and reexamination processina fees)
`
`Qualcomm, Ex. 1020, Page 14
`
`

`

`Charge any Additional Fees required under 37 C.F.R. Section 1.19 (Document supply fees)
`
`Charge any Additional Fees required under 37 C.F.R. Section 1.20 (Post Issuance fees)
`
`Charge any Additional Fees required under 37 C.F.R. Section 1.21 (Miscellaneous fees and charges)
`
`File Listing:
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`Document
`Number
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`Document Description
`
`File Name
`
`Pages
`Multi
`File Size(Bytes)
`/Message Digest Part /.zip (if appl.}
`
`127554
`
`1
`
`Oath or Declaration filed
`
`Declaration-00507.pdf
`
`no
`
`3
`
`8ae21319da5c8f1 7026c3f9984688a00
`e4b813cf
`
`Warnings:
`
`Information:
`
`2
`
`Drawings-only black and white line
`drawings
`
`Drawings-00507.pdf
`
`no
`
`4
`
`59331
`
`45b58843fec1 d9d3b9f5db98628b5017
`d5eb5929
`
`Warnings:
`
`Information:
`
`3
`
`Miscellaneous Incoming Letter
`
`Notice-of-Recordation-00507
`.pdf
`
`229522
`
`fd747ad96eae5990d63a52dbbe703604
`1 ec4d950
`
`no
`
`2
`
`Warnings:
`
`Information:
`
`4
`
`Application-00507.pdf
`
`yes
`
`26
`
`1389834
`
`964d4370a676d7bdc4a0bc4107a6e2a
`95c13f0f7
`
`Multipart Description/PDF files in .zip description
`
`Document Description
`
`Start
`
`End
`
`Sequence Listing
`
`Claims
`
`Abstract
`
`Warnings:
`
`Information:
`
`5
`
`Information Disclosure Statement
`(IDS) Filed
`
`Warnings:
`
`Information:
`
`This is not an USPTO supplied IDS fillable form
`
`20
`
`25
`
`26
`
`1
`
`21
`
`26
`
`36820
`
`I OS 1 -00507. pdf
`
`no
`
`5
`
`c2d024bb4509ee507817143438c5a56
`bf88bdd65
`
`Qualcomm, Ex. 1020, Page 15
`
`

`

`6
`
`Prelim-Amend-00507.pdf
`
`yes
`
`9
`
`82840
`
`Multipart Description/PDF files in .zip description
`
`6492be7159419ab4f97fc7a7b3a71 Oa3
`1db3e629
`
`Document Description
`
`Start
`
`End
`
`Preliminary Amendment
`
`Claims
`
`Applicant Arguments/Remarks Made in an Amendment
`
`Warnings:
`
`Information:
`
`1
`
`7
`
`9
`
`1
`
`2
`
`8
`
`8412
`
`7
`
`Fee Worksheet (PTO-06)
`
`fee-info.pdf
`
`no
`
`2
`
`c373a8ae851f22fba65f4e66702796f86
`1833eb9
`
`Warnings:
`
`Information:
`
`Total Files Size (in bytes):
`
`1934313
`
`This Acknowledgement Receipt evidences receipt on the noted date by the USPTO of the indicated documents,
`characterized by the applicant, and including page counts, where applicable. It serves as evidence of receipt
`similar to a Post Card, as described in MPEP 503.
`
`New Agglications Under 35 U.S.C. 111
`If a new application is being filed and the application includes the necessary components for a filing date (see
`37 CFR 1.53(b)-(d) and MPEP 506), a Filing Receipt (37 CFR 1.54) will be issued in due course and the date
`shown on this Acknowledgement Receipt will establish the filing date of the application.
`
`National Stage of an International Agglication under 35 U.S.C. 371
`If a timely submission to enter the national stage of an international application is compliant with the conditions
`of 35 U.S.C. 371 and other applicable requirements a Form PCT/DO/EO/903 indicating acceptance of the
`application as a national stage submission under 35 U.S.C. 371 will be issued in addition to the Filing Receipt,
`in due course.
`
`New International Agglication Filed with the USPTO as a Receiving Office
`If a new international application is being filed and the international application includes the necessary
`components for an international filing date (see PCT Article 11 and MPEP 1810), a Notification of the
`International Application Number and of the International Filing Date (Form PCT/RO/105) will be issued in due
`course, subject to prescriptions concerning national security, and the date shown on this Acknowledgement
`Receipt will establish the international filing date of the application.
`
`Qualcomm, Ex. 1020, Page 16
`
`

`

`Docket No. 5888-00500
`
`DECLARATION AND POWER OF ATTORNEY
`
`As a below named inventor, I hereby declare that:
`
`My residence, post office address, and citizenship are as stated below next to my name.
`
`I believe the inventor(s) named below to be the original and first inventor(s) of the subject matter which is
`claimed and for which a patent is sought on the invention entitled "INTEGRATED CIRCUIT WITH SEPARATE
`SUPPLY VOLTAGE FOR MEMORY THAT IS DIFFERENT FROM LOGIC CIRCUIT SUPPLY
`VOLTAGE," the specification of which:
`t8J is attached hereto.
`D was filed on _ _ _ _ _ _ _ _ _ as Application Serial No. _ _ _ _ _ _ _ _ _ _
`(if applicable).
`and was amended on
`
`I hereby state that I have reviewed and understand the contents of the above-identified specification,
`including the claims, as amended by any amendment referred to above.
`
`I acknowledge the duty to disclose to the Patent and Trademark Office all information known to me to be
`material to patentability of the subject matter claimed in this application, as "materiality" is defined in 3 7 C.F .R. §
`1.56.
`
`I hereby claim foreign pnonty benefits under 35 U.S.C. § 119(a)-(d) or § 365(b) of any foreign
`application(s) for patent or inventor's certificate listed below, or under§ 365(a) of any PCT international application
`listed below designating least one country other than the United States of America, and have identified below any
`foreign application for patent or inventor's certificate, or of any PCT international application, having a filing date
`before that of the application on which priority is claimed.
`
`Prior Foreign Application No.
`
`Country
`
`Filing Date
`(mm/dd/yy)
`
`Priority
`Claimed
`
`Cert. copy
`Attached
`
`NIA
`
`I hereby claim the benefit under 35 U.S.C. § 119(e) of any United States provisional application(s) listed
`
`below.
`
`Provisional Application No.
`
`NIA
`
`Filing Date
`(1mn/dd/yy)
`
`I hereby claim the benefit under 35 U.S.C. § 120 of any United States application(s) listed below, or under
`§ 365(c) of any PCT international application listed below designating the United States of America, and, insofar as
`the subject matter of each of the claims of this application is not disclosed in the prior United States or PCT
`international application in the manner provided by the first paragraph of35 U.S.C. § 112, I acknowledge the duty to
`disclose all information known to me to be material to the patentability of the subject matter claimed in this
`application, as "materiality" is defined in 37 C.F.R. § 1.56, which became available between the filing date of the
`prior application and the national or PCT international filing date of this application.
`Parent Patent No. (if applicable) or Status
`
`Parent Application No.
`
`Filing Date
`(1mn/dd/yy)
`
`NIA
`
`Pagel of3
`
`Qualcomm, Ex. 1020, Page 17
`
`

`

`I hereby revoke any previous Powers of Attorney and appoint each of
`
`the practitioners at Customer Number 35690, and
`
`Docket No. 5888-00500
`
`Mark K. Brightwell
`Steve J. Curran
`Mark R. DeLuca
`Erik A. Heter
`Jeffrey C. Hood
`B. Noel Kivlin
`Robert C. Kowert
`Lawrence J. Merkel
`Eric B. Meyertons
`David W. Quimby
`Rory D. Rankin
`Mark S. Williams
`Chris Thompson
`Gareth Sampson
`Russell Henrichs
`Liza Philip
`Kay A. Colapret
`Neal E. Persky
`Heather L. Flanagan
`Rajiv Jauhari
`Mario Lewin
`
`Reg. No. 47,446
`Reg. No. 50,664
`Reg. No. 44,649
`Reg. No. 50,652
`Reg. No. 35,198
`Reg. No. 33,929
`Reg. No. 39,255
`Reg. No. 41,191
`Reg. No. 34,876
`Reg. No. 39,338
`Reg. No. 47,884
`Reg. No. 50,658
`Reg. No. 43,188
`Reg. No. 52,191
`Reg. No. 50,354
`Reg. No. 51,352
`Reg. No. 52,759
`Reg. No. 53,452
`Reg. No. 54,101
`Reg. No. 55,850
`Reg. No. 54,268
`
`as attorney or agent, with full power of substitution and revocation, to prosecute the application, to make alterations
`and amendments therein, to transact all business in the Patent and Trademark Office in connection therewith, and to
`receive the Letters Patent.
`
`Please direct all co1mnunications to:
`
`Lawrence J. Merkel
`Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.
`P.O. Box398
`Austin, TX 78767-0398
`Phone: (512) 853-8800
`
`I hereby declare that all statements made herein of my own knowledge are true and that all statements made
`herein on information and belief are believed to be tme; and further that these statements were made with the
`knowledge that willful false statements and the like so made are punishable by fine or imprisomnent, or both, under
`18 U.S.C. § 1001 and that such willful false statements may jeopardize the validity of the application or any patent
`issued thereon.
`
`Inventor's Full Name:
`
`lnvento,'s Signaruce,
`
`::r,,,:;,,z~L_/,t{t_
`
`Brian J. Campbell
`
`Date:
`
`l
`
`L
`
`City and State ( or Foreign Country) ofR~ce:
`
`Sunnyvale, CA
`
`Citizenship:
`
`U.S.A.
`
`Mailing Address:
`
`1163 Corral Ave, Sunnyvale, CA 94086
`(Include number, street name, city, state and zip code)
`
`Page 2 of3
`
`Qualcomm, Ex. 1020, Page 18
`
`

`

`Docket No. 5888-00500
`
`\J \ Y\ C, e.V\ ~ \JO V'\ I,( . Vincent R. von Kaenel
`
`Inventor's Full Name:
`
`Inventor's Signature:
`
`Date: ~/q_z/os
`
`l
`
`I
`
`City and State (or Foreign Country) of Residence:
`
`Palo Alto, CA
`
`Citizenship:
`
`Swiss
`
`Mailing Address:
`
`2320 Bowdoin Street, Palo Alto, CA 94306
`(Include number, street name, city, state and zip code)
`
`Inventor's Full Name:
`
`Inventors Signarw-e: b ._/ C ,M ~
`
`Daniel C. Murray
`
`Date:
`
`6 I Zz I 05-
`
`City and State (or Foreign Country) of Residence: ~ n Hill, CA
`
`Citizenship:
`
`U.S.A.
`
`Mailing Address:
`
`315 Via Largo, Morgan Hill, CA 95037
`(Include number, street name, city, state and zip code)
`
`Inventor's Full Name:
`
`Inventor's Signature:
`
`Gregory S. Scott
`
`Date:
`
`City and State (or Foreign Country) of Residence: ___ S_an_ta_C_l_a_ra_,,_C;_A ___ Citizenship:
`
`U.S.A.
`
`Mailing Address:
`
`474 Hickory Place, Santa Clara, CA 95051
`(Include number, street name, city, state and zip code)
`
`Inventor's Full Name:
`
`Inventor's Signature:
`
`City and State (or Foreign Country) of Residence:
`
`Palo Alto, CA
`
`Citizenship:
`
`India
`
`Mailing Address:
`
`1353 Lincoln Ave. Palo Alto, CA 94301
`(Include number, street name, city, state and zip code)
`
`Page 3 of3
`
`Qualcomm, Ex. 1020, Page 19
`
`

`

`r-------
`------ ------------------- ------
`- - - - - - -1
`ircuit 10
`1 Integrated C
`1
`I
`I
`I
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`~---------------------------------------------J
`
`Logic Circuits
`12
`
`~
`
`~
`
`..
`
`,,...
`
`Memory Circuits
`li
`
`I
`
`Fig. 1
`
`Level
`Shifter 20
`
`..---~--__, WLO .. ,--__.__--~___,
`Word Line WLN
`Memory
`Array 24
`Drivers 22
`
`Addr Inputs
`r-----------------
`: Memory Circuit 14A
`VM
`:
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`1 gclk
`1 En
`
`Clock
`Gater 26
`
`elk
`
`I
`I
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`I
`I
`I
`I
`I
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`Dout:
`I
`I
`I
`I
`I
`I
`I
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`I
`_ __ J
`
`Din
`
`Control
`Signal
`Generator 28
`
`REI
`WE/
`PChg/
`_____ etc. _
`
`~--------------------------
`
`CTL Inputs
`
`Fig. 2
`
`Qualcomm, Ex. 1020, Page 20
`
`

`

`Bit Line Drivers 30
`
`WE
`
`40A
`
`I ---------------------------------------1
`, DinO
`y
`, Memory Array 24
`L
`I
`I
`I
`I
`I
`WL0 1
`I
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`I
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`I
`WLN:
`
`--------------- --,
`Memory Cell 3 2A
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I I
`I
`40B
`:
`_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ J
`1
`
`L . ._ - - -£~ ~ - -~
`
`I
`I
`I
`I
`I
`I
`I
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`I
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`PChg1
`
`Memory Cell 32N
`,---------------
`: Bit Line Precharge 34 :
`I
`I
`I
`I
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`I
`I
`I
`, - - - - - - - ' - - - -~ I
`I
`I
`I
`I
`I
`I
`
`I ______________ __.
`
`VL
`
`r - - - - - - - - - - - - - -
`1
`: Bit Line Hold 36
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
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`I
`I
`I
`I
`I
`I
`
`I ______________ __.
`
`BL
`
`BL
`
`Senseamp 38
`-------------------J
`DoutO
`Fig. 3
`
`RE
`
`Qualcomm, Ex. 1020, Page 21
`
`

`

`: Level Shifter 20a
`I
`:
`
`VM
`
`I
`I
`I
`I
`I
`I
`I
`gclk1
`
`elk e
`
`En
`
`En
`
`50
`
`52
`
`L _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ J
`
`Fig. 4
`
`I
`I
`I
`I
`I
`I
`I
`56
`I
`I
`L _______________________________________ _
`
`Fig. 5
`
`Qualcomm, Ex. 1020, Page 22
`
`

`

`r----------------------------------,
`V M
`Word Line Driver 22A
`
`__ c_lk--=-e _ _ _ _ _ _ _ 9
`
`N3
`
`Al~
`
`A2 ~
`
`elk
`
`WLO
`
`'--60
`
`~----------------------------------
`
`Fig. 6
`
`Start
`
`Logic Circuits Read
`and/or Write Memory
`Circuits
`
`Memory Circuits
`Respond to Reads Using
`VL signals
`
`Memory Circuits Store
`Write Data Supplied
`Using V L signals
`
`70
`
`72
`
`74
`
`End
`
`Fig. 7
`
`Qualcomm, Ex. 1020, Page 23
`
`

`

`UNDER SECRETARY OF COMMERCE FOR INTELLECTUAL P!j!~F'&fV"M'Jll't,!,=====1,~~~=~====
`DIRECTOR OF THE UNITED STATES PATENT AND TRADEMi~'Olc'!"IC~
`
`0
`
`V
`
`• • -
`
`NOVEMBER 09, 2005
`
`LAWRENCE J. MERKEL
`MEYERTONS, HOOD, KIVLIN ET AL.
`P.O. BOX 398
`AUSTIN, TX 78767-0398
`
`PTAS
`
`111111111111 11111111111111111111 11111 1111111111 111111111 llll
`*103040050A*
`
`DEC
`
`5 2005
`
`j
`
`UNITED STATES PATENT AND TRADEMARK.OFFICE
`NOTICE OF R.ECORDATION OF ASSIGNr/JENT"'DC°Cl:}MEI:JT
`
`THE ENCLOSED DOCUMENT HAS BEEN RECORDED BY THE ASSIGNMENT DIVISION OF
`THE U.S. PATENT AND TRADEMARK OFFICE. A COMPLETE MICROFILM COPY IS
`AVAILABLE AT THE ASSIGNMENT SEARCH ROOM ON THE REEL AND FRAME NUMBER
`REFERENCED BELOW.
`
`THE
`PLEASE REVIEW ALL INFORMATION CONTAINED ON THIS NOTICE.
`INFORMATION CONTAINED ON THIS RECORDATION NOTICE REFLECTS THE DATA
`IF YOU SHOULD
`PRESENT IN THE PATENT AND TRADEMARK ASSIGNMENT SYSTEM.
`FIND ANY ERRORS OR HAVE QUESTIONS CONCERNING THIS NOTICE, YOU MAY
`CONTACT THE EMPLOYEE WHOSE NAME APPEARS ON THIS NOTICE AT 571-272-3350.
`PLEASE SEND REQUEST FOR CORRECTION TO: U.S. PATENT AND TRADEMARK OFFICE,
`MAIL STOP: ASSIGNMENT SERVICES DIVISION, P.O. BOX 1450, ALEXANDRIA, VA 22313.
`
`RECORDATION DATE: 07/01/2005
`
`REEL/FRAME: 016756/0742
`NUMBER OF PAGES: 4
`
`BRIEF: ASSIGNMENT OF ASSIGNOR'S INTEREST (SEE DOCUMENT FOR DETAILS).
`
`ASSIGNOR:
`CAMPBELL, BRIAN J.
`
`ASSIGNOR:
`VON KAENEL, VINCENT R.
`
`ASSIGNOR:
`MURRAY, DANIEL C.
`
`ASSIGNOR:
`SCOTT, GREGORY S.
`
`ASSIGNOR:
`SANTHANAM, SRIBALAN
`
`ASSIGNEE:
`P.A. SEMI, INC.
`3965 FREEDOM CIRCLE, FLOOR 8
`SANTA CLARA, CALIFORNIA 95054
`
`DOC DATE: 06/22/2005
`
`DOC DATE: 06/22/2005
`
`DOC DATE: 06/22/2005
`
`DOC DATE: 06/23/2005
`
`DOC DATE: 06/22/2005
`
`P.O. Box 1450, Alexandria, Virginia 22313-1450 • www.uSPTO.Gov
`
`Qualcomm, Ex. 1020, Page 24
`
`

`

`016756/0742 PAGE 2
`
`FILING DATE: 07/01/2005
`SERIAL NUMBER: 11173565
`ISSUE DATE:
`PATENT NUMBER:
`TITLE: INTEGRATED CIRCUIT WITH SEPARATE SUPPLY VOLTAGE FOR MEMORY THAT IS
`DIFFERENT FROM LOGIC CIRCUIT SUPPLY VOLTAGE
`
`LENELL MACKALL, SUPERVISOR
`ASSIGNMENT DIVISION
`OFFICE OF PUBLIC RECORDS
`
`Qualcomm, Ex. 1020, Page 25
`
`

`

`PATENT
`5888-00501
`
`Integrated Circuit with Separate Supply Voltage for Memory
`That is Different from Logic Circuit Supply Voltage
`
`By:
`
`Brian J. Campbell
`Vincent R. von Kaenel
`Daniel C. Murray
`Gregory S. Scott
`Sribalan Santhanam
`
`Qualcomm, Ex. 1020, Page 26
`
`

`

`BACKGROUND
`This application is a divisional of U.S. Application Serial No. 11/173,565, which
`
`was filed on July 1, 2005.
`
`5
`
`Field of the Invention
`
`[0001] This invention is related to the field of integrated circuits including integrated
`
`memories such as static random access memory (SRAM) and, more particularly, to
`
`supplying power to such integrated circuits.
`
`10 Description of the Related Art
`
`[0002] As the number of transistors included on a single integrated circuit "chip" has 10
`
`increased and as the operating frequency of the integrated circuits has increased, the
`
`management of power consumed by an integrated circuit has continued to increase in
`
`importance. If power consumption is not managed, meeting the thermal requirements of
`
`15
`
`the integrated circuit ( e.g. providing components required to adequately cool the
`
`integrated circuit during operation to remain within thermal limits of the integrated
`
`circuit) may be overly costly or even infeasible. Additionally, in some applications such
`
`as battery powered devices, managing power consumption in an integrated circuit may be
`
`key to providing acceptable battery life.
`
`20
`
`[0003] Power consumption m an integrated circuit is related to the supply voltage
`
`provided to the integrated circuit. For example, many digital logic circuits represent a
`
`binary one and a binary zero as the supply voltage and ground voltage, respectively ( or
`
`vice versa). As digital logic evaluates during operation, signals frequently transition fully
`
`25
`
`from one voltage to the other. Thus, the power consumed in an integrated circuit is
`
`dependent on the magnitude of the supply voltage relative to the ground voltage.
`
`Reducing the supply voltage generally leads to reduced power consumption. However,
`
`there are limits to the amount by which the supply voltage may be reduced.
`
`30
`
`[004] One limit to the reduction of supply voltage that is experienced in integrated
`
`circuits that integrate memories (such as SRAM) is related to the robustness of the
`
`1
`
`Qualcomm, Ex. 1020, Page 27
`
`

`

`memmy. As supply voltage decreases below a certain voltage, the ability to reliably read
`and write the memory decreases. The reduced reliability may have several sources. The
`resistances of some devices in the memory ( e.g. the pass gate transistors that couple bit
`lines to memory cells in an SRAM) may change as the supply voltage falls. The changed
`resistance may impact the ability to overdrive the memory cell for a write or to discharge
`the bit line for a read. Additionally, in some designs, the transistors in the memory are
`high threshold voltage (high VT) transistors. That is, the threshold voltage at which the
`••• i.e. actively conduct current) is higher than other
`transistors activate ( or "turn on11
`transistors in the integrated circuit. The threshold voltage of such transistors does not
`scale well with supply voltage. Accordingly, the "trip point" (the point at which a write
`to a memory cell occurs) as a percentage of the supply voltage worsens as the supply
`voltage is decreased. As an example, in one current integrated circuit manufacturing
`process, a supply voltage below about 0.9 volts results in reduced ability to write the
`memory reliably. Similarly, the ability to quickly and/or reliably read the memory
`decreases. Accordingly, the supply voltage at which the robustness of the memory begins
`to be impacted has served as a floor to reducing the supply voltage to an integrated circuit
`that includes memory.
`
`SUMMARY
`
`5
`
`10
`
`15
`
`20
`
`In one embodiment, an integrated circuit comprises at least one logic circuit
`[0005}
`supplied by a first supply voltage and at least one memory circuit coupled to the logic
`circuit and supplied by a second supply voltage. The memory circuit is configmed to be
`read and written responsive to the logic circuit even if the first supply voltage is less than
`the second supply voltage during use.
`
`25 ·
`
`h1 another embodiment, a method com