Paper No. 1
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`__________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`__________________
`
`
`QUALCOMM INC. AND QUALCOMM TECHNOLOGIES,
`INC.,
`
`Petitioners,
`
`v.
`
`APPLE INC.,
`
`Patent Owner.
`
`
`
`U.S. PATENT NO. 7,355,905
`
`TITLE: INTEGRATED CIRCUIT WITH SEPARATE SUPPLY
`VOLTAGE FOR MEMORY THAT IS DIFFERENT FROM
`LOGIC CIRCUIT SUPPLY VOLTAGE
`
`Issue Date: April 8, 2008
`
`
`PETITION FOR INTER PARTES REVIEW
`UNDER 35 U.S.C. § 312
`
`
`
`

`

`TABLE OF CONTENTS
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`Page
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`Introduction ..................................................................................................... 1
`I.
`II. Mandatory Notices .......................................................................................... 3
`A.
`Real Party in Interest (37 C.F.R. § 42.8(b)(1)) .................................... 3
`B.
`Related Matters (37 C.F.R. § 42.8(b)(2)) ............................................. 3
`C.
`Lead and Back-Up Counsel and Service Information (37 C.F.R.
`§ 42.8(b)(3) and (b)(4)) ........................................................................ 4
`Fees (37 C.F.R. § 42.103) .................................................................... 5
`D.
`III. Grounds for Standing Pursuant to (37 C.F.R. § 104(a)) ................................. 5
`IV. Statement of Precise Relief Requested for Each Challenged Claim .............. 5
`A.
`The Claims for Which Review Is Requested (37 C.F.R. §
`42.104(b)(1)) ........................................................................................ 5
`The Specific Statutory Grounds on Which the Challenge is
`Based and Prior Art Relied Upon for Each Ground (37 C.F.R. §
`42.104(b)(2)) ........................................................................................ 6
`Reasons for the Relief Requested Under 37 C.F.R. §§ 42.22(a)(2) and
`42.104(b)(4) .................................................................................................... 7
`A. Overview of the ’905 Patent and its Technology ................................. 7
`B.
`The Prosecution History of the ’905 Patent ....................................... 12
`1.
`The Daga Patent ....................................................................... 13
`2.
`The Claim Amendments to Attempt to Overcome Daga ......... 13
`37 C.F.R. § 42.104(b)(3): Claim Construction ................................. 16
`1.
`A Person of Ordinary Skill in the Art ...................................... 16
`2.
`Construction of Claim Terms ................................................... 16
`(a)
`“integrated circuit” ........................................................ 17
`(b)
`“received on a first / second input to the integrated
`circuit” ........................................................................... 18
`“during use” ................................................................... 18
`(c)
`D. Overview of the Prior Art ................................................................... 19
`
`V.
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`B.
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`C.
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`TABLE OF CONTENTS
`(continued)
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`Page
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`E.
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`Clark ......................................................................................... 19
`1.
`Kawata ..................................................................................... 24
`2.
`37 C.F.R. § 42.104(b)(4): How the Construed Claims are
`Unpatentable ....................................................................................... 26
`37 C.F.R. § 42.104(b)(5): Supporting Evidence ............................... 26
`F.
`VI. Claims 1–4 and 13 of the ’905 Patent are Unpatentable .............................. 27
`A. Ground 1: Clark Anticipates Claims 1–4 and 13 .............................. 27
`1.
`Independent Claim 1 ................................................................ 27
`(a)
`Preamble – “An integrated circuit comprising:” ........... 27
`(b) Element 1[a] – “at least one logic circuit supplied
`by a first supply voltage received on a first input to
`the integrated circuit; and” ............................................ 28
`(c) Element 1[b] – “at least one memory circuit
`coupled to the logic circuit and supplied by a
`second supply voltage received on a second input
`to the integrated circuit, and” ........................................ 30
`(d) Element 1[c] – “wherein the memory circuit is
`configured to be read and written responsive to the
`logic circuit even if the first supply voltage is less
`than the second supply voltage during use, and” .......... 32
`(e) Element 1[d] – “wherein the memory circuit
`comprises at least one memory array, and” ................... 35
`Element 1[e] – “wherein the memory array
`comprises a plurality of memory cells that are
`continuously supplied by the second supply
`voltage during use.” ....................................................... 35
`Dependent Claim 2 .................................................................. 37
`Dependent Claim 3 ................................................................. 38
`Dependent Claim 4 .................................................................. 40
`Independent Claim 13 .............................................................. 42
`
`(f)
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`2.
`3.
`4.
`5.
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`TABLE OF CONTENTS
`(continued)
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`Page
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`Preamble – “A method comprising” .............................. 42
`(a)
`(b) Element 13[a] – “a logic circuit reading a memory
`cell, the logic circuit supplied by a first supply
`voltage received on a first input to the integrated
`circuit; and” ................................................................... 42
`(c) Element 13[b] – “the memory cell responding to
`the read using signals that are referenced to the
`first supply voltage, wherein the memory cell is
`supplied with a second supply voltage that is
`greater than the first supply voltage during use;
`and” ................................................................................ 43
`(d) Element 13[c] – “wherein the second supply
`voltage is received on a second input to the
`integrated circuit, and” .................................................. 45
`(e) Element 13[d] – “wherein the memory circuit
`comprises at least one memory array, and” ................... 45
`Element 13[e] – “wherein the memory array
`comprises a plurality of memory cells that are
`continuously supplied by the second supply
`voltage during use.” ....................................................... 45
`B. Ground 2: Claims 1–4 are Anticipated by Kawata ............................ 46
`1.
`Independent Claim 1 ................................................................ 46
`(a)
`Preamble – “An integrated circuit comprising” ............ 46
`(b) Element 1[a] – “at least one logic circuit supplied
`by a first supply voltage received on a first input to
`the integrated circuit; and” ............................................ 47
`(c) Element 1[b] – “at least one memory circuit
`coupled to the logic circuit and supplied by a
`second supply voltage received on a second input
`to the integrated circuit, and” ........................................ 49
`
`(f)
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`-iii-
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`TABLE OF CONTENTS
`(continued)
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`Page
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`(d) Element 1[c] – “wherein the memory circuit is
`configured to be read and written responsive to the
`logic circuit even if the first supply voltage is less
`than the second supply voltage during use, and” .......... 51
`(e) Element 1[d] – “wherein the memory circuit
`comprises at least one memory array, and” ................... 52
`Element 1[e] – “wherein the memory array
`comprises a plurality of memory cells that are
`continuously supplied by the second supply
`voltage during use.” ....................................................... 53
`Dependent Claim 2 .................................................................. 54
`2.
`Dependent Claim 3 .................................................................. 54
`3.
`Dependent Claim 4 .................................................................. 56
`4.
`VII. Conclusion .................................................................................................... 57
`
`(f)
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`-iv-
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`I.
`
`Introduction
`Pursuant to 35 U.S.C. § 312 and 37 C.F.R. § 42.100 et seq., Qualcomm Inc.
`
`and Qualcomm Technologies, Inc. (collectively, “Petitioners” or “Qualcomm”)
`
`request inter partes review (“IPR”) of claims 1–4 and 13 (the “Challenged Claims”)
`
`of U.S. Patent No. 7,355,905 (“the ’905 Patent,” Ex. 1001), which issued on April 8,
`
`2008, and is assigned to Apple, Inc. (“Apple”).
`
`The ’905 Patent is directed to an integrated circuit having at least one logic
`
`circuit and one memory circuit, each of which is supplied by respective first and
`
`second supply voltages. Ex. 1001, [57], 2:3–6, 3:22–36, Fig. 1 (disclosing “Logic
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`Circuits 12” supplied by supply voltage VL and “Memory Circuits 14” supplied by
`
`supply voltage VM). According to the ’905 Patent, if a single voltage is used to
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`supply both the logic and memory circuits, then this common supply voltage can be
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`reduced only so far due to memory reliability issues. Id., 1:15–67. “As supply
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`voltage decreases below a certain voltage, the ability to reliably read and write the
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`memory decreases.” Id., 1:43–44; see also id., 1:64–67. The ’905 Patent
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`supposedly improved upon the prior art by using separate supply voltages for the
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`logic and memory circuits. This allows the logic and memory supply voltages to be
`
`different, including allowing the logic supply voltage to be lower than the memory
`
`supply voltage in order to further conserve power. Id., 2:49–58, 3:22–36, Fig. 1; see
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`also Ex. 1002 ¶¶ 31–34 (Clark Decl.).
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`There is nothing, however, patentable about using different supply voltages to
`
`supply a logic circuit and a memory circuit. This feature is disclosed by each of
`
`U.S. Patent No. 6,650,589 to Clark (“Clark”) (Ex. 1003) and U.S. Patent No.
`
`6,920,071 to Kawata et al. (“Kawata”) (Ex. 1004), neither of which were of record
`
`during prosecution of the ’905 Patent. Nor is there anything patentable about the
`
`other aspects of the Challenged Claims, which recite conventional memory and logic
`
`circuitry known to a person of ordinary skill in the art (“POSITA”) as of the
`
`effective filing date of the ’905 Patent. As explained herein, and as supported by the
`
`Declaration of Lawrence T. Clark, Ph.D. (the inventor of the prior art Clark patent)
`
`(Ex. 1002), the Challenged Claims are unpatentable in view of both Clark and
`
`Kawata. See §§ IV, V, VI, infra.
`
`Notably, during prosecution of the ’905 Patent, the Examiner found that using
`
`a first supply voltage to supply a logic circuit and a second supply voltage to supply
`
`a memory circuit was met by U.S. Patent No. 7,120,061 to Daga (“Daga”) (Ex.
`
`1005). See § V.B, infra (discussing the prosecution history). In response, the
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`applicants amended the patent claims to recite that the first supply voltage (i.e., the
`
`logic supply voltage VL) and the second supply voltage (i.e., the memory supply
`
`voltage VM) are received on respective first and second inputs to the claimed
`
`integrated circuit. Id. Based on these amendments regarding where the supply
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`voltages are input to, and received by, the integrated circuit, the Examiner allowed
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`the claims. Id. However, these additional features are met by each of Clark and
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`Kawata, which were not previously considered by the Office. See §§ IV, V, VI,
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`infra. And, in co-pending litigation against Qualcomm, Apple has asserted as a
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`matter of claim construction that the ’905 Patent claims should be construed such
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`that any supply voltage to the logic circuit or memory circuit is received on an input
`
`to the integrated circuit, even if the supply voltage is generated, supplied, input, and
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`received from within the integrated circuit. See § V.C, infra.
`
`Because the Challenged Claims are unpatentable, IPR should be instituted and
`
`the Challenged Claims should be cancelled.
`
`II. Mandatory Notices
` Real Party in Interest (37 C.F.R. § 42.8(b)(1))
`Qualcomm Inc. and Qualcomm Technologies, Inc. are the real parties-in-
`
`interest.
`
` Related Matters (37 C.F.R. § 42.8(b)(2))
`The ’905 Patent is involved in the following proceeding that may affect, or be
`
`affected by, a decision in this proceeding: Qualcomm Inc. v. Apple Inc., No. 3:17-
`
`cv-1375 (S.D. Cal.) (“’1375 Case”). The ’905 Patent was previously involved in the
`
`following proceeding: Nokia Corp. v. Apple Inc., No. 3:10-cv-249 (W.D. Wis.).
`
`Additionally, Qualcomm is concurrently filing separate petitions challenging claims
`
`of U.S. Patent Nos. 7,760,559 and 8,098,534, which are in the same family, and
`
`share a specification with, the ’905 Patent.
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` Lead and Back-Up Counsel and Service Information (37 C.F.R.
`§ 42.8(b)(3) and (b)(4))
`Lead Counsel
`John A. Marlott
`Reg. No. 37,031
`JONES DAY
`77 West Wacker, Suite 3500
`Chicago, Illinois 60601-1692
`(312) 269-4236
`jamarlott@jonesday.com
`
`Back-up Counsel
`Matthew W. Johnson
`Reg. No. 59,108
`JONES DAY
`500 Grant Street, Suite 4500
`Pittsburgh, Pennsylvania 15219-2514
`(412) 394-9524
`mwjohnson@jonesday.com
`
`John M. Michalik
`Reg. No. 56,914
`JONES DAY
`77 West Wacker, Suite 3500
`Chicago, Illinois 60601-1692
`(312) 269-4215
`jmichalik@jonesday.
`
`Thomas W. Ritchie
`Reg. No. 65,505
`JONES DAY
`77 West Wacker, Suite 3500
`Chicago, Illinois 60601-1692
`(312) 269-4003
`twritchie@jonesday.com
`
`Pursuant to 37 C.F.R. § 42.10(b), a power of attorney accompanies this
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`petition. Please address all correspondence to lead and back-up counsel at the
`
`addresses above. Qualcomm consents to electronic service by email at the email
`
`addresses listed above.
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`Fees (37 C.F.R. § 42.103)
`The undersigned representative of Qualcomm authorizes the Board to charge
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`the $15,500 petition fee, as well as any additional fees, to Deposit Account 501432,
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`ref: 178774-680002. Five claims are being reviewed, so $15,000 in post institution
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`fees are due for a total of $30,500.
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`III. Grounds for Standing Pursuant to (37 C.F.R. § 104(a))
`Qualcomm certifies that the ’905 Patent is available for IPR and that
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`Qualcomm is not barred or estopped from requesting IPR of the Challenged Claims
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`on the grounds identified in this petition. Apple filed and served its first amended
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`answer and counterclaims in the ’1375 Case, first asserting infringement of the ’905
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`Patent by Qualcomm, on November 29, 2017. Qualcomm has filed this petition
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`within one year of service of Apple’s first amended answer and counterclaims, and
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`shortly after the District Court issued a claim construction order adopting certain of
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`Apple’s positions regarding the breadth of the ’905 Patent claims.
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`IV. Statement of Precise Relief Requested for Each Challenged Claim
` The Claims for Which Review Is Requested (37 C.F.R. §
`42.104(b)(1))
`Qualcomm requests review and cancellation of claims 1–4 and 13 of the ’905
`
`Patent (the “Challenged Claims”).
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`The Specific Statutory Grounds on Which the Challenge is Based
`and Prior Art Relied Upon for Each Ground (37 C.F.R. § 42.104(b)(2))
`Qualcomm requests IPR of the Challenged Claims on the grounds set forth
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`below and requests that each Challenged Claim be found unpatentable and
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`cancelled. An explanation of how the Challenged Claims are unpatentable is
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`provided in the form of the detailed description that follows, which indicates where
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`each of the claim elements can be found in, and the relevance of, the prior art.
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`Additional explanation and support for each ground is set forth in Ex. 1002
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`(Declaration of Lawrence T. Clark, Ph.D.) referenced throughout this petition.
`
`Ground
`Ground 1
`
`
`Ground 2
`
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`Claims
`1–4, 13
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`1–4
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`
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`Basis
`35 U.S.C. § 102 based on U.S. Patent No.
`6,650,589 to Clark (“Clark”)
`
`35 U.S.C. § 102 based on U.S. Patent No.
`6,920,071 to Kawata et al. (“Kawata”)
`
`
`The ’905 Patent issued on April 8, 2008, from U.S. Application No.
`
`11/173,565, which was filed on July 1, 2005, and does not claim priority to any
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`earlier-filed patent application. Accordingly, the effective filing date of the ’905
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`Patent is July 1, 2005.
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`Clark was filed on November 29, 2001, issued on November 18, 2003, and is
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`prior art under pre-AIA 35 U.S.C. § 102(a)-(b).
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`Kawata was filed on May 14, 2004, published on January 6, 2005, as U.S.
`
`Patent Application Publication No. 2005/0002224, issued on July 19, 2005, and is
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`prior art under pre-AIA 35 U.S.C. § 102(a), (e).
`
`V. Reasons for the Relief Requested Under 37 C.F.R. §§ 42.22(a)(2) and
`42.104(b)(4)
` Overview of the ’905 Patent and its Technology
`The ’905 Patent is entitled “Integrated Circuit with Separate Supply Voltage
`
`for Memory that is Different From Logic Circuit Supply Voltage.” Ex. 1001, [54].
`
`The ’905 Patent is related to “an integrated circuit compris[ing] at least one logic
`
`circuit supplied by a first supply voltage and at least one memory circuit coupled to
`
`the logic circuit and supplied by a second supply voltage.” Id., [57]. This
`
`arrangement is shown by the embodiment of Figure 1 (with coloring annotations
`
`added):
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`“[A] block diagram of . . . an integrated circuit 10 is shown” above, with the
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`boundary of the integrated circuit annotated in blue. Id., 2:49–50. “[T]he integrated
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`circuit includes a plurality of logic circuits 12 and a plurality of memory circuits 14”
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`that are coupled together. Id., 2:51–53.
`
`As shown by the yellow annotation, “[t]he logic circuits 12 are powered by a
`
`first supply voltage provided to the integrated circuit 10 (labeled VL in FIG. 1).” Id.,
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`2:53–55. As shown by the green annotation, “[t]he memory circuits 14 are powered
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`by a second power supply voltage provided to the integrated circuit 10 (labeled VM
`
`in FIG. 1).” Id., 2:56–58. Thus, the second supply voltage (VM) supplied to the
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`memory circuits 14 is different from the first supply voltage (VL) supplied to the
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`logic circuits 12. Ex. 1002 ¶¶ 34–35.
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`In this embodiment, the first supply voltage (VL) is also supplied to the
`
`memory circuits 14, as shown by the yellow annotation extending to memory
`
`circuits 14. Ex. 1001, 2:58–60. But the first supply voltage (VL) need not be
`
`supplied to the memory circuits 14 in all embodiments. See Ex. 1002 ¶¶ 111–115,
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`237–239 (dependent claim 2). The ’905 Patent describes this as a feature of “certain
`
`embodiments.” Ex. 1001, 2:58–60. For example, independent claim 1 lacks this
`
`element, but it is required by dependent claim 2 as well as several other dependent
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`claims reciting that different subcomponents of the memory circuit receive the first
`
`supply voltage (e.g., claims 7–12).
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`The ’905 Patent states that “logic circuits 12 may generally implement the
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`operation for which the integrated circuit is designed,” which may involve
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`“generat[ing] various values during operation,” storing values in the memory
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`circuits, and “read[ing] various values from the memory circuits 14 on which to
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`operate.” Id., 2:64–3:2.
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`The ’905 Patent states that memory circuits 14 store data. “For example, . . .
`
`the memory circuits 14 may include memory used for caches, register files,
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`integrated-circuit-specific data structures, etc.” Id., 3:2–5. “The memory circuits 14
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`may implement any type of readable/writable memory,” including, for example,
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`static random access memory (SRAM). Id., 3:5–8. But the memory circuits of the
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`’905 Patent include more than just memory. Ex. 1002 ¶¶ 37–39, 90, 223. As shown
`
`in the memory circuit of Figure 2, for example, the memory circuit may include a
`
`level shifter circuit 20, word line driver circuits 22, and other circuits in addition to
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`memory array 24 where data is stored. Ex. 1001, 3:45–51, Fig. 2. As shown in
`
`Figure 3, the memory circuits (which include the memory array) may include bit line
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`driver circuits 30, memory cells 32A-32N, bit line precharge circuits 34, bit line hold
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`circuits 36, and senseamps 38. Id., 6:38-41, Fig. 3.
`
`The circuit elements shown in Figures 2 and 3 as part of the illustrated
`
`embodiment of the memory circuit from Figure 1 were conventional and well-
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`known at the filing date of the ’905 Patent. See Ex. 1002 ¶¶ 86, 91, 99–100, 117,
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`119, 125, 152, 246 (citing Ex. 1013, at 384; Ex. 1014, at 604–05; Ex. 1016, at 313,
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`570, 574–79; Ex. 1017, at 83–90, 144–54; Ex. 1018, at 143–47). Among these
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`conventional circuit elements is a “level shifter circuit 20,” which is “configured to
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`level shift an input signal to produce an output signal” by “changing the high
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`assertion of the signal from one voltage to another.” Ex. 1001, 5:14–17. “Level
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`shifting may be performed in either direction (e.g. the voltage after level shifting
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`may be higher or lower than the voltage before level shifting).” Id., 5:17–20. Two
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`embodiments of level shifter circuit 20 are shown in Figures 4 and 5. Id., 8:39–40,
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`9:59–62, Figs. 4, 5. However, other embodiments are within the scope of the ’905
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`Patent. Ex. 1002 ¶¶ 125, 185, 246 (discussing ’905 Patent and related ’534 Patent);
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`Ex. 1001, 5:27–42, 6:4–7, 6:23–24, 8:21–24, 9:38–39, 10:18–21.
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`The word line drivers 22 are a second example of conventional circuit
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`elements that may form part of the memory circuit. Ex. 1002 ¶¶ 52, 99, 117 (citing
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`Ex. 1016, at 563–80; Ex. 1017, at 144–54; Ex. 1018, at 143–55). The word line
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`drivers 22 generate a set of word line signals to memory array 24. Ex. 1001, 3:64–
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`66.
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`A third conventional circuit element of memory circuits 14 is memory array
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`24. See Ex. 1002 ¶¶ 52, 91, 152 (discussing ’905 Patent and related ’559 Patent and
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`citing Ex. 1016, at 563–80; Ex. 1018, at 143–55). Figure 3 of the ’905 Patent shows
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`“a circuit diagram of a portion of one embodiment of the memory array 24” of the
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`memory circuit (as shown in Figure 2), which consists of additional conventional
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`circuit elements. See Ex. 1001, 6:32–8:38, Fig. 3. Among these conventional circuit
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`elements is a “bit line precharge circuit 34,” which precharges bit lines in
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`preparation for read operations. See id., 6:38–41, 7:40–57; Ex. 1002 ¶¶ 7, 52, 101,
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`117 (discussing ’905 Patent and citing Ex. 1016, at 563–80; Ex. 1017, at 144–51,
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`164; Ex. 1018, at 143–55). “The memory cells 32A-32N [of memory array 24] are
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`supplied with the [second] VM supply voltage” and can be a “typical CMOS SRAM
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`cell.” Ex. 1001, 6:41–42, 6:61–64.
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`By supplying the memory circuit 14 (and its memory array 24) with a supply
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`voltage (VM) that is different than the supply voltage (VL) supplied to the logic
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`circuit 12, these two supply voltages can differ for each type of circuit. Id., 3:22–36;
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`Ex. 1002 ¶¶ 31–34. The logic circuit supply voltage (VL) can be decreased below
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`that of the memory circuit supply voltage (VM) while ensuring that the memory
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`circuit 14 still has a higher supply voltage (VM) that is sufficient for the memory to
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`remain stable. Ex. 1001, 3:22–36; Ex. 1002 ¶¶ 31–34.
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`As discussed herein, a POSITA would have known at the time of the ’905
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`Patent’s filing that, all things being equal, a circuit’s power consumption can be
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`reduced by reducing the supply voltage to that circuit. See Ex. 1002 ¶¶ 53–56; see
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`also Ex. 1001, 1:28–39. A POSITA would also have known at the time of the ’905
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`Patent’s filing that memory can become unreliable if it is supplied by a voltage that
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`is too low for the circuit’s design. See Ex. 1002 ¶¶ 50–56; see also Ex. 1001, 1:40–
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`67. And, a POSITA would have known before the ’905 Patent’s filing that the
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`minimum usable voltage for a common supply voltage shared by logic and memory
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`circuits is dependent on the memory circuit. Ex. 1002 ¶¶ 50–56; see also Ex. 1001,
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`1:63–67. Thus, in order to reduce the power consumed by logic circuitry through
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`reduction of its supply voltage, it was known to a POSITA, and disclosed in the
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`prior art (including Clark and Kawata), to use two different supply voltages to
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`supply logic circuitry and memory circuitry, respectively. See § VI, infra.
`
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`The Prosecution History of the ’905 Patent
`As originally filed, claim 1 in the application that issued as the ’905 Patent
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`recited an “integrated circuit” comprising “at least one logic circuit supplied by a
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`first supply voltage,” “at least one memory circuit coupled to the logic circuit and
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`supplied by a second supply voltage,” as well as other elements. Ex. 1006, at 25.
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`Claim 13 recited a method comprising a logic circuit and memory cell performing
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`certain steps, with the logic circuit and memory cell similarly supplied by different
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`supply voltages. Id., at 27. The Examiner initially rejected these and all other
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`pending claims as anticipated under pre-AIA 35 U.S.C. § 102(e) by U.S. Patent No.
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`7,120,061 to Daga (“Daga”). Id., at 80–84.
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`1.
`The Daga Patent
`Figure 3 of Daga is reproduced below, with coloring annotations added.
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`Figure 3 shows a system-on-a-chip 300 having circuitry supplied by two supply
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`voltages, ExtVDD and RegVDD. Ex. 1005, 3:13–24, Fig. 3. RegVDD is a first supply
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`voltage of “for example 1.8V,” which is generated on system-on-chip 300 by
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`voltage regulator 315 and “applied to . . . advanced logic 335” such as the
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`microcontroller 335 shown in Figure 3. Id., 3:18–23, Fig. 3. ExtVDD is a second
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`supply voltage, “for example 3.3V or 5V,” which is “applied to memory 340.” Id.,
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`3:16–18, 3:23–24, Fig. 3.
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`2.
`The Claim Amendments to Attempt to Overcome Daga
`The applicants responded to the Examiner’s rejection based on Daga by
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`amending the claims in two ways. First, they amended independent claims 1 and 13
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`of the ’905 Patent application to require that the first supply voltage be “received on
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`a first input to the integrated circuit” and the second supply voltage be “received on
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`a second input to the integrated circuit.” Ex. 1006, at 97, 99. The applicants relied
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`on these claim amendments in their remarks, explaining that “Daga’s integrated
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`circuit has only one power supply input to the integrated circuit (ExtVDD, see Fig.
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`3).” Id., at 103. The applicants further argued: “Thus, Daga fails to anticipate ‘a
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`first supply voltage received on a first input to the integrated circuit; and . . . a
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`second supply voltage received on a second input to the integrated circuit’ as recited
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`in claim 1.” Id. (emphasis by applicants in original).
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`Second, the applicants amended independent claims 1 and 13 to recite that the
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`memory circuit includes a memory array, and the memory array is “continuously
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`supplied by the second supply voltage during use.” Id., at 97, 99. The applicants
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`relied on this new “continuously supplied” language to distinguish their claims from
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`Daga’s disclosures. Specifically, this language was used to distinguish prior art,
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`such as Daga, which uses non-volatile memory. See id., at 102–03; Ex. 1002 ¶ 105.
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`The applicants noted that “Daga teaches a non-volatile memory such as an
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`EEPROM or Flash memory (see, e.g., Daga, col. 3, lines 20-24)” and argued that
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`“[i]n such memories, the memory array does not include memory cells that are
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`continuously supplied with a supply voltage during use.” Ex. 1006, at 102
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`(emphasis by applicants in original). Instead, “the memory arrays are designed to
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`retain values without any power applied (hence the ‘nonvolatile’ nature of such
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`cells).” Id.
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`The applicants referred to Figure 4 in Daga (reproduced below) to further
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`explain this second argument. Id. Figure 4 “is a schematic diagram illustrating one
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`embodiment of the memory from FIG. 3.” Ex. 1005, 2:62–63. The applicants
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`specifically pointed to memory array 430 and argued there are no power supply
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`inputs to the memory array. Ex. 1006, at 102.
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`In comparison, Figure 3 of the ’905 Patent, which “is a circuit diagram of one
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`embodiment of a memory array shown in FIG. 2,” shows that “[t]he memory cells
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`32A-32N are supplied with the VM supply voltage.” Ex. 1001, 2:26–27, 6:41–42,
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`Fig. 3.
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`Based on these claim amendments and two distinguishing arguments
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`regarding the necessity of: (1) two, distinct power supply inputs to the integrated
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`circuit; and (2) memory cells continuously supplied with a supply voltage during
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`use, the Examiner allowed independent claims 1 and 13 (and the corresponding
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`dependent claims) in the form as issued in the ’905 Patent. See Ex. 1006, at 112.
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`37 C.F.R. § 42.104(b)(3): Claim Construction
`1.
`A Person of Ordinary Skill in the Art
`Qualcomm maintains that a POSITA, as of July 1, 2005, would have had a
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`master’s degree in electrical engineering or computer engineering or at least four
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`years of experience in the field of integrated circuit SRAM design, or an equivalent
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`combination of education and experience in this field. Ex. 1002 ¶¶ 46–49.
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`2.
`Construction of Claim Terms
`In this IPR, the claims of the ’905 Patent “shall be given [their] broadest
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`reasonable construction in light of the [’905 Patent’s] specification.” 37 C.F.R.
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`§ 42.100(b). Because a district court applies a different standard, the claim
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`constructions presented in this petition do not necessarily reflect the constructions
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`that Petitioners believe should be adopted by a district court.
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`In the ’1375 Case, the District Court adopted certain of Apple’s claim
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`construction positions. Ex. 1012 (Order Construing Claims), at 3–5. Petitioners
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`have submitted the District Court’s claim construction decision for the Board’s
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`consideration. Power Integrations, Inc. v. Lee, 797 F.3d 1318, 1326–27 (Fed. Cir.
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`2015) (“The fact that the board is not generally bound by a previous judicial
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`interpretation of a disputed claim term does not mean, however, that it has no
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`obligation to acknowledge that interpretation or to assess whether it is consistent
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`with the broadest reasonable construction of the term.”). Although Petitioners
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`reserve the right to appeal or otherwise challenge the District Court’s claim
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`construction order, Petitioners request that the Board in this IPR construe any claim
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`terms at least as broad as the District Court. See, e.g., Cisco Sys., Inc. v. Crossroads
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`Sys., Inc., IPR2014-01463, Final Written Decision, Paper 49, at 11–12 (PTAB, Mar.
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`16, 2016) (“Petitioners argue that the ‘control access’ limitations ‘should be at least
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`as broad as the District Court’s construction . . . .’ We agree with Petitioners . . . .”).
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`(a)
`“integrated circuit”
`In the ’1375 Case, Apple construed “integrated circuit” to mean “one or more
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`circuit elements that are integrated onto a single semiconductor substrate,” and
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`argued that the claimed “integrated circuit” is not limited to a “chip” or any
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`particular combination of connected circuit elements on a semiconductor substrate.
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`Ex. 1007, at 3–4; Ex. 1008, at 1–2; Ex. 1009, at 4–13, 25–27; Ex. 1010 ¶¶ 23–35;
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`Ex. 1011, at 59–98, 116–18. Apple’s construction does not exclude from the scope
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`of “integrated circuit” a subset of the circuit elements integrated onto a single
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`semiconductor substrate. Ex. 1002 ¶ 58. The District Court adopted Apple’s
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`proposed construction. Ex. 1012, at 3. For purposes of this IPR, Petitioners
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`maintain that Apple’s construction should be accepted as the broadest reasonable
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`interpretation.
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`(b)
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`“received on a first / second input to the integrated
`circuit”
`In the ’1375 Case, Apple argued that “received on a first input to the
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`integrated circuit” and “received on a second input to the integrated circuit” mean
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`“provided to the integrated circuit on a first input” and “provided to the integrated
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`circuit on a second input,” respectively. Ex. 1007, at 4–5; Ex. 1008, at 2; Ex. 1009,
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`at 27–33, 37–39; Ex. 1010 ¶¶ 36–44; Ex. 1011, at 118–145. In particular, Apple
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`argued that there is no requirement that the first and second supply voltages must be
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`generated externally to the integrated circuit and connected to the integrated circuit.
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`See id. Instead, Apple argued that a supply voltage connected anywhere within the
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`integrated circuit, regardless of whether it is generated externally to the integrated
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`circuit, is received on an input to the integrated circuit. The District Court construed
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`these terms according to their plain and ordinary meaning. Ex. 1012, at 4–5. I